2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
10 #include "ls2080a_common.h"
12 #undef CONFIG_CONS_INDEX
13 #define CONFIG_CONS_INDEX 2
15 #define I2C_MUX_CH_VOL_MONITOR 0xa
16 #define I2C_VOL_MONITOR_ADDR 0x38
17 #define CONFIG_VOL_MONITOR_IR36021_READ
18 #define CONFIG_VOL_MONITOR_IR36021_SET
20 #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
21 #ifndef CONFIG_SPL_BUILD
24 /* step the IR regulator in 5mV increments */
25 #define IR_VDD_STEP_DOWN 5
26 #define IR_VDD_STEP_UP 5
27 /* The lowest and highest voltage allowed for LS2080ARDB */
28 #define VDD_MV_MIN 819
29 #define VDD_MV_MAX 1212
32 unsigned long get_board_sys_clk(void);
35 #define CONFIG_SYS_FSL_CLK
36 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
37 #define CONFIG_DDR_CLK_FREQ 133333333
38 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
40 #define CONFIG_DDR_SPD
41 #define CONFIG_DDR_ECC
42 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
43 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
44 #define SPD_EEPROM_ADDRESS1 0x51
45 #define SPD_EEPROM_ADDRESS2 0x52
46 #define SPD_EEPROM_ADDRESS3 0x53
47 #define SPD_EEPROM_ADDRESS4 0x54
48 #define SPD_EEPROM_ADDRESS5 0x55
49 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
50 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
51 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
52 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
53 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
54 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
55 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
57 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
61 #define CONFIG_SCSI_AHCI
62 #define CONFIG_SCSI_AHCI_PLAT
64 #define CONFIG_DOS_PARTITION
65 #define CONFIG_BOARD_LATE_INIT
67 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
68 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
70 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
71 #define CONFIG_SYS_SCSI_MAX_LUN 1
72 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
73 CONFIG_SYS_SCSI_MAX_LUN)
74 #define CONFIG_PARTITION_UUIDS
75 #define CONFIG_EFI_PARTITION
76 #define CONFIG_CMD_GPT
78 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
80 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
81 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
82 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
84 #define CONFIG_SYS_NOR0_CSPR \
85 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
89 #define CONFIG_SYS_NOR0_CSPR_EARLY \
90 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
94 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
95 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
96 FTIM0_NOR_TEADC(0x5) | \
98 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
99 FTIM1_NOR_TRAD_NOR(0x1a) |\
100 FTIM1_NOR_TSEQRAD_NOR(0x13))
101 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
102 FTIM2_NOR_TCH(0x4) | \
103 FTIM2_NOR_TWPH(0x0E) | \
105 #define CONFIG_SYS_NOR_FTIM3 0x04000000
106 #define CONFIG_SYS_IFC_CCR 0x01000000
108 #ifndef CONFIG_SYS_NO_FLASH
109 #define CONFIG_FLASH_CFI_DRIVER
110 #define CONFIG_SYS_FLASH_CFI
111 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
112 #define CONFIG_SYS_FLASH_QUIET_TEST
113 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
117 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
118 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
120 #define CONFIG_SYS_FLASH_EMPTY_INFO
121 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
122 CONFIG_SYS_FLASH_BASE + 0x40000000}
125 #define CONFIG_NAND_FSL_IFC
126 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
127 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
129 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
130 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
131 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
132 | CSPR_MSEL_NAND /* MSEL = NAND */ \
134 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
136 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
137 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
138 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
139 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
140 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
141 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
142 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
144 #define CONFIG_SYS_NAND_ONFI_DETECTION
146 /* ONFI NAND Flash mode0 Timing Params */
147 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
148 FTIM0_NAND_TWP(0x30) | \
149 FTIM0_NAND_TWCHT(0x0e) | \
150 FTIM0_NAND_TWH(0x14))
151 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
152 FTIM1_NAND_TWBE(0xab) | \
153 FTIM1_NAND_TRR(0x1c) | \
154 FTIM1_NAND_TRP(0x30))
155 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
156 FTIM2_NAND_TREH(0x14) | \
157 FTIM2_NAND_TWHRE(0x3c))
158 #define CONFIG_SYS_NAND_FTIM3 0x0
160 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
161 #define CONFIG_SYS_MAX_NAND_DEVICE 1
162 #define CONFIG_MTD_NAND_VERIFY_WRITE
163 #define CONFIG_CMD_NAND
165 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
167 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
168 #define QIXIS_LBMAP_SWITCH 0x06
169 #define QIXIS_LBMAP_MASK 0x0f
170 #define QIXIS_LBMAP_SHIFT 0
171 #define QIXIS_LBMAP_DFLTBANK 0x00
172 #define QIXIS_LBMAP_ALTBANK 0x04
173 #define QIXIS_LBMAP_NAND 0x09
174 #define QIXIS_RST_CTL_RESET 0x31
175 #define QIXIS_RST_CTL_RESET_EN 0x30
176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
177 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
179 #define QIXIS_RCW_SRC_NAND 0x119
180 #define QIXIS_RST_FORCE_MEM 0x01
182 #define CONFIG_SYS_CSPR3_EXT (0x0)
183 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
187 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
192 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
193 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
194 /* QIXIS Timing parameters for IFC CS3 */
195 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
196 FTIM0_GPCM_TEADC(0x0e) | \
197 FTIM0_GPCM_TEAHC(0x0e))
198 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
199 FTIM1_GPCM_TRAD(0x3f))
200 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
201 FTIM2_GPCM_TCH(0xf) | \
202 FTIM2_GPCM_TWP(0x3E))
203 #define CONFIG_SYS_CS3_FTIM3 0x0
205 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
206 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
207 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
208 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
209 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
210 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
211 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
212 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
213 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
214 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
215 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
216 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
217 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
218 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
219 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
220 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
221 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
222 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
224 #define CONFIG_ENV_IS_IN_NAND
225 #define CONFIG_ENV_OFFSET (2048 * 1024)
226 #define CONFIG_ENV_SECT_SIZE 0x20000
227 #define CONFIG_ENV_SIZE 0x2000
228 #define CONFIG_SPL_PAD_TO 0x80000
229 #define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
230 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
232 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
233 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
234 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
235 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
236 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
237 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
238 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
239 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
240 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
241 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
242 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
243 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
244 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
245 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
246 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
247 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
248 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
250 #define CONFIG_ENV_IS_IN_FLASH
251 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
252 #define CONFIG_ENV_SECT_SIZE 0x20000
253 #define CONFIG_ENV_SIZE 0x2000
256 /* Debug Server firmware */
257 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
258 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
260 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
265 #define I2C_MUX_PCA_ADDR 0x75
266 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
268 /* I2C bus multiplexer */
269 #define I2C_MUX_CH_DEFAULT 0x8
272 #ifdef CONFIG_FSL_DSPI
273 #define CONFIG_SPI_FLASH
274 #define CONFIG_SPI_FLASH_BAR
275 #define CONFIG_SPI_FLASH_STMICRO
282 #define CONFIG_RTC_DS3231 1
283 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
284 #define CONFIG_CMD_DATE
287 #define CONFIG_ID_EEPROM
288 #define CONFIG_CMD_EEPROM
289 #define CONFIG_SYS_I2C_EEPROM_NXID
290 #define CONFIG_SYS_EEPROM_BUS_NUM 0
291 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
292 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
293 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
296 #define CONFIG_FSL_MEMAC
299 #define CONFIG_PCI_SCAN_SHOW
300 #define CONFIG_CMD_PCI
305 #define CONFIG_FSL_ESDHC
306 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
307 #define CONFIG_GENERIC_MMC
308 #define CONFIG_DOS_PARTITION
311 #define CONFIG_MISC_INIT_R
316 #define CONFIG_HAS_FSL_XHCI_USB
317 #define CONFIG_USB_XHCI_FSL
318 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
319 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
321 #undef CONFIG_CMDLINE_EDITING
322 #include <config_distro_defaults.h>
324 #define BOOT_TARGET_DEVICES(func) \
327 func(SCSI, scsi, 0) \
329 #include <config_distro_bootcmd.h>
331 /* Initial environment variables */
332 #undef CONFIG_EXTRA_ENV_SETTINGS
333 #define CONFIG_EXTRA_ENV_SETTINGS \
334 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
335 "scriptaddr=0x80800000\0" \
336 "kernel_addr_r=0x81000000\0" \
337 "pxefile_addr_r=0x81000000\0" \
338 "fdt_addr_r=0x88000000\0" \
339 "ramdisk_addr_r=0x89000000\0" \
340 "loadaddr=0x80100000\0" \
341 "kernel_addr=0x100000\0" \
342 "ramdisk_addr=0x800000\0" \
343 "ramdisk_size=0x2000000\0" \
344 "fdt_high=0xa0000000\0" \
345 "initrd_high=0xffffffffffffffff\0" \
346 "kernel_start=0x581100000\0" \
347 "kernel_load=0xa0000000\0" \
348 "kernel_size=0x2800000\0" \
349 "fdtfile=fsl-ls2080a-rdb.dtb\0" \
350 "mcinitcmd=fsl_mc start mc 0x580300000" \
354 #undef CONFIG_BOOTARGS
355 #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \
356 "earlycon=uart8250,mmio,0x21c0600 " \
357 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
358 " hugepagesz=2m hugepages=256"
360 #undef CONFIG_BOOTCOMMAND
361 /* Try to boot an on-NOR kernel first, then do normal distro boot */
362 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
363 " && cp.b $kernel_start $kernel_load $kernel_size" \
364 " && bootm $kernel_load" \
365 " || run distro_bootcmd"
367 /* MAC/PHY configuration */
368 #ifdef CONFIG_FSL_MC_ENET
369 #define CONFIG_PHYLIB_10G
370 #define CONFIG_PHY_AQUANTIA
371 #define CONFIG_PHY_CORTINA
372 #define CONFIG_PHYLIB
373 #define CONFIG_SYS_CORTINA_FW_IN_NOR
374 #define CONFIG_CORTINA_FW_ADDR 0x581000000
375 #define CONFIG_CORTINA_FW_LENGTH 0x40000
377 #define CORTINA_PHY_ADDR1 0x10
378 #define CORTINA_PHY_ADDR2 0x11
379 #define CORTINA_PHY_ADDR3 0x12
380 #define CORTINA_PHY_ADDR4 0x13
381 #define AQ_PHY_ADDR1 0x00
382 #define AQ_PHY_ADDR2 0x01
383 #define AQ_PHY_ADDR3 0x02
384 #define AQ_PHY_ADDR4 0x03
385 #define AQR405_IRQ_MASK 0x36
388 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
389 #define CONFIG_PHY_GIGE
390 #define CONFIG_PHY_AQUANTIA
393 #include <asm/fsl_secure_boot.h>
395 #endif /* __LS2_RDB_H */