1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #define I2C_MUX_CH_VOL_MONITOR 0xa
13 #define I2C_VOL_MONITOR_ADDR 0x38
15 /* step the IR regulator in 5mV increments */
16 #define IR_VDD_STEP_DOWN 5
17 #define IR_VDD_STEP_UP 5
18 /* The lowest and highest voltage allowed for LS2080ARDB */
19 #define VDD_MV_MIN 819
20 #define VDD_MV_MAX 1212
22 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
24 #define SPD_EEPROM_ADDRESS1 0x51
25 #define SPD_EEPROM_ADDRESS2 0x52
26 #define SPD_EEPROM_ADDRESS3 0x53
27 #define SPD_EEPROM_ADDRESS4 0x54
28 #define SPD_EEPROM_ADDRESS5 0x55
29 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
30 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
32 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
34 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
35 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
36 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
38 #define CFG_SYS_NOR0_CSPR \
39 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
43 #define CFG_SYS_NOR0_CSPR_EARLY \
44 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
48 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
49 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
50 FTIM0_NOR_TEADC(0x5) | \
52 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
53 FTIM1_NOR_TRAD_NOR(0x1a) |\
54 FTIM1_NOR_TSEQRAD_NOR(0x13))
55 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
56 FTIM2_NOR_TCH(0x4) | \
57 FTIM2_NOR_TWPH(0x0E) | \
59 #define CFG_SYS_NOR_FTIM3 0x04000000
60 #define CFG_SYS_IFC_CCR 0x01000000
62 #ifdef CONFIG_MTD_NOR_FLASH
63 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
64 CFG_SYS_FLASH_BASE + 0x40000000}
67 #define CFG_SYS_NAND_CSPR_EXT (0x0)
68 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
69 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
70 | CSPR_MSEL_NAND /* MSEL = NAND */ \
72 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
74 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
75 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
76 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
77 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
78 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
79 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
80 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
82 /* ONFI NAND Flash mode0 Timing Params */
83 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
84 FTIM0_NAND_TWP(0x30) | \
85 FTIM0_NAND_TWCHT(0x0e) | \
87 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
88 FTIM1_NAND_TWBE(0xab) | \
89 FTIM1_NAND_TRR(0x1c) | \
91 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
92 FTIM2_NAND_TREH(0x14) | \
93 FTIM2_NAND_TWHRE(0x3c))
94 #define CFG_SYS_NAND_FTIM3 0x0
96 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
98 #define QIXIS_LBMAP_SWITCH 0x06
99 #define QIXIS_LBMAP_MASK 0x0f
100 #define QIXIS_LBMAP_SHIFT 0
101 #define QIXIS_LBMAP_DFLTBANK 0x00
102 #define QIXIS_LBMAP_ALTBANK 0x04
103 #define QIXIS_LBMAP_NAND 0x09
104 #define QIXIS_RST_CTL_RESET 0x31
105 #define QIXIS_RST_CTL_RESET_EN 0x30
106 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
107 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
108 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
109 #define QIXIS_RCW_SRC_NAND 0x119
110 #define QIXIS_RST_FORCE_MEM 0x01
112 #define CFG_SYS_CSPR3_EXT (0x0)
113 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
117 #define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
122 #define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
123 #define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
124 /* QIXIS Timing parameters for IFC CS3 */
125 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
126 FTIM0_GPCM_TEADC(0x0e) | \
127 FTIM0_GPCM_TEAHC(0x0e))
128 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
129 FTIM1_GPCM_TRAD(0x3f))
130 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
131 FTIM2_GPCM_TCH(0xf) | \
132 FTIM2_GPCM_TWP(0x3E))
133 #define CFG_SYS_CS3_FTIM3 0x0
135 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
136 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
137 #define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR_EARLY
138 #define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR0_CSPR
139 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
140 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
141 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
142 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
143 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
144 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
145 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
146 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
147 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
148 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
149 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
150 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
151 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
152 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
154 #define CFG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
156 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
157 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
158 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
159 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
160 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
161 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
162 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
163 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
164 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
165 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
166 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
167 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
168 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
169 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
170 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
171 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
172 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
175 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
177 #ifdef CONFIG_TARGET_LS2081ARDB
178 #define QIXIS_QMAP_MASK 0x07
179 #define QIXIS_QMAP_SHIFT 5
180 #define QIXIS_LBMAP_DFLTBANK 0x00
181 #define QIXIS_LBMAP_QSPI 0x00
182 #define QIXIS_RCW_SRC_QSPI 0x62
183 #define QIXIS_LBMAP_ALTBANK 0x20
184 #define QIXIS_RST_CTL_RESET 0x31
185 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
186 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
187 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
188 #define QIXIS_LBMAP_MASK 0x0f
189 #define QIXIS_RST_CTL_RESET_EN 0x30
195 #ifdef CONFIG_TARGET_LS2081ARDB
196 #define CFG_SYS_I2C_FPGA_ADDR 0x66
198 #define I2C_MUX_PCA_ADDR 0x75
199 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
201 /* I2C bus multiplexer */
202 #define I2C_MUX_CH_DEFAULT 0x8
209 #ifdef CONFIG_TARGET_LS2081ARDB
210 #define CFG_SYS_I2C_RTC_ADDR 0x51
212 #define CFG_SYS_I2C_RTC_ADDR 0x68
215 #define BOOT_TARGET_DEVICES(func) \
218 func(SCSI, scsi, 0) \
220 #include <config_distro_bootcmd.h>
222 #ifdef CONFIG_TFABOOT
223 #define QSPI_MC_INIT_CMD \
225 "sf read 0x80640000 0x640000 0x80000; " \
226 "env exists secureboot && " \
227 "esbc_validate 0x80640000 && " \
228 "esbc_validate 0x80680000; " \
229 "sf read 0x80a00000 0xa00000 0x200000; " \
230 "sf read 0x80e00000 0xe00000 0x100000; " \
231 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
232 #define SD_MC_INIT_CMD \
233 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
234 "mmc read 0x80e00000 0x7000 0x800;" \
235 "env exists secureboot && " \
236 "mmc read 0x80640000 0x3200 0x20 && " \
237 "mmc read 0x80680000 0x3400 0x20 && " \
238 "esbc_validate 0x80640000 && " \
239 "esbc_validate 0x80680000 ;" \
240 "fsl_mc start mc 0x80a00000 0x80e00000\0"
241 #define IFC_MC_INIT_CMD \
242 "env exists secureboot && " \
243 "esbc_validate 0x580640000 && " \
244 "esbc_validate 0x580680000; " \
245 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
247 #ifdef CONFIG_QSPI_BOOT
248 #define MC_INIT_CMD \
249 "mcinitcmd=sf probe 0:0; " \
250 "sf read 0x80640000 0x640000 0x80000; " \
251 "env exists secureboot && " \
252 "esbc_validate 0x80640000 && " \
253 "esbc_validate 0x80680000; " \
254 "sf read 0x80a00000 0xa00000 0x200000; " \
255 "sf read 0x80e00000 0xe00000 0x100000; " \
256 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
257 #elif defined(CONFIG_SD_BOOT)
258 #define MC_INIT_CMD \
259 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
260 "mmc read 0x80e00000 0x7000 0x800;" \
261 "env exists secureboot && " \
262 "mmc read 0x80640000 0x3200 0x20 && " \
263 "mmc read 0x80680000 0x3400 0x20 && " \
264 "esbc_validate 0x80640000 && " \
265 "esbc_validate 0x80680000 ;" \
266 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
267 "mcmemsize=0x70000000\0"
269 #define MC_INIT_CMD \
270 "mcinitcmd=env exists secureboot && " \
271 "esbc_validate 0x580640000 && " \
272 "esbc_validate 0x580680000; " \
273 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
277 /* Initial environment variables */
278 #undef CFG_EXTRA_ENV_SETTINGS
279 #ifdef CONFIG_TFABOOT
280 #define CFG_EXTRA_ENV_SETTINGS \
281 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
282 "ramdisk_addr=0x800000\0" \
283 "ramdisk_size=0x2000000\0" \
284 "fdt_high=0xa0000000\0" \
285 "initrd_high=0xffffffffffffffff\0" \
286 "kernel_addr=0x581000000\0" \
287 "kernel_start=0x1000000\0" \
288 "kernelheader_start=0x800000\0" \
289 "scriptaddr=0x80000000\0" \
290 "scripthdraddr=0x80080000\0" \
291 "fdtheader_addr_r=0x80100000\0" \
292 "kernelheader_addr_r=0x80200000\0" \
293 "kernelheader_addr=0x580600000\0" \
294 "kernel_addr_r=0x81000000\0" \
295 "kernelheader_size=0x40000\0" \
296 "fdt_addr_r=0x90000000\0" \
297 "load_addr=0xa0000000\0" \
298 "kernel_size=0x2800000\0" \
299 "kernel_addr_sd=0x8000\0" \
300 "kernel_size_sd=0x14000\0" \
301 "console=ttyAMA0,38400n8\0" \
302 "mcmemsize=0x70000000\0" \
303 "sd_bootcmd=echo Trying load from SD ..;" \
304 "mmcinfo; mmc read $load_addr " \
305 "$kernel_addr_sd $kernel_size_sd && " \
306 "bootm $load_addr#$board\0" \
309 "boot_scripts=ls2088ardb_boot.scr\0" \
310 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
311 "scan_dev_for_boot_part=" \
312 "part list ${devtype} ${devnum} devplist; " \
313 "env exists devplist || setenv devplist 1; " \
314 "for distro_bootpart in ${devplist}; do " \
315 "if fstype ${devtype} " \
316 "${devnum}:${distro_bootpart} " \
317 "bootfstype; then " \
318 "run scan_dev_for_boot; " \
322 "load ${devtype} ${devnum}:${distro_bootpart} " \
323 "${scriptaddr} ${prefix}${script}; " \
324 "env exists secureboot && load ${devtype} " \
325 "${devnum}:${distro_bootpart} " \
326 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
327 "&& esbc_validate ${scripthdraddr};" \
328 "source ${scriptaddr}\0" \
329 "qspi_bootcmd=echo Trying load from qspi..;" \
330 "sf probe && sf read $load_addr " \
331 "$kernel_start $kernel_size ; env exists secureboot &&" \
332 "sf read $kernelheader_addr_r $kernelheader_start " \
333 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
334 " bootm $load_addr#$board\0" \
335 "nor_bootcmd=echo Trying load from nor..;" \
336 "cp.b $kernel_addr $load_addr " \
337 "$kernel_size ; env exists secureboot && " \
338 "cp.b $kernelheader_addr $kernelheader_addr_r " \
339 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
340 "bootm $load_addr#$board\0"
342 #define CFG_EXTRA_ENV_SETTINGS \
343 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
344 "ramdisk_addr=0x800000\0" \
345 "ramdisk_size=0x2000000\0" \
346 "fdt_high=0xa0000000\0" \
347 "initrd_high=0xffffffffffffffff\0" \
348 "kernel_addr=0x581000000\0" \
349 "kernel_start=0x1000000\0" \
350 "kernelheader_start=0x600000\0" \
351 "scriptaddr=0x80000000\0" \
352 "scripthdraddr=0x80080000\0" \
353 "fdtheader_addr_r=0x80100000\0" \
354 "kernelheader_addr_r=0x80200000\0" \
355 "kernelheader_addr=0x580600000\0" \
356 "kernel_addr_r=0x81000000\0" \
357 "kernelheader_size=0x40000\0" \
358 "fdt_addr_r=0x90000000\0" \
359 "load_addr=0xa0000000\0" \
360 "kernel_size=0x2800000\0" \
361 "kernel_addr_sd=0x8000\0" \
362 "kernel_size_sd=0x14000\0" \
363 "console=ttyAMA0,38400n8\0" \
364 "mcmemsize=0x70000000\0" \
365 "sd_bootcmd=echo Trying load from SD ..;" \
366 "mmcinfo; mmc read $load_addr " \
367 "$kernel_addr_sd $kernel_size_sd && " \
368 "bootm $load_addr#$board\0" \
371 "boot_scripts=ls2088ardb_boot.scr\0" \
372 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
373 "scan_dev_for_boot_part=" \
374 "part list ${devtype} ${devnum} devplist; " \
375 "env exists devplist || setenv devplist 1; " \
376 "for distro_bootpart in ${devplist}; do " \
377 "if fstype ${devtype} " \
378 "${devnum}:${distro_bootpart} " \
379 "bootfstype; then " \
380 "run scan_dev_for_boot; " \
384 "load ${devtype} ${devnum}:${distro_bootpart} " \
385 "${scriptaddr} ${prefix}${script}; " \
386 "env exists secureboot && load ${devtype} " \
387 "${devnum}:${distro_bootpart} " \
388 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
389 "env exists secureboot " \
390 "&& esbc_validate ${scripthdraddr};" \
391 "source ${scriptaddr}\0" \
392 "qspi_bootcmd=echo Trying load from qspi..;" \
393 "sf probe && sf read $load_addr " \
394 "$kernel_start $kernel_size ; env exists secureboot &&" \
395 "sf read $kernelheader_addr_r $kernelheader_start " \
396 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
397 " bootm $load_addr#$board\0" \
398 "nor_bootcmd=echo Trying load from nor..;" \
399 "cp.b $kernel_addr $load_addr " \
400 "$kernel_size ; env exists secureboot && " \
401 "cp.b $kernelheader_addr $kernelheader_addr_r " \
402 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
403 "bootm $load_addr#$board\0"
406 #ifdef CONFIG_TFABOOT
407 #define QSPI_NOR_BOOTCOMMAND \
409 "sf read 0x806c0000 0x6c0000 0x40000; " \
410 "env exists mcinitcmd && env exists secureboot "\
411 "&& esbc_validate 0x806c0000; " \
412 "sf read 0x80d00000 0xd00000 0x100000; " \
413 "env exists mcinitcmd && " \
414 "fsl_mc lazyapply dpl 0x80d00000; " \
415 "run distro_bootcmd;run qspi_bootcmd; " \
416 "env exists secureboot && esbc_halt;"
418 /* Try to boot an on-SD kernel first, then do normal distro boot */
419 #define SD_BOOTCOMMAND \
420 "env exists mcinitcmd && env exists secureboot "\
421 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
422 "&& esbc_validate $load_addr; " \
423 "env exists mcinitcmd && run mcinitcmd " \
424 "&& mmc read 0x80d00000 0x6800 0x800 " \
425 "&& fsl_mc lazyapply dpl 0x80d00000; " \
426 "run distro_bootcmd;run sd_bootcmd; " \
427 "env exists secureboot && esbc_halt;"
429 /* Try to boot an on-NOR kernel first, then do normal distro boot */
430 #define IFC_NOR_BOOTCOMMAND \
431 "env exists mcinitcmd && env exists secureboot "\
432 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
433 "&& fsl_mc lazyapply dpl 0x580d00000;" \
434 "run distro_bootcmd;run nor_bootcmd; " \
435 "env exists secureboot && esbc_halt;"
437 #ifdef CONFIG_QSPI_BOOT
438 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
439 #elif defined(CONFIG_SD_BOOT)
440 /* Try to boot an on-SD kernel first, then do normal distro boot */
442 /* Try to boot an on-NOR kernel first, then do normal distro boot */
446 /* MAC/PHY configuration */
447 #define CORTINA_PHY_ADDR1 0x10
448 #define CORTINA_PHY_ADDR2 0x11
449 #define CORTINA_PHY_ADDR3 0x12
450 #define CORTINA_PHY_ADDR4 0x13
451 #define AQ_PHY_ADDR1 0x00
452 #define AQ_PHY_ADDR2 0x01
453 #define AQ_PHY_ADDR3 0x02
454 #define AQ_PHY_ADDR4 0x03
455 #define AQR405_IRQ_MASK 0x36
457 #include <asm/fsl_secure_boot.h>
459 #endif /* __LS2_RDB_H */