1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #ifdef CONFIG_TARGET_LS2081ARDB
14 #define CONFIG_QIXIS_I2C_ACCESS
18 #define I2C_MUX_CH_VOL_MONITOR 0xa
19 #define I2C_VOL_MONITOR_ADDR 0x38
21 /* step the IR regulator in 5mV increments */
22 #define IR_VDD_STEP_DOWN 5
23 #define IR_VDD_STEP_UP 5
24 /* The lowest and highest voltage allowed for LS2080ARDB */
25 #define VDD_MV_MIN 819
26 #define VDD_MV_MAX 1212
28 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
30 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
31 #define SPD_EEPROM_ADDRESS1 0x51
32 #define SPD_EEPROM_ADDRESS2 0x52
33 #define SPD_EEPROM_ADDRESS3 0x53
34 #define SPD_EEPROM_ADDRESS4 0x54
35 #define SPD_EEPROM_ADDRESS5 0x55
36 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
37 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
38 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
39 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
40 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
41 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
42 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
46 #define CONFIG_SCSI_AHCI_PLAT
48 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
49 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
51 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
52 #define CONFIG_SYS_SCSI_MAX_LUN 1
53 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
54 CONFIG_SYS_SCSI_MAX_LUN)
56 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
58 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
59 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
60 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
62 #define CONFIG_SYS_NOR0_CSPR \
63 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
67 #define CONFIG_SYS_NOR0_CSPR_EARLY \
68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
72 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
73 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
74 FTIM0_NOR_TEADC(0x5) | \
76 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
77 FTIM1_NOR_TRAD_NOR(0x1a) |\
78 FTIM1_NOR_TSEQRAD_NOR(0x13))
79 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
80 FTIM2_NOR_TCH(0x4) | \
81 FTIM2_NOR_TWPH(0x0E) | \
83 #define CONFIG_SYS_NOR_FTIM3 0x04000000
84 #define CONFIG_SYS_IFC_CCR 0x01000000
86 #ifdef CONFIG_MTD_NOR_FLASH
87 #define CONFIG_SYS_FLASH_QUIET_TEST
88 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
90 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
91 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
92 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
94 #define CONFIG_SYS_FLASH_EMPTY_INFO
95 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
96 CONFIG_SYS_FLASH_BASE + 0x40000000}
99 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
100 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
102 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
103 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
104 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
105 | CSPR_MSEL_NAND /* MSEL = NAND */ \
107 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
109 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
110 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
111 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
112 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
113 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
114 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
115 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
117 /* ONFI NAND Flash mode0 Timing Params */
118 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
119 FTIM0_NAND_TWP(0x30) | \
120 FTIM0_NAND_TWCHT(0x0e) | \
121 FTIM0_NAND_TWH(0x14))
122 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
123 FTIM1_NAND_TWBE(0xab) | \
124 FTIM1_NAND_TRR(0x1c) | \
125 FTIM1_NAND_TRP(0x30))
126 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
127 FTIM2_NAND_TREH(0x14) | \
128 FTIM2_NAND_TWHRE(0x3c))
129 #define CONFIG_SYS_NAND_FTIM3 0x0
131 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
132 #define CONFIG_SYS_MAX_NAND_DEVICE 1
133 #define CONFIG_MTD_NAND_VERIFY_WRITE
135 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
136 #define QIXIS_LBMAP_SWITCH 0x06
137 #define QIXIS_LBMAP_MASK 0x0f
138 #define QIXIS_LBMAP_SHIFT 0
139 #define QIXIS_LBMAP_DFLTBANK 0x00
140 #define QIXIS_LBMAP_ALTBANK 0x04
141 #define QIXIS_LBMAP_NAND 0x09
142 #define QIXIS_RST_CTL_RESET 0x31
143 #define QIXIS_RST_CTL_RESET_EN 0x30
144 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
145 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
146 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
147 #define QIXIS_RCW_SRC_NAND 0x119
148 #define QIXIS_RST_FORCE_MEM 0x01
150 #define CONFIG_SYS_CSPR3_EXT (0x0)
151 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
155 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
160 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
161 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
162 /* QIXIS Timing parameters for IFC CS3 */
163 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
164 FTIM0_GPCM_TEADC(0x0e) | \
165 FTIM0_GPCM_TEAHC(0x0e))
166 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
167 FTIM1_GPCM_TRAD(0x3f))
168 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
169 FTIM2_GPCM_TCH(0xf) | \
170 FTIM2_GPCM_TWP(0x3E))
171 #define CONFIG_SYS_CS3_FTIM3 0x0
173 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
174 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
175 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
176 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
177 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
178 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
179 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
180 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
181 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
182 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
183 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
184 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
185 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
186 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
187 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
188 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
189 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
190 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
192 #define CONFIG_SPL_PAD_TO 0x80000
193 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
195 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
196 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
197 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
198 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
199 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
200 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
201 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
202 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
203 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
205 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
206 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
207 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
208 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
209 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
210 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
211 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
214 /* Debug Server firmware */
215 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
216 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
218 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
220 #ifdef CONFIG_TARGET_LS2081ARDB
221 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
222 #define QIXIS_QMAP_MASK 0x07
223 #define QIXIS_QMAP_SHIFT 5
224 #define QIXIS_LBMAP_DFLTBANK 0x00
225 #define QIXIS_LBMAP_QSPI 0x00
226 #define QIXIS_RCW_SRC_QSPI 0x62
227 #define QIXIS_LBMAP_ALTBANK 0x20
228 #define QIXIS_RST_CTL_RESET 0x31
229 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
230 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
231 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
232 #define QIXIS_LBMAP_MASK 0x0f
233 #define QIXIS_RST_CTL_RESET_EN 0x30
239 #ifdef CONFIG_TARGET_LS2081ARDB
240 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
242 #define I2C_MUX_PCA_ADDR 0x75
243 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
245 /* I2C bus multiplexer */
246 #define I2C_MUX_CH_DEFAULT 0x8
254 #ifdef CONFIG_TARGET_LS2081ARDB
255 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
257 #define CONFIG_RTC_DS3231 1
258 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
262 #define CONFIG_SYS_I2C_EEPROM_NXID
263 #define CONFIG_SYS_EEPROM_BUS_NUM 0
265 #define CONFIG_FSL_MEMAC
268 #define CONFIG_PCI_SCAN_SHOW
271 #define BOOT_TARGET_DEVICES(func) \
274 func(SCSI, scsi, 0) \
276 #include <config_distro_bootcmd.h>
278 #ifdef CONFIG_TFABOOT
279 #define QSPI_MC_INIT_CMD \
281 "sf read 0x80640000 0x640000 0x80000; " \
282 "env exists secureboot && " \
283 "esbc_validate 0x80640000 && " \
284 "esbc_validate 0x80680000; " \
285 "sf read 0x80a00000 0xa00000 0x200000; " \
286 "sf read 0x80e00000 0xe00000 0x100000; " \
287 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
288 #define SD_MC_INIT_CMD \
289 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
290 "mmc read 0x80e00000 0x7000 0x800;" \
291 "env exists secureboot && " \
292 "mmc read 0x80640000 0x3200 0x20 && " \
293 "mmc read 0x80680000 0x3400 0x20 && " \
294 "esbc_validate 0x80640000 && " \
295 "esbc_validate 0x80680000 ;" \
296 "fsl_mc start mc 0x80a00000 0x80e00000\0"
297 #define IFC_MC_INIT_CMD \
298 "env exists secureboot && " \
299 "esbc_validate 0x580640000 && " \
300 "esbc_validate 0x580680000; " \
301 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
303 #ifdef CONFIG_QSPI_BOOT
304 #define MC_INIT_CMD \
305 "mcinitcmd=sf probe 0:0; " \
306 "sf read 0x80640000 0x640000 0x80000; " \
307 "env exists secureboot && " \
308 "esbc_validate 0x80640000 && " \
309 "esbc_validate 0x80680000; " \
310 "sf read 0x80a00000 0xa00000 0x200000; " \
311 "sf read 0x80e00000 0xe00000 0x100000; " \
312 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
313 #elif defined(CONFIG_SD_BOOT)
314 #define MC_INIT_CMD \
315 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
316 "mmc read 0x80e00000 0x7000 0x800;" \
317 "env exists secureboot && " \
318 "mmc read 0x80640000 0x3200 0x20 && " \
319 "mmc read 0x80680000 0x3400 0x20 && " \
320 "esbc_validate 0x80640000 && " \
321 "esbc_validate 0x80680000 ;" \
322 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
323 "mcmemsize=0x70000000\0"
325 #define MC_INIT_CMD \
326 "mcinitcmd=env exists secureboot && " \
327 "esbc_validate 0x580640000 && " \
328 "esbc_validate 0x580680000; " \
329 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
333 /* Initial environment variables */
334 #undef CONFIG_EXTRA_ENV_SETTINGS
335 #ifdef CONFIG_TFABOOT
336 #define CONFIG_EXTRA_ENV_SETTINGS \
337 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
338 "ramdisk_addr=0x800000\0" \
339 "ramdisk_size=0x2000000\0" \
340 "fdt_high=0xa0000000\0" \
341 "initrd_high=0xffffffffffffffff\0" \
342 "fdt_addr=0x64f00000\0" \
343 "kernel_addr=0x581000000\0" \
344 "kernel_start=0x1000000\0" \
345 "kernelheader_start=0x800000\0" \
346 "scriptaddr=0x80000000\0" \
347 "scripthdraddr=0x80080000\0" \
348 "fdtheader_addr_r=0x80100000\0" \
349 "kernelheader_addr_r=0x80200000\0" \
350 "kernelheader_addr=0x580600000\0" \
351 "kernel_addr_r=0x81000000\0" \
352 "kernelheader_size=0x40000\0" \
353 "fdt_addr_r=0x90000000\0" \
354 "load_addr=0xa0000000\0" \
355 "kernel_size=0x2800000\0" \
356 "kernel_addr_sd=0x8000\0" \
357 "kernel_size_sd=0x14000\0" \
358 "console=ttyAMA0,38400n8\0" \
359 "mcmemsize=0x70000000\0" \
360 "sd_bootcmd=echo Trying load from SD ..;" \
361 "mmcinfo; mmc read $load_addr " \
362 "$kernel_addr_sd $kernel_size_sd && " \
363 "bootm $load_addr#$board\0" \
366 "boot_scripts=ls2088ardb_boot.scr\0" \
367 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
368 "scan_dev_for_boot_part=" \
369 "part list ${devtype} ${devnum} devplist; " \
370 "env exists devplist || setenv devplist 1; " \
371 "for distro_bootpart in ${devplist}; do " \
372 "if fstype ${devtype} " \
373 "${devnum}:${distro_bootpart} " \
374 "bootfstype; then " \
375 "run scan_dev_for_boot; " \
379 "load ${devtype} ${devnum}:${distro_bootpart} " \
380 "${scriptaddr} ${prefix}${script}; " \
381 "env exists secureboot && load ${devtype} " \
382 "${devnum}:${distro_bootpart} " \
383 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
384 "&& esbc_validate ${scripthdraddr};" \
385 "source ${scriptaddr}\0" \
386 "qspi_bootcmd=echo Trying load from qspi..;" \
387 "sf probe && sf read $load_addr " \
388 "$kernel_start $kernel_size ; env exists secureboot &&" \
389 "sf read $kernelheader_addr_r $kernelheader_start " \
390 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
391 " bootm $load_addr#$board\0" \
392 "nor_bootcmd=echo Trying load from nor..;" \
393 "cp.b $kernel_addr $load_addr " \
394 "$kernel_size ; env exists secureboot && " \
395 "cp.b $kernelheader_addr $kernelheader_addr_r " \
396 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
397 "bootm $load_addr#$board\0"
399 #define CONFIG_EXTRA_ENV_SETTINGS \
400 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
401 "ramdisk_addr=0x800000\0" \
402 "ramdisk_size=0x2000000\0" \
403 "fdt_high=0xa0000000\0" \
404 "initrd_high=0xffffffffffffffff\0" \
405 "fdt_addr=0x64f00000\0" \
406 "kernel_addr=0x581000000\0" \
407 "kernel_start=0x1000000\0" \
408 "kernelheader_start=0x600000\0" \
409 "scriptaddr=0x80000000\0" \
410 "scripthdraddr=0x80080000\0" \
411 "fdtheader_addr_r=0x80100000\0" \
412 "kernelheader_addr_r=0x80200000\0" \
413 "kernelheader_addr=0x580600000\0" \
414 "kernel_addr_r=0x81000000\0" \
415 "kernelheader_size=0x40000\0" \
416 "fdt_addr_r=0x90000000\0" \
417 "load_addr=0xa0000000\0" \
418 "kernel_size=0x2800000\0" \
419 "kernel_addr_sd=0x8000\0" \
420 "kernel_size_sd=0x14000\0" \
421 "console=ttyAMA0,38400n8\0" \
422 "mcmemsize=0x70000000\0" \
423 "sd_bootcmd=echo Trying load from SD ..;" \
424 "mmcinfo; mmc read $load_addr " \
425 "$kernel_addr_sd $kernel_size_sd && " \
426 "bootm $load_addr#$board\0" \
429 "boot_scripts=ls2088ardb_boot.scr\0" \
430 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
431 "scan_dev_for_boot_part=" \
432 "part list ${devtype} ${devnum} devplist; " \
433 "env exists devplist || setenv devplist 1; " \
434 "for distro_bootpart in ${devplist}; do " \
435 "if fstype ${devtype} " \
436 "${devnum}:${distro_bootpart} " \
437 "bootfstype; then " \
438 "run scan_dev_for_boot; " \
442 "load ${devtype} ${devnum}:${distro_bootpart} " \
443 "${scriptaddr} ${prefix}${script}; " \
444 "env exists secureboot && load ${devtype} " \
445 "${devnum}:${distro_bootpart} " \
446 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
447 "env exists secureboot " \
448 "&& esbc_validate ${scripthdraddr};" \
449 "source ${scriptaddr}\0" \
450 "qspi_bootcmd=echo Trying load from qspi..;" \
451 "sf probe && sf read $load_addr " \
452 "$kernel_start $kernel_size ; env exists secureboot &&" \
453 "sf read $kernelheader_addr_r $kernelheader_start " \
454 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
455 " bootm $load_addr#$board\0" \
456 "nor_bootcmd=echo Trying load from nor..;" \
457 "cp.b $kernel_addr $load_addr " \
458 "$kernel_size ; env exists secureboot && " \
459 "cp.b $kernelheader_addr $kernelheader_addr_r " \
460 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
461 "bootm $load_addr#$board\0"
464 #ifdef CONFIG_TFABOOT
465 #define QSPI_NOR_BOOTCOMMAND \
467 "sf read 0x806c0000 0x6c0000 0x40000; " \
468 "env exists mcinitcmd && env exists secureboot "\
469 "&& esbc_validate 0x806c0000; " \
470 "sf read 0x80d00000 0xd00000 0x100000; " \
471 "env exists mcinitcmd && " \
472 "fsl_mc lazyapply dpl 0x80d00000; " \
473 "run distro_bootcmd;run qspi_bootcmd; " \
474 "env exists secureboot && esbc_halt;"
476 /* Try to boot an on-SD kernel first, then do normal distro boot */
477 #define SD_BOOTCOMMAND \
478 "env exists mcinitcmd && env exists secureboot "\
479 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
480 "&& esbc_validate $load_addr; " \
481 "env exists mcinitcmd && run mcinitcmd " \
482 "&& mmc read 0x80d00000 0x6800 0x800 " \
483 "&& fsl_mc lazyapply dpl 0x80d00000; " \
484 "run distro_bootcmd;run sd_bootcmd; " \
485 "env exists secureboot && esbc_halt;"
487 /* Try to boot an on-NOR kernel first, then do normal distro boot */
488 #define IFC_NOR_BOOTCOMMAND \
489 "env exists mcinitcmd && env exists secureboot "\
490 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
491 "&& fsl_mc lazyapply dpl 0x580d00000;" \
492 "run distro_bootcmd;run nor_bootcmd; " \
493 "env exists secureboot && esbc_halt;"
495 #ifdef CONFIG_QSPI_BOOT
496 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
497 #elif defined(CONFIG_SD_BOOT)
498 /* Try to boot an on-SD kernel first, then do normal distro boot */
500 /* Try to boot an on-NOR kernel first, then do normal distro boot */
504 /* MAC/PHY configuration */
505 #define CORTINA_PHY_ADDR1 0x10
506 #define CORTINA_PHY_ADDR2 0x11
507 #define CORTINA_PHY_ADDR3 0x12
508 #define CORTINA_PHY_ADDR4 0x13
509 #define AQ_PHY_ADDR1 0x00
510 #define AQ_PHY_ADDR2 0x01
511 #define AQ_PHY_ADDR3 0x02
512 #define AQ_PHY_ADDR4 0x03
513 #define AQR405_IRQ_MASK 0x36
514 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
516 #include <asm/fsl_secure_boot.h>
518 #endif /* __LS2_RDB_H */