include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #endif
  17
  18 #define I2C_MUX_CH_VOL_MONITOR          0xa
  19 #define I2C_VOL_MONITOR_ADDR            0x38
  20
  21 /* step the IR regulator in 5mV increments */
  22 #define IR_VDD_STEP_DOWN                5
  23 #define IR_VDD_STEP_UP                  5
  24 /* The lowest and highest voltage allowed for LS2080ARDB */
  25 #define VDD_MV_MIN                      819
  26 #define VDD_MV_MAX                      1212
  27
  28 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  29
  30 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  31 #define SPD_EEPROM_ADDRESS1     0x51
  32 #define SPD_EEPROM_ADDRESS2     0x52
  33 #define SPD_EEPROM_ADDRESS3     0x53
  34 #define SPD_EEPROM_ADDRESS4     0x54
  35 #define SPD_EEPROM_ADDRESS5     0x55
  36 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  37 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  38 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  39 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  40 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  41 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  42 #endif
  43
  44 /* SATA */
  45
  46 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  47 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  48
  49 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  50
  51 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  53 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  54
  55 #define CONFIG_SYS_NOR0_CSPR                                    \
  56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  57         CSPR_PORT_SIZE_16                                       | \
  58         CSPR_MSEL_NOR                                           | \
  59         CSPR_V)
  60 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  61         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  62         CSPR_PORT_SIZE_16                                       | \
  63         CSPR_MSEL_NOR                                           | \
  64         CSPR_V)
  65 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  66 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  67                                 FTIM0_NOR_TEADC(0x5) | \
  68                                 FTIM0_NOR_TEAHC(0x5))
  69 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  70                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  71                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  72 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  73                                 FTIM2_NOR_TCH(0x4) | \
  74                                 FTIM2_NOR_TWPH(0x0E) | \
  75                                 FTIM2_NOR_TWP(0x1c))
  76 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  77 #define CONFIG_SYS_IFC_CCR      0x01000000
  78
  79 #ifdef CONFIG_MTD_NOR_FLASH
  80 #define CONFIG_SYS_FLASH_QUIET_TEST
  81 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  82
  83 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  84 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  85 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  86
  87 #define CONFIG_SYS_FLASH_EMPTY_INFO
  88 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  89                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  90 #endif
  91
  92 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  93 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  94
  95 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  96 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  97                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  98                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  99                                 | CSPR_V)
 100 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 101
 102 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 103                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 104                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 105                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 106                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 107                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 108                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 109
 110 /* ONFI NAND Flash mode0 Timing Params */
 111 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 112                                         FTIM0_NAND_TWP(0x30)   | \
 113                                         FTIM0_NAND_TWCHT(0x0e) | \
 114                                         FTIM0_NAND_TWH(0x14))
 115 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 116                                         FTIM1_NAND_TWBE(0xab)  | \
 117                                         FTIM1_NAND_TRR(0x1c)   | \
 118                                         FTIM1_NAND_TRP(0x30))
 119 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 120                                         FTIM2_NAND_TREH(0x14) | \
 121                                         FTIM2_NAND_TWHRE(0x3c))
 122 #define CONFIG_SYS_NAND_FTIM3           0x0
 123
 124 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 125 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 126 #define CONFIG_MTD_NAND_VERIFY_WRITE
 127
 128 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 129 #define QIXIS_LBMAP_SWITCH              0x06
 130 #define QIXIS_LBMAP_MASK                0x0f
 131 #define QIXIS_LBMAP_SHIFT               0
 132 #define QIXIS_LBMAP_DFLTBANK            0x00
 133 #define QIXIS_LBMAP_ALTBANK             0x04
 134 #define QIXIS_LBMAP_NAND                0x09
 135 #define QIXIS_RST_CTL_RESET             0x31
 136 #define QIXIS_RST_CTL_RESET_EN          0x30
 137 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 138 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 139 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 140 #define QIXIS_RCW_SRC_NAND              0x119
 141 #define QIXIS_RST_FORCE_MEM             0x01
 142
 143 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 144 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 145                                 | CSPR_PORT_SIZE_8 \
 146                                 | CSPR_MSEL_GPCM \
 147                                 | CSPR_V)
 148 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 149                                 | CSPR_PORT_SIZE_8 \
 150                                 | CSPR_MSEL_GPCM \
 151                                 | CSPR_V)
 152
 153 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 154 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 155 /* QIXIS Timing parameters for IFC CS3 */
 156 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 157                                         FTIM0_GPCM_TEADC(0x0e) | \
 158                                         FTIM0_GPCM_TEAHC(0x0e))
 159 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 160                                         FTIM1_GPCM_TRAD(0x3f))
 161 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 162                                         FTIM2_GPCM_TCH(0xf) | \
 163                                         FTIM2_GPCM_TWP(0x3E))
 164 #define CONFIG_SYS_CS3_FTIM3            0x0
 165
 166 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 167 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 168 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 169 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 170 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 171 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 172 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 173 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 174 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 175 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 176 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 177 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 178 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 179 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 180 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 181 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 182 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 183 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 184
 185 #define CONFIG_SPL_PAD_TO               0x80000
 186 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 187 #else
 188 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 189 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 190 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 191 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 192 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 193 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 194 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 195 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 196 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 197 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 198 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 199 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 200 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 201 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 202 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 203 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 204 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 205 #endif
 206
 207 /* Debug Server firmware */
 208 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 209 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 210 #endif
 211 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 212
 213 #ifdef CONFIG_TARGET_LS2081ARDB
 214 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 215 #define QIXIS_QMAP_MASK                 0x07
 216 #define QIXIS_QMAP_SHIFT                5
 217 #define QIXIS_LBMAP_DFLTBANK            0x00
 218 #define QIXIS_LBMAP_QSPI                0x00
 219 #define QIXIS_RCW_SRC_QSPI              0x62
 220 #define QIXIS_LBMAP_ALTBANK             0x20
 221 #define QIXIS_RST_CTL_RESET             0x31
 222 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 223 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 224 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 225 #define QIXIS_LBMAP_MASK                0x0f
 226 #define QIXIS_RST_CTL_RESET_EN          0x30
 227 #endif
 228
 229 /*
 230  * I2C
 231  */
 232 #ifdef CONFIG_TARGET_LS2081ARDB
 233 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 234 #endif
 235 #define I2C_MUX_PCA_ADDR                0x75
 236 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 237
 238 /* I2C bus multiplexer */
 239 #define I2C_MUX_CH_DEFAULT      0x8
 240
 241 /* SPI */
 242
 243 /*
 244  * RTC configuration
 245  */
 246 #define RTC
 247 #ifdef CONFIG_TARGET_LS2081ARDB
 248 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 249 #else
 250 #define CONFIG_RTC_DS3231               1
 251 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 252 #endif
 253
 254 /* EEPROM */
 255 #define CONFIG_SYS_I2C_EEPROM_NXID
 256 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 257
 258 #define CONFIG_FSL_MEMAC
 259
 260 #ifdef CONFIG_PCI
 261 #define CONFIG_PCI_SCAN_SHOW
 262 #endif
 263
 264 #define BOOT_TARGET_DEVICES(func) \
 265         func(USB, usb, 0) \
 266         func(MMC, mmc, 0) \
 267         func(SCSI, scsi, 0) \
 268         func(DHCP, dhcp, na)
 269 #include <config_distro_bootcmd.h>
 270
 271 #ifdef CONFIG_TFABOOT
 272 #define QSPI_MC_INIT_CMD                                \
 273         "sf probe 0:0; "                                \
 274         "sf read 0x80640000 0x640000 0x80000; "         \
 275         "env exists secureboot && "                     \
 276         "esbc_validate 0x80640000 && "                  \
 277         "esbc_validate 0x80680000; "                    \
 278         "sf read 0x80a00000 0xa00000 0x200000; "        \
 279         "sf read 0x80e00000 0xe00000 0x100000; "        \
 280         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 281 #define SD_MC_INIT_CMD                          \
 282         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 283         "mmc read 0x80e00000 0x7000 0x800;"     \
 284         "env exists secureboot && "             \
 285         "mmc read 0x80640000 0x3200 0x20 && "   \
 286         "mmc read 0x80680000 0x3400 0x20 && "   \
 287         "esbc_validate 0x80640000 && "          \
 288         "esbc_validate 0x80680000 ;"            \
 289         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 290 #define IFC_MC_INIT_CMD                         \
 291         "env exists secureboot && "     \
 292         "esbc_validate 0x580640000 && "         \
 293         "esbc_validate 0x580680000; "           \
 294         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 295 #else
 296 #ifdef CONFIG_QSPI_BOOT
 297 #define MC_INIT_CMD                                     \
 298         "mcinitcmd=sf probe 0:0; "                      \
 299         "sf read 0x80640000 0x640000 0x80000; "         \
 300         "env exists secureboot && "                     \
 301         "esbc_validate 0x80640000 && "                  \
 302         "esbc_validate 0x80680000; "                    \
 303         "sf read 0x80a00000 0xa00000 0x200000; "        \
 304         "sf read 0x80e00000 0xe00000 0x100000; "        \
 305         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 306 #elif defined(CONFIG_SD_BOOT)
 307 #define MC_INIT_CMD                             \
 308         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 309         "mmc read 0x80e00000 0x7000 0x800;"     \
 310         "env exists secureboot && "             \
 311         "mmc read 0x80640000 0x3200 0x20 && "   \
 312         "mmc read 0x80680000 0x3400 0x20 && "   \
 313         "esbc_validate 0x80640000 && "          \
 314         "esbc_validate 0x80680000 ;"            \
 315         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 316         "mcmemsize=0x70000000\0"
 317 #else
 318 #define MC_INIT_CMD                             \
 319         "mcinitcmd=env exists secureboot && "   \
 320         "esbc_validate 0x580640000 && "         \
 321         "esbc_validate 0x580680000; "           \
 322         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 323 #endif
 324 #endif
 325
 326 /* Initial environment variables */
 327 #undef CONFIG_EXTRA_ENV_SETTINGS
 328 #ifdef CONFIG_TFABOOT
 329 #define CONFIG_EXTRA_ENV_SETTINGS               \
 330         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 331         "ramdisk_addr=0x800000\0"               \
 332         "ramdisk_size=0x2000000\0"              \
 333         "fdt_high=0xa0000000\0"                 \
 334         "initrd_high=0xffffffffffffffff\0"      \
 335         "fdt_addr=0x64f00000\0"                 \
 336         "kernel_addr=0x581000000\0"             \
 337         "kernel_start=0x1000000\0"              \
 338         "kernelheader_start=0x800000\0"         \
 339         "scriptaddr=0x80000000\0"               \
 340         "scripthdraddr=0x80080000\0"            \
 341         "fdtheader_addr_r=0x80100000\0"         \
 342         "kernelheader_addr_r=0x80200000\0"      \
 343         "kernelheader_addr=0x580600000\0"       \
 344         "kernel_addr_r=0x81000000\0"            \
 345         "kernelheader_size=0x40000\0"           \
 346         "fdt_addr_r=0x90000000\0"               \
 347         "load_addr=0xa0000000\0"                \
 348         "kernel_size=0x2800000\0"               \
 349         "kernel_addr_sd=0x8000\0"               \
 350         "kernel_size_sd=0x14000\0"              \
 351         "console=ttyAMA0,38400n8\0"             \
 352         "mcmemsize=0x70000000\0"                \
 353         "sd_bootcmd=echo Trying load from SD ..;" \
 354         "mmcinfo; mmc read $load_addr "         \
 355         "$kernel_addr_sd $kernel_size_sd && "   \
 356         "bootm $load_addr#$board\0"             \
 357         QSPI_MC_INIT_CMD                                \
 358         BOOTENV                                 \
 359         "boot_scripts=ls2088ardb_boot.scr\0"    \
 360         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 361         "scan_dev_for_boot_part="               \
 362                 "part list ${devtype} ${devnum} devplist; "     \
 363                 "env exists devplist || setenv devplist 1; "    \
 364                 "for distro_bootpart in ${devplist}; do "       \
 365                         "if fstype ${devtype} "                 \
 366                                 "${devnum}:${distro_bootpart} " \
 367                                 "bootfstype; then "             \
 368                                 "run scan_dev_for_boot; "       \
 369                         "fi; "                                  \
 370                 "done\0"                                        \
 371         "boot_a_script="                                        \
 372                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 373                         "${scriptaddr} ${prefix}${script}; "    \
 374                 "env exists secureboot && load ${devtype} "     \
 375                         "${devnum}:${distro_bootpart} "         \
 376                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 377                         "&& esbc_validate ${scripthdraddr};"    \
 378                 "source ${scriptaddr}\0"                        \
 379         "qspi_bootcmd=echo Trying load from qspi..;"            \
 380                 "sf probe && sf read $load_addr "               \
 381                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 382                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 383                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 384                 " bootm $load_addr#$board\0"                    \
 385         "nor_bootcmd=echo Trying load from nor..;"              \
 386                 "cp.b $kernel_addr $load_addr "                 \
 387                 "$kernel_size ; env exists secureboot && "      \
 388                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 389                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 390                 "bootm $load_addr#$board\0"
 391 #else
 392 #define CONFIG_EXTRA_ENV_SETTINGS               \
 393         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 394         "ramdisk_addr=0x800000\0"               \
 395         "ramdisk_size=0x2000000\0"              \
 396         "fdt_high=0xa0000000\0"                 \
 397         "initrd_high=0xffffffffffffffff\0"      \
 398         "fdt_addr=0x64f00000\0"                 \
 399         "kernel_addr=0x581000000\0"             \
 400         "kernel_start=0x1000000\0"              \
 401         "kernelheader_start=0x600000\0"         \
 402         "scriptaddr=0x80000000\0"               \
 403         "scripthdraddr=0x80080000\0"            \
 404         "fdtheader_addr_r=0x80100000\0"         \
 405         "kernelheader_addr_r=0x80200000\0"      \
 406         "kernelheader_addr=0x580600000\0"       \
 407         "kernel_addr_r=0x81000000\0"            \
 408         "kernelheader_size=0x40000\0"           \
 409         "fdt_addr_r=0x90000000\0"               \
 410         "load_addr=0xa0000000\0"                \
 411         "kernel_size=0x2800000\0"               \
 412         "kernel_addr_sd=0x8000\0"               \
 413         "kernel_size_sd=0x14000\0"              \
 414         "console=ttyAMA0,38400n8\0"             \
 415         "mcmemsize=0x70000000\0"                \
 416         "sd_bootcmd=echo Trying load from SD ..;" \
 417         "mmcinfo; mmc read $load_addr "         \
 418         "$kernel_addr_sd $kernel_size_sd && "   \
 419         "bootm $load_addr#$board\0"             \
 420         MC_INIT_CMD                             \
 421         BOOTENV                                 \
 422         "boot_scripts=ls2088ardb_boot.scr\0"    \
 423         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 424         "scan_dev_for_boot_part="               \
 425                 "part list ${devtype} ${devnum} devplist; "     \
 426                 "env exists devplist || setenv devplist 1; "    \
 427                 "for distro_bootpart in ${devplist}; do "       \
 428                         "if fstype ${devtype} "                 \
 429                                 "${devnum}:${distro_bootpart} " \
 430                                 "bootfstype; then "             \
 431                                 "run scan_dev_for_boot; "       \
 432                         "fi; "                                  \
 433                 "done\0"                                        \
 434         "boot_a_script="                                        \
 435                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 436                         "${scriptaddr} ${prefix}${script}; "    \
 437                 "env exists secureboot && load ${devtype} "     \
 438                         "${devnum}:${distro_bootpart} "         \
 439                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 440                         "env exists secureboot "        \
 441                         "&& esbc_validate ${scripthdraddr};"    \
 442                 "source ${scriptaddr}\0"                        \
 443         "qspi_bootcmd=echo Trying load from qspi..;"            \
 444                 "sf probe && sf read $load_addr "               \
 445                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 446                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 447                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 448                 " bootm $load_addr#$board\0"                    \
 449         "nor_bootcmd=echo Trying load from nor..;"              \
 450                 "cp.b $kernel_addr $load_addr "                 \
 451                 "$kernel_size ; env exists secureboot && "      \
 452                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 453                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 454                 "bootm $load_addr#$board\0"
 455 #endif
 456
 457 #ifdef CONFIG_TFABOOT
 458 #define QSPI_NOR_BOOTCOMMAND                                            \
 459                         "sf probe 0:0; "                                \
 460                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 461                         "env exists mcinitcmd && env exists secureboot "\
 462                         "&& esbc_validate 0x806c0000; "                 \
 463                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 464                         "env exists mcinitcmd && "                      \
 465                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 466                         "run distro_bootcmd;run qspi_bootcmd; "         \
 467                         "env exists secureboot && esbc_halt;"
 468
 469 /* Try to boot an on-SD kernel first, then do normal distro boot */
 470 #define SD_BOOTCOMMAND                                          \
 471                         "env exists mcinitcmd && env exists secureboot "\
 472                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 473                         "&& esbc_validate $load_addr; "                 \
 474                         "env exists mcinitcmd && run mcinitcmd "        \
 475                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 476                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 477                         "run distro_bootcmd;run sd_bootcmd; "           \
 478                         "env exists secureboot && esbc_halt;"
 479
 480 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 481 #define IFC_NOR_BOOTCOMMAND                                             \
 482                         "env exists mcinitcmd && env exists secureboot "\
 483                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 484                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 485                         "run distro_bootcmd;run nor_bootcmd; "          \
 486                         "env exists secureboot && esbc_halt;"
 487 #else
 488 #ifdef CONFIG_QSPI_BOOT
 489 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 490 #elif defined(CONFIG_SD_BOOT)
 491 /* Try to boot an on-SD kernel first, then do normal distro boot */
 492 #else
 493 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 494 #endif
 495 #endif
 496
 497 /* MAC/PHY configuration */
 498 #define CORTINA_PHY_ADDR1       0x10
 499 #define CORTINA_PHY_ADDR2       0x11
 500 #define CORTINA_PHY_ADDR3       0x12
 501 #define CORTINA_PHY_ADDR4       0x13
 502 #define AQ_PHY_ADDR1            0x00
 503 #define AQ_PHY_ADDR2            0x01
 504 #define AQ_PHY_ADDR3            0x02
 505 #define AQ_PHY_ADDR4            0x03
 506 #define AQR405_IRQ_MASK         0x36
 507
 508 #include <asm/fsl_secure_boot.h>
 509
 510 #endif /* __LS2_RDB_H */