include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #define I2C_MUX_CH_VOL_MONITOR          0xa
  13 #define I2C_VOL_MONITOR_ADDR            0x38
  14
  15 /* step the IR regulator in 5mV increments */
  16 #define IR_VDD_STEP_DOWN                5
  17 #define IR_VDD_STEP_UP                  5
  18 /* The lowest and highest voltage allowed for LS2080ARDB */
  19 #define VDD_MV_MIN                      819
  20 #define VDD_MV_MAX                      1212
  21
  22 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  23
  24 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  25 #define SPD_EEPROM_ADDRESS1     0x51
  26 #define SPD_EEPROM_ADDRESS2     0x52
  27 #define SPD_EEPROM_ADDRESS3     0x53
  28 #define SPD_EEPROM_ADDRESS4     0x54
  29 #define SPD_EEPROM_ADDRESS5     0x55
  30 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  31 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  32
  33 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  34
  35 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  36 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  37 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  38
  39 #define CONFIG_SYS_NOR0_CSPR                                    \
  40         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  41         CSPR_PORT_SIZE_16                                       | \
  42         CSPR_MSEL_NOR                                           | \
  43         CSPR_V)
  44 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  45         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  46         CSPR_PORT_SIZE_16                                       | \
  47         CSPR_MSEL_NOR                                           | \
  48         CSPR_V)
  49 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  50 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  51                                 FTIM0_NOR_TEADC(0x5) | \
  52                                 FTIM0_NOR_TEAHC(0x5))
  53 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  54                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  55                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  56 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  57                                 FTIM2_NOR_TCH(0x4) | \
  58                                 FTIM2_NOR_TWPH(0x0E) | \
  59                                 FTIM2_NOR_TWP(0x1c))
  60 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  61 #define CONFIG_SYS_IFC_CCR      0x01000000
  62
  63 #ifdef CONFIG_MTD_NOR_FLASH
  64 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  65
  66 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  67                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  68 #endif
  69
  70 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  71 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  72
  73 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  74 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  75                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  76                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  77                                 | CSPR_V)
  78 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  79
  80 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  81                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  82                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  83                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  84                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
  85                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
  86                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
  87
  88 /* ONFI NAND Flash mode0 Timing Params */
  89 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
  90                                         FTIM0_NAND_TWP(0x30)   | \
  91                                         FTIM0_NAND_TWCHT(0x0e) | \
  92                                         FTIM0_NAND_TWH(0x14))
  93 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
  94                                         FTIM1_NAND_TWBE(0xab)  | \
  95                                         FTIM1_NAND_TRR(0x1c)   | \
  96                                         FTIM1_NAND_TRP(0x30))
  97 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
  98                                         FTIM2_NAND_TREH(0x14) | \
  99                                         FTIM2_NAND_TWHRE(0x3c))
 100 #define CONFIG_SYS_NAND_FTIM3           0x0
 101
 102 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 103 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 104 #define CONFIG_MTD_NAND_VERIFY_WRITE
 105
 106 #define QIXIS_LBMAP_SWITCH              0x06
 107 #define QIXIS_LBMAP_MASK                0x0f
 108 #define QIXIS_LBMAP_SHIFT               0
 109 #define QIXIS_LBMAP_DFLTBANK            0x00
 110 #define QIXIS_LBMAP_ALTBANK             0x04
 111 #define QIXIS_LBMAP_NAND                0x09
 112 #define QIXIS_RST_CTL_RESET             0x31
 113 #define QIXIS_RST_CTL_RESET_EN          0x30
 114 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 115 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 116 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 117 #define QIXIS_RCW_SRC_NAND              0x119
 118 #define QIXIS_RST_FORCE_MEM             0x01
 119
 120 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 121 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 122                                 | CSPR_PORT_SIZE_8 \
 123                                 | CSPR_MSEL_GPCM \
 124                                 | CSPR_V)
 125 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 126                                 | CSPR_PORT_SIZE_8 \
 127                                 | CSPR_MSEL_GPCM \
 128                                 | CSPR_V)
 129
 130 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 131 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 132 /* QIXIS Timing parameters for IFC CS3 */
 133 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 134                                         FTIM0_GPCM_TEADC(0x0e) | \
 135                                         FTIM0_GPCM_TEAHC(0x0e))
 136 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 137                                         FTIM1_GPCM_TRAD(0x3f))
 138 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 139                                         FTIM2_GPCM_TCH(0xf) | \
 140                                         FTIM2_GPCM_TWP(0x3E))
 141 #define CONFIG_SYS_CS3_FTIM3            0x0
 142
 143 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 144 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 145 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 146 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 147 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 148 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 149 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 150 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 151 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 152 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 153 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 154 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 155 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 156 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 157 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 158 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 159 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 160 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 161
 162 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 163 #else
 164 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 165 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 166 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 167 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 168 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 169 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 170 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 171 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 172 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 173 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 174 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 175 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 176 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 177 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 178 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 179 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 180 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 181 #endif
 182 #endif
 183 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 184
 185 #ifdef CONFIG_TARGET_LS2081ARDB
 186 #define QIXIS_QMAP_MASK                 0x07
 187 #define QIXIS_QMAP_SHIFT                5
 188 #define QIXIS_LBMAP_DFLTBANK            0x00
 189 #define QIXIS_LBMAP_QSPI                0x00
 190 #define QIXIS_RCW_SRC_QSPI              0x62
 191 #define QIXIS_LBMAP_ALTBANK             0x20
 192 #define QIXIS_RST_CTL_RESET             0x31
 193 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 194 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 195 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 196 #define QIXIS_LBMAP_MASK                0x0f
 197 #define QIXIS_RST_CTL_RESET_EN          0x30
 198 #endif
 199
 200 /*
 201  * I2C
 202  */
 203 #ifdef CONFIG_TARGET_LS2081ARDB
 204 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 205 #endif
 206 #define I2C_MUX_PCA_ADDR                0x75
 207 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 208
 209 /* I2C bus multiplexer */
 210 #define I2C_MUX_CH_DEFAULT      0x8
 211
 212 /* SPI */
 213
 214 /*
 215  * RTC configuration
 216  */
 217 #define RTC
 218 #ifdef CONFIG_TARGET_LS2081ARDB
 219 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 220 #else
 221 #define CONFIG_RTC_DS3231               1
 222 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 223 #endif
 224
 225 #define BOOT_TARGET_DEVICES(func) \
 226         func(USB, usb, 0) \
 227         func(MMC, mmc, 0) \
 228         func(SCSI, scsi, 0) \
 229         func(DHCP, dhcp, na)
 230 #include <config_distro_bootcmd.h>
 231
 232 #ifdef CONFIG_TFABOOT
 233 #define QSPI_MC_INIT_CMD                                \
 234         "sf probe 0:0; "                                \
 235         "sf read 0x80640000 0x640000 0x80000; "         \
 236         "env exists secureboot && "                     \
 237         "esbc_validate 0x80640000 && "                  \
 238         "esbc_validate 0x80680000; "                    \
 239         "sf read 0x80a00000 0xa00000 0x200000; "        \
 240         "sf read 0x80e00000 0xe00000 0x100000; "        \
 241         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 242 #define SD_MC_INIT_CMD                          \
 243         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 244         "mmc read 0x80e00000 0x7000 0x800;"     \
 245         "env exists secureboot && "             \
 246         "mmc read 0x80640000 0x3200 0x20 && "   \
 247         "mmc read 0x80680000 0x3400 0x20 && "   \
 248         "esbc_validate 0x80640000 && "          \
 249         "esbc_validate 0x80680000 ;"            \
 250         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 251 #define IFC_MC_INIT_CMD                         \
 252         "env exists secureboot && "     \
 253         "esbc_validate 0x580640000 && "         \
 254         "esbc_validate 0x580680000; "           \
 255         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 256 #else
 257 #ifdef CONFIG_QSPI_BOOT
 258 #define MC_INIT_CMD                                     \
 259         "mcinitcmd=sf probe 0:0; "                      \
 260         "sf read 0x80640000 0x640000 0x80000; "         \
 261         "env exists secureboot && "                     \
 262         "esbc_validate 0x80640000 && "                  \
 263         "esbc_validate 0x80680000; "                    \
 264         "sf read 0x80a00000 0xa00000 0x200000; "        \
 265         "sf read 0x80e00000 0xe00000 0x100000; "        \
 266         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 267 #elif defined(CONFIG_SD_BOOT)
 268 #define MC_INIT_CMD                             \
 269         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 270         "mmc read 0x80e00000 0x7000 0x800;"     \
 271         "env exists secureboot && "             \
 272         "mmc read 0x80640000 0x3200 0x20 && "   \
 273         "mmc read 0x80680000 0x3400 0x20 && "   \
 274         "esbc_validate 0x80640000 && "          \
 275         "esbc_validate 0x80680000 ;"            \
 276         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 277         "mcmemsize=0x70000000\0"
 278 #else
 279 #define MC_INIT_CMD                             \
 280         "mcinitcmd=env exists secureboot && "   \
 281         "esbc_validate 0x580640000 && "         \
 282         "esbc_validate 0x580680000; "           \
 283         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 284 #endif
 285 #endif
 286
 287 /* Initial environment variables */
 288 #undef CONFIG_EXTRA_ENV_SETTINGS
 289 #ifdef CONFIG_TFABOOT
 290 #define CONFIG_EXTRA_ENV_SETTINGS               \
 291         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 292         "ramdisk_addr=0x800000\0"               \
 293         "ramdisk_size=0x2000000\0"              \
 294         "fdt_high=0xa0000000\0"                 \
 295         "initrd_high=0xffffffffffffffff\0"      \
 296         "kernel_addr=0x581000000\0"             \
 297         "kernel_start=0x1000000\0"              \
 298         "kernelheader_start=0x800000\0"         \
 299         "scriptaddr=0x80000000\0"               \
 300         "scripthdraddr=0x80080000\0"            \
 301         "fdtheader_addr_r=0x80100000\0"         \
 302         "kernelheader_addr_r=0x80200000\0"      \
 303         "kernelheader_addr=0x580600000\0"       \
 304         "kernel_addr_r=0x81000000\0"            \
 305         "kernelheader_size=0x40000\0"           \
 306         "fdt_addr_r=0x90000000\0"               \
 307         "load_addr=0xa0000000\0"                \
 308         "kernel_size=0x2800000\0"               \
 309         "kernel_addr_sd=0x8000\0"               \
 310         "kernel_size_sd=0x14000\0"              \
 311         "console=ttyAMA0,38400n8\0"             \
 312         "mcmemsize=0x70000000\0"                \
 313         "sd_bootcmd=echo Trying load from SD ..;" \
 314         "mmcinfo; mmc read $load_addr "         \
 315         "$kernel_addr_sd $kernel_size_sd && "   \
 316         "bootm $load_addr#$board\0"             \
 317         QSPI_MC_INIT_CMD                                \
 318         BOOTENV                                 \
 319         "boot_scripts=ls2088ardb_boot.scr\0"    \
 320         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 321         "scan_dev_for_boot_part="               \
 322                 "part list ${devtype} ${devnum} devplist; "     \
 323                 "env exists devplist || setenv devplist 1; "    \
 324                 "for distro_bootpart in ${devplist}; do "       \
 325                         "if fstype ${devtype} "                 \
 326                                 "${devnum}:${distro_bootpart} " \
 327                                 "bootfstype; then "             \
 328                                 "run scan_dev_for_boot; "       \
 329                         "fi; "                                  \
 330                 "done\0"                                        \
 331         "boot_a_script="                                        \
 332                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 333                         "${scriptaddr} ${prefix}${script}; "    \
 334                 "env exists secureboot && load ${devtype} "     \
 335                         "${devnum}:${distro_bootpart} "         \
 336                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 337                         "&& esbc_validate ${scripthdraddr};"    \
 338                 "source ${scriptaddr}\0"                        \
 339         "qspi_bootcmd=echo Trying load from qspi..;"            \
 340                 "sf probe && sf read $load_addr "               \
 341                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 342                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 343                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 344                 " bootm $load_addr#$board\0"                    \
 345         "nor_bootcmd=echo Trying load from nor..;"              \
 346                 "cp.b $kernel_addr $load_addr "                 \
 347                 "$kernel_size ; env exists secureboot && "      \
 348                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 349                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 350                 "bootm $load_addr#$board\0"
 351 #else
 352 #define CONFIG_EXTRA_ENV_SETTINGS               \
 353         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 354         "ramdisk_addr=0x800000\0"               \
 355         "ramdisk_size=0x2000000\0"              \
 356         "fdt_high=0xa0000000\0"                 \
 357         "initrd_high=0xffffffffffffffff\0"      \
 358         "kernel_addr=0x581000000\0"             \
 359         "kernel_start=0x1000000\0"              \
 360         "kernelheader_start=0x600000\0"         \
 361         "scriptaddr=0x80000000\0"               \
 362         "scripthdraddr=0x80080000\0"            \
 363         "fdtheader_addr_r=0x80100000\0"         \
 364         "kernelheader_addr_r=0x80200000\0"      \
 365         "kernelheader_addr=0x580600000\0"       \
 366         "kernel_addr_r=0x81000000\0"            \
 367         "kernelheader_size=0x40000\0"           \
 368         "fdt_addr_r=0x90000000\0"               \
 369         "load_addr=0xa0000000\0"                \
 370         "kernel_size=0x2800000\0"               \
 371         "kernel_addr_sd=0x8000\0"               \
 372         "kernel_size_sd=0x14000\0"              \
 373         "console=ttyAMA0,38400n8\0"             \
 374         "mcmemsize=0x70000000\0"                \
 375         "sd_bootcmd=echo Trying load from SD ..;" \
 376         "mmcinfo; mmc read $load_addr "         \
 377         "$kernel_addr_sd $kernel_size_sd && "   \
 378         "bootm $load_addr#$board\0"             \
 379         MC_INIT_CMD                             \
 380         BOOTENV                                 \
 381         "boot_scripts=ls2088ardb_boot.scr\0"    \
 382         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 383         "scan_dev_for_boot_part="               \
 384                 "part list ${devtype} ${devnum} devplist; "     \
 385                 "env exists devplist || setenv devplist 1; "    \
 386                 "for distro_bootpart in ${devplist}; do "       \
 387                         "if fstype ${devtype} "                 \
 388                                 "${devnum}:${distro_bootpart} " \
 389                                 "bootfstype; then "             \
 390                                 "run scan_dev_for_boot; "       \
 391                         "fi; "                                  \
 392                 "done\0"                                        \
 393         "boot_a_script="                                        \
 394                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 395                         "${scriptaddr} ${prefix}${script}; "    \
 396                 "env exists secureboot && load ${devtype} "     \
 397                         "${devnum}:${distro_bootpart} "         \
 398                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 399                         "env exists secureboot "        \
 400                         "&& esbc_validate ${scripthdraddr};"    \
 401                 "source ${scriptaddr}\0"                        \
 402         "qspi_bootcmd=echo Trying load from qspi..;"            \
 403                 "sf probe && sf read $load_addr "               \
 404                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 405                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 406                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 407                 " bootm $load_addr#$board\0"                    \
 408         "nor_bootcmd=echo Trying load from nor..;"              \
 409                 "cp.b $kernel_addr $load_addr "                 \
 410                 "$kernel_size ; env exists secureboot && "      \
 411                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 412                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 413                 "bootm $load_addr#$board\0"
 414 #endif
 415
 416 #ifdef CONFIG_TFABOOT
 417 #define QSPI_NOR_BOOTCOMMAND                                            \
 418                         "sf probe 0:0; "                                \
 419                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 420                         "env exists mcinitcmd && env exists secureboot "\
 421                         "&& esbc_validate 0x806c0000; "                 \
 422                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 423                         "env exists mcinitcmd && "                      \
 424                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 425                         "run distro_bootcmd;run qspi_bootcmd; "         \
 426                         "env exists secureboot && esbc_halt;"
 427
 428 /* Try to boot an on-SD kernel first, then do normal distro boot */
 429 #define SD_BOOTCOMMAND                                          \
 430                         "env exists mcinitcmd && env exists secureboot "\
 431                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 432                         "&& esbc_validate $load_addr; "                 \
 433                         "env exists mcinitcmd && run mcinitcmd "        \
 434                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 435                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 436                         "run distro_bootcmd;run sd_bootcmd; "           \
 437                         "env exists secureboot && esbc_halt;"
 438
 439 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 440 #define IFC_NOR_BOOTCOMMAND                                             \
 441                         "env exists mcinitcmd && env exists secureboot "\
 442                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 443                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 444                         "run distro_bootcmd;run nor_bootcmd; "          \
 445                         "env exists secureboot && esbc_halt;"
 446 #else
 447 #ifdef CONFIG_QSPI_BOOT
 448 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 449 #elif defined(CONFIG_SD_BOOT)
 450 /* Try to boot an on-SD kernel first, then do normal distro boot */
 451 #else
 452 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 453 #endif
 454 #endif
 455
 456 /* MAC/PHY configuration */
 457 #define CORTINA_PHY_ADDR1       0x10
 458 #define CORTINA_PHY_ADDR2       0x11
 459 #define CORTINA_PHY_ADDR3       0x12
 460 #define CORTINA_PHY_ADDR4       0x13
 461 #define AQ_PHY_ADDR1            0x00
 462 #define AQ_PHY_ADDR2            0x01
 463 #define AQ_PHY_ADDR3            0x02
 464 #define AQ_PHY_ADDR4            0x03
 465 #define AQR405_IRQ_MASK         0x36
 466
 467 #include <asm/fsl_secure_boot.h>
 468
 469 #endif /* __LS2_RDB_H */