include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2020 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #ifndef CONFIG_DM_I2C
  17 #define CONFIG_SYS_I2C_EARLY_INIT
  18 #endif
  19 #endif
  20
  21 #define I2C_MUX_CH_VOL_MONITOR          0xa
  22 #define I2C_VOL_MONITOR_ADDR            0x38
  23 #define CONFIG_VOL_MONITOR_IR36021_READ
  24 #define CONFIG_VOL_MONITOR_IR36021_SET
  25
  26 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  27 #ifndef CONFIG_SPL_BUILD
  28 #define CONFIG_VID
  29 #endif
  30 /* step the IR regulator in 5mV increments */
  31 #define IR_VDD_STEP_DOWN                5
  32 #define IR_VDD_STEP_UP                  5
  33 /* The lowest and highest voltage allowed for LS2080ARDB */
  34 #define VDD_MV_MIN                      819
  35 #define VDD_MV_MAX                      1212
  36
  37 #ifndef __ASSEMBLY__
  38 unsigned long get_board_sys_clk(void);
  39 #endif
  40
  41 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  42 #define CONFIG_DDR_CLK_FREQ             133333333
  43 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  44
  45 #define CONFIG_DDR_SPD
  46 #define CONFIG_DDR_ECC
  47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #define SPD_EEPROM_ADDRESS1     0x51
  50 #define SPD_EEPROM_ADDRESS2     0x52
  51 #define SPD_EEPROM_ADDRESS3     0x53
  52 #define SPD_EEPROM_ADDRESS4     0x54
  53 #define SPD_EEPROM_ADDRESS5     0x55
  54 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  55 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  56 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  57 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  58 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  59 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  60 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  61 #endif
  62
  63 /* SATA */
  64 #define CONFIG_SCSI_AHCI_PLAT
  65
  66 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  67 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  68
  69 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  70 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  71 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  72                                                 CONFIG_SYS_SCSI_MAX_LUN)
  73 #ifdef CONFIG_TFABOOT
  74 #define CONFIG_SYS_MMC_ENV_DEV         0
  75 #endif
  76
  77 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  78
  79 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  80 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  81 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  82
  83 #define CONFIG_SYS_NOR0_CSPR                                    \
  84         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  85         CSPR_PORT_SIZE_16                                       | \
  86         CSPR_MSEL_NOR                                           | \
  87         CSPR_V)
  88 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  89         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  90         CSPR_PORT_SIZE_16                                       | \
  91         CSPR_MSEL_NOR                                           | \
  92         CSPR_V)
  93 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  94 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  95                                 FTIM0_NOR_TEADC(0x5) | \
  96                                 FTIM0_NOR_TEAHC(0x5))
  97 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  98                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  99                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 100 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 101                                 FTIM2_NOR_TCH(0x4) | \
 102                                 FTIM2_NOR_TWPH(0x0E) | \
 103                                 FTIM2_NOR_TWP(0x1c))
 104 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 105 #define CONFIG_SYS_IFC_CCR      0x01000000
 106
 107 #ifdef CONFIG_MTD_NOR_FLASH
 108 #define CONFIG_SYS_FLASH_QUIET_TEST
 109 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 110
 111 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 112 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 113 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 114 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 115
 116 #define CONFIG_SYS_FLASH_EMPTY_INFO
 117 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 118                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 119 #endif
 120
 121 #define CONFIG_NAND_FSL_IFC
 122 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 123 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 124
 125 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 126 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 127                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 128                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 129                                 | CSPR_V)
 130 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 131
 132 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 133                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 134                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 135                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 136                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 137                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 138                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 139
 140 #define CONFIG_SYS_NAND_ONFI_DETECTION
 141
 142 /* ONFI NAND Flash mode0 Timing Params */
 143 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 144                                         FTIM0_NAND_TWP(0x30)   | \
 145                                         FTIM0_NAND_TWCHT(0x0e) | \
 146                                         FTIM0_NAND_TWH(0x14))
 147 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 148                                         FTIM1_NAND_TWBE(0xab)  | \
 149                                         FTIM1_NAND_TRR(0x1c)   | \
 150                                         FTIM1_NAND_TRP(0x30))
 151 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 152                                         FTIM2_NAND_TREH(0x14) | \
 153                                         FTIM2_NAND_TWHRE(0x3c))
 154 #define CONFIG_SYS_NAND_FTIM3           0x0
 155
 156 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 157 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 158 #define CONFIG_MTD_NAND_VERIFY_WRITE
 159
 160 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 161 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 162 #define QIXIS_LBMAP_SWITCH              0x06
 163 #define QIXIS_LBMAP_MASK                0x0f
 164 #define QIXIS_LBMAP_SHIFT               0
 165 #define QIXIS_LBMAP_DFLTBANK            0x00
 166 #define QIXIS_LBMAP_ALTBANK             0x04
 167 #define QIXIS_LBMAP_NAND                0x09
 168 #define QIXIS_RST_CTL_RESET             0x31
 169 #define QIXIS_RST_CTL_RESET_EN          0x30
 170 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 171 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 172 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 173 #define QIXIS_RCW_SRC_NAND              0x119
 174 #define QIXIS_RST_FORCE_MEM             0x01
 175
 176 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 177 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 178                                 | CSPR_PORT_SIZE_8 \
 179                                 | CSPR_MSEL_GPCM \
 180                                 | CSPR_V)
 181 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 182                                 | CSPR_PORT_SIZE_8 \
 183                                 | CSPR_MSEL_GPCM \
 184                                 | CSPR_V)
 185
 186 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 187 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 188 /* QIXIS Timing parameters for IFC CS3 */
 189 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 190                                         FTIM0_GPCM_TEADC(0x0e) | \
 191                                         FTIM0_GPCM_TEAHC(0x0e))
 192 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 193                                         FTIM1_GPCM_TRAD(0x3f))
 194 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 195                                         FTIM2_GPCM_TCH(0xf) | \
 196                                         FTIM2_GPCM_TWP(0x3E))
 197 #define CONFIG_SYS_CS3_FTIM3            0x0
 198
 199 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 200 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 201 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 202 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 203 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 204 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 205 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 206 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 207 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 208 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 209 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 210 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 211 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 212 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 213 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 214 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 215 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 216 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 217
 218 #define CONFIG_SPL_PAD_TO               0x80000
 219 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 220 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 221 #else
 222 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 223 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 224 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 225 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 226 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 227 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 228 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 229 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 230 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 231 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 232 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 233 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 234 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 235 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 236 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 237 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 238 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 239 #endif
 240
 241 /* Debug Server firmware */
 242 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 243 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 244 #endif
 245 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 246
 247 #ifdef CONFIG_TARGET_LS2081ARDB
 248 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 249 #define QIXIS_QMAP_MASK                 0x07
 250 #define QIXIS_QMAP_SHIFT                5
 251 #define QIXIS_LBMAP_DFLTBANK            0x00
 252 #define QIXIS_LBMAP_QSPI                0x00
 253 #define QIXIS_RCW_SRC_QSPI              0x62
 254 #define QIXIS_LBMAP_ALTBANK             0x20
 255 #define QIXIS_RST_CTL_RESET             0x31
 256 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 257 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 258 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 259 #define QIXIS_LBMAP_MASK                0x0f
 260 #define QIXIS_RST_CTL_RESET_EN          0x30
 261 #endif
 262
 263 /*
 264  * I2C
 265  */
 266 #ifdef CONFIG_TARGET_LS2081ARDB
 267 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 268 #endif
 269 #define I2C_MUX_PCA_ADDR                0x75
 270 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 271
 272 /* I2C bus multiplexer */
 273 #define I2C_MUX_CH_DEFAULT      0x8
 274
 275 /* SPI */
 276 #if defined(CONFIG_FSL_DSPI)
 277 #define CONFIG_SPI_FLASH_STMICRO
 278 #endif
 279
 280 /*
 281  * RTC configuration
 282  */
 283 #define RTC
 284 #ifdef CONFIG_TARGET_LS2081ARDB
 285 #define CONFIG_RTC_PCF8563              1
 286 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 287 #else
 288 #define CONFIG_RTC_DS3231               1
 289 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 290 #endif
 291
 292 /* EEPROM */
 293 #define CONFIG_ID_EEPROM
 294 #define CONFIG_SYS_I2C_EEPROM_NXID
 295 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 296 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 297 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 298 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 300
 301 #define CONFIG_FSL_MEMAC
 302
 303 #ifdef CONFIG_PCI
 304 #define CONFIG_PCI_SCAN_SHOW
 305 #endif
 306
 307 /*  MMC  */
 308 #ifdef CONFIG_MMC
 309 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 310 #endif
 311
 312 #define BOOT_TARGET_DEVICES(func) \
 313         func(USB, usb, 0) \
 314         func(MMC, mmc, 0) \
 315         func(SCSI, scsi, 0) \
 316         func(DHCP, dhcp, na)
 317 #include <config_distro_bootcmd.h>
 318
 319 #ifdef CONFIG_TFABOOT
 320 #define QSPI_MC_INIT_CMD                                \
 321         "sf probe 0:0; "                                \
 322         "sf read 0x80640000 0x640000 0x80000; "         \
 323         "env exists secureboot && "                     \
 324         "esbc_validate 0x80640000 && "                  \
 325         "esbc_validate 0x80680000; "                    \
 326         "sf read 0x80a00000 0xa00000 0x300000; "        \
 327         "sf read 0x80e00000 0xe00000 0x100000; "        \
 328         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 329 #define SD_MC_INIT_CMD                          \
 330         "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \
 331         "mmc read 0x80e00000 0x7000 0x800;"     \
 332         "env exists secureboot && "             \
 333         "mmc read 0x80640000 0x3200 0x20 && "   \
 334         "mmc read 0x80680000 0x3400 0x20 && "   \
 335         "esbc_validate 0x80640000 && "          \
 336         "esbc_validate 0x80680000 ;"            \
 337         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 338 #define IFC_MC_INIT_CMD                         \
 339         "env exists secureboot && "     \
 340         "esbc_validate 0x580640000 && "         \
 341         "esbc_validate 0x580680000; "           \
 342         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 343 #else
 344 #ifdef CONFIG_QSPI_BOOT
 345 #define MC_INIT_CMD                                     \
 346         "mcinitcmd=sf probe 0:0; "                      \
 347         "sf read 0x80640000 0x640000 0x80000; "         \
 348         "env exists secureboot && "                     \
 349         "esbc_validate 0x80640000 && "                  \
 350         "esbc_validate 0x80680000; "                    \
 351         "sf read 0x80a00000 0xa00000 0x300000; "        \
 352         "sf read 0x80e00000 0xe00000 0x100000; "        \
 353         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 354 #elif defined(CONFIG_SD_BOOT)
 355 #define MC_INIT_CMD                             \
 356         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
 357         "mmc read 0x80100000 0x7000 0x800;"     \
 358         "env exists secureboot && "             \
 359         "mmc read 0x80640000 0x3200 0x20 && "   \
 360         "mmc read 0x80680000 0x3400 0x20 && "   \
 361         "esbc_validate 0x80640000 && "          \
 362         "esbc_validate 0x80680000 ;"            \
 363         "fsl_mc start mc 0x80000000 0x80100000\0" \
 364         "mcmemsize=0x70000000\0"
 365 #else
 366 #define MC_INIT_CMD                             \
 367         "mcinitcmd=env exists secureboot && "   \
 368         "esbc_validate 0x580640000 && "         \
 369         "esbc_validate 0x580680000; "           \
 370         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 371 #endif
 372 #endif
 373
 374 /* Initial environment variables */
 375 #undef CONFIG_EXTRA_ENV_SETTINGS
 376 #ifdef CONFIG_TFABOOT
 377 #define CONFIG_EXTRA_ENV_SETTINGS               \
 378         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 379         "ramdisk_addr=0x800000\0"               \
 380         "ramdisk_size=0x2000000\0"              \
 381         "fdt_high=0xa0000000\0"                 \
 382         "initrd_high=0xffffffffffffffff\0"      \
 383         "fdt_addr=0x64f00000\0"                 \
 384         "kernel_addr=0x581000000\0"             \
 385         "kernel_start=0x1000000\0"              \
 386         "kernelheader_start=0x800000\0"         \
 387         "scriptaddr=0x80000000\0"               \
 388         "scripthdraddr=0x80080000\0"            \
 389         "fdtheader_addr_r=0x80100000\0"         \
 390         "kernelheader_addr_r=0x80200000\0"      \
 391         "kernelheader_addr=0x580600000\0"       \
 392         "kernel_addr_r=0x81000000\0"            \
 393         "kernelheader_size=0x40000\0"           \
 394         "fdt_addr_r=0x90000000\0"               \
 395         "load_addr=0xa0000000\0"                \
 396         "kernel_size=0x2800000\0"               \
 397         "kernel_addr_sd=0x8000\0"               \
 398         "kernel_size_sd=0x14000\0"              \
 399         "console=ttyAMA0,38400n8\0"             \
 400         "mcmemsize=0x70000000\0"                \
 401         "sd_bootcmd=echo Trying load from SD ..;" \
 402         "mmcinfo; mmc read $load_addr "         \
 403         "$kernel_addr_sd $kernel_size_sd && "   \
 404         "bootm $load_addr#$board\0"             \
 405         QSPI_MC_INIT_CMD                                \
 406         BOOTENV                                 \
 407         "boot_scripts=ls2088ardb_boot.scr\0"    \
 408         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 409         "scan_dev_for_boot_part="               \
 410                 "part list ${devtype} ${devnum} devplist; "     \
 411                 "env exists devplist || setenv devplist 1; "    \
 412                 "for distro_bootpart in ${devplist}; do "       \
 413                         "if fstype ${devtype} "                 \
 414                                 "${devnum}:${distro_bootpart} " \
 415                                 "bootfstype; then "             \
 416                                 "run scan_dev_for_boot; "       \
 417                         "fi; "                                  \
 418                 "done\0"                                        \
 419         "boot_a_script="                                        \
 420                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 421                         "${scriptaddr} ${prefix}${script}; "    \
 422                 "env exists secureboot && load ${devtype} "     \
 423                         "${devnum}:${distro_bootpart} "         \
 424                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 425                         "&& esbc_validate ${scripthdraddr};"    \
 426                 "source ${scriptaddr}\0"                        \
 427         "qspi_bootcmd=echo Trying load from qspi..;"            \
 428                 "sf probe && sf read $load_addr "               \
 429                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 430                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 431                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 432                 " bootm $load_addr#$board\0"                    \
 433         "nor_bootcmd=echo Trying load from nor..;"              \
 434                 "cp.b $kernel_addr $load_addr "                 \
 435                 "$kernel_size ; env exists secureboot && "      \
 436                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 437                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 438                 "bootm $load_addr#$board\0"
 439 #else
 440 #define CONFIG_EXTRA_ENV_SETTINGS               \
 441         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 442         "ramdisk_addr=0x800000\0"               \
 443         "ramdisk_size=0x2000000\0"              \
 444         "fdt_high=0xa0000000\0"                 \
 445         "initrd_high=0xffffffffffffffff\0"      \
 446         "fdt_addr=0x64f00000\0"                 \
 447         "kernel_addr=0x581000000\0"             \
 448         "kernel_start=0x1000000\0"              \
 449         "kernelheader_start=0x600000\0"         \
 450         "scriptaddr=0x80000000\0"               \
 451         "scripthdraddr=0x80080000\0"            \
 452         "fdtheader_addr_r=0x80100000\0"         \
 453         "kernelheader_addr_r=0x80200000\0"      \
 454         "kernelheader_addr=0x580600000\0"       \
 455         "kernel_addr_r=0x81000000\0"            \
 456         "kernelheader_size=0x40000\0"           \
 457         "fdt_addr_r=0x90000000\0"               \
 458         "load_addr=0xa0000000\0"                \
 459         "kernel_size=0x2800000\0"               \
 460         "kernel_addr_sd=0x8000\0"               \
 461         "kernel_size_sd=0x14000\0"              \
 462         "console=ttyAMA0,38400n8\0"             \
 463         "mcmemsize=0x70000000\0"                \
 464         "sd_bootcmd=echo Trying load from SD ..;" \
 465         "mmcinfo; mmc read $load_addr "         \
 466         "$kernel_addr_sd $kernel_size_sd && "   \
 467         "bootm $load_addr#$board\0"             \
 468         MC_INIT_CMD                             \
 469         BOOTENV                                 \
 470         "boot_scripts=ls2088ardb_boot.scr\0"    \
 471         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 472         "scan_dev_for_boot_part="               \
 473                 "part list ${devtype} ${devnum} devplist; "     \
 474                 "env exists devplist || setenv devplist 1; "    \
 475                 "for distro_bootpart in ${devplist}; do "       \
 476                         "if fstype ${devtype} "                 \
 477                                 "${devnum}:${distro_bootpart} " \
 478                                 "bootfstype; then "             \
 479                                 "run scan_dev_for_boot; "       \
 480                         "fi; "                                  \
 481                 "done\0"                                        \
 482         "boot_a_script="                                        \
 483                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 484                         "${scriptaddr} ${prefix}${script}; "    \
 485                 "env exists secureboot && load ${devtype} "     \
 486                         "${devnum}:${distro_bootpart} "         \
 487                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 488                         "env exists secureboot "        \
 489                         "&& esbc_validate ${scripthdraddr};"    \
 490                 "source ${scriptaddr}\0"                        \
 491         "qspi_bootcmd=echo Trying load from qspi..;"            \
 492                 "sf probe && sf read $load_addr "               \
 493                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 494                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 495                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 496                 " bootm $load_addr#$board\0"                    \
 497         "nor_bootcmd=echo Trying load from nor..;"              \
 498                 "cp.b $kernel_addr $load_addr "                 \
 499                 "$kernel_size ; env exists secureboot && "      \
 500                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 501                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 502                 "bootm $load_addr#$board\0"
 503 #endif
 504
 505 #ifdef CONFIG_TFABOOT
 506 #define QSPI_NOR_BOOTCOMMAND                                            \
 507                         "sf probe 0:0; "                                \
 508                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 509                         "env exists mcinitcmd && env exists secureboot "\
 510                         "&& esbc_validate 0x806c0000; "                 \
 511                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 512                         "env exists mcinitcmd && "                      \
 513                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 514                         "run distro_bootcmd;run qspi_bootcmd; "         \
 515                         "env exists secureboot && esbc_halt;"
 516
 517 /* Try to boot an on-SD kernel first, then do normal distro boot */
 518 #define SD_BOOTCOMMAND                                          \
 519                         "env exists mcinitcmd && env exists secureboot "\
 520                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 521                         "&& esbc_validate $load_addr; "                 \
 522                         "env exists mcinitcmd && run mcinitcmd "        \
 523                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 524                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 525                         "run distro_bootcmd;run sd_bootcmd; "           \
 526                         "env exists secureboot && esbc_halt;"
 527
 528 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 529 #define IFC_NOR_BOOTCOMMAND                                             \
 530                         "env exists mcinitcmd && env exists secureboot "\
 531                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 532                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 533                         "run distro_bootcmd;run nor_bootcmd; "          \
 534                         "env exists secureboot && esbc_halt;"
 535 #else
 536 #undef CONFIG_BOOTCOMMAND
 537 #ifdef CONFIG_QSPI_BOOT
 538 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 539 #define CONFIG_BOOTCOMMAND                                              \
 540                         "sf probe 0:0; "                                \
 541                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 542                         "env exists mcinitcmd && env exists secureboot "\
 543                         "&& esbc_validate 0x806C0000; "                 \
 544                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 545                         "env exists mcinitcmd && "                      \
 546                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 547                         "run distro_bootcmd;run qspi_bootcmd; "         \
 548                         "env exists secureboot && esbc_halt;"
 549 #elif defined(CONFIG_SD_BOOT)
 550 /* Try to boot an on-SD kernel first, then do normal distro boot */
 551 #define CONFIG_BOOTCOMMAND                                              \
 552                         "env exists mcinitcmd && env exists secureboot "\
 553                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 554                         "&& esbc_validate $load_addr; "                 \
 555                         "env exists mcinitcmd && run mcinitcmd "        \
 556                         "&& mmc read 0x88000000 0x6800 0x800 "          \
 557                         "&& fsl_mc lazyapply dpl 0x88000000; "          \
 558                         "run distro_bootcmd;run sd_bootcmd; "           \
 559                         "env exists secureboot && esbc_halt;"
 560 #else
 561 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 562 #define CONFIG_BOOTCOMMAND                                              \
 563                         "env exists mcinitcmd && env exists secureboot "\
 564                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 565                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 566                         "run distro_bootcmd;run nor_bootcmd; "          \
 567                         "env exists secureboot && esbc_halt;"
 568 #endif
 569 #endif
 570
 571 /* MAC/PHY configuration */
 572 #ifdef CONFIG_FSL_MC_ENET
 573 #ifdef CONFIG_QSPI_BOOT
 574 #define CONFIG_CORTINA_FW_ADDR          0x20980000
 575 #else
 576 #define CONFIG_CORTINA_FW_ADDR          0x580980000
 577 #endif
 578 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 579
 580 #define CORTINA_PHY_ADDR1       0x10
 581 #define CORTINA_PHY_ADDR2       0x11
 582 #define CORTINA_PHY_ADDR3       0x12
 583 #define CORTINA_PHY_ADDR4       0x13
 584 #define AQ_PHY_ADDR1            0x00
 585 #define AQ_PHY_ADDR2            0x01
 586 #define AQ_PHY_ADDR3            0x02
 587 #define AQ_PHY_ADDR4            0x03
 588 #define AQR405_IRQ_MASK         0x36
 589
 590 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 591 #endif
 592
 593 #include <asm/fsl_secure_boot.h>
 594
 595 #endif /* __LS2_RDB_H */