pci: Move CONFIG_PCI_PNP to Kconfig
[platform/kernel/u-boot.git] / include / configs / ls2080aqds.h
1 /*
2  * Copyright 2015 Freescale Semiconductor
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS2_QDS_H
8 #define __LS2_QDS_H
9
10 #include "ls2080a_common.h"
11
12 #ifndef __ASSEMBLY__
13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void);
15 #endif
16
17 #define CONFIG_SYS_FSL_CLK
18
19 #ifdef CONFIG_FSL_QSPI
20 #define CONFIG_SYS_NO_FLASH
21 #undef CONFIG_CMD_IMLS
22 #define CONFIG_QIXIS_I2C_ACCESS
23 #define CONFIG_SYS_I2C_EARLY_INIT
24 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
25 #endif
26
27 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
28 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
29 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
30 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
31
32 #define CONFIG_DDR_SPD
33 #define CONFIG_DDR_ECC
34 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
35 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
36 #define SPD_EEPROM_ADDRESS1     0x51
37 #define SPD_EEPROM_ADDRESS2     0x52
38 #define SPD_EEPROM_ADDRESS3     0x53
39 #define SPD_EEPROM_ADDRESS4     0x54
40 #define SPD_EEPROM_ADDRESS5     0x55
41 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
42 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
43 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
44 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
45 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
46 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
47 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
48 #endif
49 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
50
51 /* SATA */
52 #define CONFIG_LIBATA
53 #define CONFIG_SCSI_AHCI
54 #define CONFIG_SCSI_AHCI_PLAT
55 #define CONFIG_SCSI
56 #define CONFIG_DOS_PARTITION
57 #define CONFIG_BOARD_LATE_INIT
58
59 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
60 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
61
62 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
63 #define CONFIG_SYS_SCSI_MAX_LUN                 1
64 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
65                                                 CONFIG_SYS_SCSI_MAX_LUN)
66
67 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
68
69 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
70 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
71 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
72
73 #define CONFIG_SYS_NOR0_CSPR                                    \
74         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
75         CSPR_PORT_SIZE_16                                       | \
76         CSPR_MSEL_NOR                                           | \
77         CSPR_V)
78 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
79         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
80         CSPR_PORT_SIZE_16                                       | \
81         CSPR_MSEL_NOR                                           | \
82         CSPR_V)
83 #define CONFIG_SYS_NOR1_CSPR                                    \
84         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
85         CSPR_PORT_SIZE_16                                       | \
86         CSPR_MSEL_NOR                                           | \
87         CSPR_V)
88 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
89         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
90         CSPR_PORT_SIZE_16                                       | \
91         CSPR_MSEL_NOR                                           | \
92         CSPR_V)
93 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
94 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
95                                 FTIM0_NOR_TEADC(0x5) | \
96                                 FTIM0_NOR_TEAHC(0x5))
97 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
98                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
99                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
100 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
101                                 FTIM2_NOR_TCH(0x4) | \
102                                 FTIM2_NOR_TWPH(0x0E) | \
103                                 FTIM2_NOR_TWP(0x1c))
104 #define CONFIG_SYS_NOR_FTIM3    0x04000000
105 #define CONFIG_SYS_IFC_CCR      0x01000000
106
107 #ifndef CONFIG_SYS_NO_FLASH
108 #define CONFIG_FLASH_CFI_DRIVER
109 #define CONFIG_SYS_FLASH_CFI
110 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
111 #define CONFIG_SYS_FLASH_QUIET_TEST
112 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
113
114 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
115 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
116 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
117 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
118
119 #define CONFIG_SYS_FLASH_EMPTY_INFO
120 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
121                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
122 #endif
123
124 #define CONFIG_NAND_FSL_IFC
125 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
126 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
127
128 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
129 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
130                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
131                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
132                                 | CSPR_V)
133 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
134
135 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
136                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
137                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
138                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
139                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
140                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
141                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
142
143 #define CONFIG_SYS_NAND_ONFI_DETECTION
144
145 /* ONFI NAND Flash mode0 Timing Params */
146 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
147                                         FTIM0_NAND_TWP(0x18)   | \
148                                         FTIM0_NAND_TWCHT(0x07) | \
149                                         FTIM0_NAND_TWH(0x0a))
150 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
151                                         FTIM1_NAND_TWBE(0x39)  | \
152                                         FTIM1_NAND_TRR(0x0e)   | \
153                                         FTIM1_NAND_TRP(0x18))
154 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
155                                         FTIM2_NAND_TREH(0x0a) | \
156                                         FTIM2_NAND_TWHRE(0x1e))
157 #define CONFIG_SYS_NAND_FTIM3           0x0
158
159 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
160 #define CONFIG_SYS_MAX_NAND_DEVICE      1
161 #define CONFIG_MTD_NAND_VERIFY_WRITE
162 #define CONFIG_CMD_NAND
163
164 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
165
166 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
167 #define QIXIS_LBMAP_SWITCH              0x06
168 #define QIXIS_LBMAP_MASK                0x0f
169 #define QIXIS_LBMAP_SHIFT               0
170 #define QIXIS_LBMAP_DFLTBANK            0x00
171 #define QIXIS_LBMAP_ALTBANK             0x04
172 #define QIXIS_LBMAP_NAND                0x09
173 #define QIXIS_LBMAP_QSPI                0x0f
174 #define QIXIS_RST_CTL_RESET             0x31
175 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
176 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
177 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
178 #define QIXIS_RCW_SRC_NAND              0x107
179 #define QIXIS_RCW_SRC_QSPI              0x62
180 #define QIXIS_RST_FORCE_MEM             0x01
181
182 #define CONFIG_SYS_CSPR3_EXT    (0x0)
183 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
184                                 | CSPR_PORT_SIZE_8 \
185                                 | CSPR_MSEL_GPCM \
186                                 | CSPR_V)
187 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
188                                 | CSPR_PORT_SIZE_8 \
189                                 | CSPR_MSEL_GPCM \
190                                 | CSPR_V)
191
192 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
193 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
194 /* QIXIS Timing parameters for IFC CS3 */
195 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
196                                         FTIM0_GPCM_TEADC(0x0e) | \
197                                         FTIM0_GPCM_TEAHC(0x0e))
198 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
199                                         FTIM1_GPCM_TRAD(0x3f))
200 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
201                                         FTIM2_GPCM_TCH(0xf) | \
202                                         FTIM2_GPCM_TWP(0x3E))
203 #define CONFIG_SYS_CS3_FTIM3            0x0
204
205 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
206 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
207 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
208 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
209 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
210 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
211 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
212 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
213 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
214 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
215 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
216 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
217 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
218 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
219 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
220 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
221 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
222 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
223 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
224 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
225 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
226 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
227 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
228 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
229 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
230 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
231 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
232 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
233
234 #define CONFIG_ENV_IS_IN_NAND
235 #define CONFIG_ENV_OFFSET               (896 * 1024)
236 #define CONFIG_ENV_SECT_SIZE            0x20000
237 #define CONFIG_ENV_SIZE                 0x2000
238 #define CONFIG_SPL_PAD_TO               0x20000
239 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
240 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
241 #else
242 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
243 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
244 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
245 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
246 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
247 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
248 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
249 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
250 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
251 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
252 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
253 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
254 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
255 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
256 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
257 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
258 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
259 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
260 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
261 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
262 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
263 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
264 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
265 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
266 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
267 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
268 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
269
270 #if defined(CONFIG_QSPI_BOOT)
271 #define CONFIG_SYS_TEXT_BASE            0x20010000
272 #define CONFIG_ENV_IS_IN_SPI_FLASH
273 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
274 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
275 #define CONFIG_ENV_SECT_SIZE            0x10000
276 #else
277 #define CONFIG_ENV_IS_IN_FLASH
278 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
279 #define CONFIG_ENV_SECT_SIZE            0x20000
280 #define CONFIG_ENV_SIZE                 0x2000
281 #endif
282 #endif
283
284 /* Debug Server firmware */
285 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
286 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
287
288 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
289
290 /*
291  * I2C
292  */
293 #define I2C_MUX_PCA_ADDR                0x77
294 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
295
296 /* I2C bus multiplexer */
297 #define I2C_MUX_CH_DEFAULT      0x8
298
299 /* SPI */
300 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
301 #define CONFIG_SPI_FLASH
302
303 #ifdef CONFIG_FSL_DSPI
304 #define CONFIG_SPI_FLASH_STMICRO
305 #define CONFIG_SPI_FLASH_SST
306 #define CONFIG_SPI_FLASH_EON
307 #endif
308
309 #ifdef CONFIG_FSL_QSPI
310 #define CONFIG_SPI_FLASH_SPANSION
311 #define FSL_QSPI_FLASH_SIZE             (1 << 26) /* 64MB */
312 #define FSL_QSPI_FLASH_NUM              4
313 #endif
314 /*
315  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
316  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
317  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
318  */
319 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
320
321 #endif
322
323 /*
324  * MMC
325  */
326 #ifdef CONFIG_MMC
327 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
328         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
329 #endif
330
331 /*
332  * RTC configuration
333  */
334 #define RTC
335 #define CONFIG_RTC_DS3231               1
336 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
337 #define CONFIG_CMD_DATE
338
339 /* EEPROM */
340 #define CONFIG_ID_EEPROM
341 #define CONFIG_CMD_EEPROM
342 #define CONFIG_SYS_I2C_EEPROM_NXID
343 #define CONFIG_SYS_EEPROM_BUS_NUM       0
344 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
345 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
346 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
347 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
348
349 #define CONFIG_FSL_MEMAC
350 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
351
352 #ifdef CONFIG_PCI
353 #define CONFIG_PCI_SCAN_SHOW
354 #define CONFIG_CMD_PCI
355 #endif
356
357 /*  MMC  */
358 #define CONFIG_MMC
359 #ifdef CONFIG_MMC
360 #define CONFIG_FSL_ESDHC
361 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
362 #define CONFIG_GENERIC_MMC
363 #define CONFIG_DOS_PARTITION
364 #endif
365
366 /* Initial environment variables */
367 #undef CONFIG_EXTRA_ENV_SETTINGS
368 #define CONFIG_EXTRA_ENV_SETTINGS               \
369         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
370         "loadaddr=0x80100000\0"                 \
371         "kernel_addr=0x100000\0"                \
372         "ramdisk_addr=0x800000\0"               \
373         "ramdisk_size=0x2000000\0"              \
374         "fdt_high=0xa0000000\0"                 \
375         "initrd_high=0xffffffffffffffff\0"      \
376         "kernel_start=0x581100000\0"            \
377         "kernel_load=0xa0000000\0"              \
378         "kernel_size=0x2800000\0"               \
379         "mcinitcmd=fsl_mc start mc 0x580300000" \
380         " 0x580800000 \0"
381
382 #ifdef CONFIG_FSL_MC_ENET
383 #define CONFIG_FSL_MEMAC
384 #define CONFIG_PHYLIB
385 #define CONFIG_PHYLIB_10G
386 #define CONFIG_PHY_VITESSE
387 #define CONFIG_PHY_REALTEK
388 #define CONFIG_PHY_TERANETICS
389 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
390 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
391 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
392 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
393
394 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
395 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
396 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
397 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
398 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
399 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
400 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
401 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
402 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
403 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
404 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
405 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
406 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
407 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
408 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
409 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
410
411 #define CONFIG_MII              /* MII PHY management */
412 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
413 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
414
415 #endif
416
417 /*
418  * USB
419  */
420 #define CONFIG_HAS_FSL_XHCI_USB
421 #define CONFIG_USB_XHCI_FSL
422 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
423 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
424
425 #include <asm/fsl_secure_boot.h>
426
427 #endif /* __LS2_QDS_H */