1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
16 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
17 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
20 #define SPD_EEPROM_ADDRESS1 0x51
21 #define SPD_EEPROM_ADDRESS2 0x52
22 #define SPD_EEPROM_ADDRESS3 0x53
23 #define SPD_EEPROM_ADDRESS4 0x54
24 #define SPD_EEPROM_ADDRESS5 0x55
25 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
26 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
27 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
28 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
29 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
34 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
35 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
37 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
38 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
39 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
41 #define CONFIG_SYS_NOR0_CSPR \
42 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
46 #define CONFIG_SYS_NOR0_CSPR_EARLY \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
51 #define CONFIG_SYS_NOR1_CSPR \
52 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
56 #define CONFIG_SYS_NOR1_CSPR_EARLY \
57 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
61 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
62 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
63 FTIM0_NOR_TEADC(0x5) | \
65 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
66 FTIM1_NOR_TRAD_NOR(0x1a) |\
67 FTIM1_NOR_TSEQRAD_NOR(0x13))
68 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
69 FTIM2_NOR_TCH(0x4) | \
70 FTIM2_NOR_TWPH(0x0E) | \
72 #define CONFIG_SYS_NOR_FTIM3 0x04000000
73 #define CONFIG_SYS_IFC_CCR 0x01000000
75 #ifdef CONFIG_MTD_NOR_FLASH
76 #define CONFIG_SYS_FLASH_QUIET_TEST
77 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
79 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
80 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
81 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
83 #define CONFIG_SYS_FLASH_EMPTY_INFO
84 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
85 CONFIG_SYS_FLASH_BASE + 0x40000000}
88 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
89 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
91 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
92 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
93 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
94 | CSPR_MSEL_NAND /* MSEL = NAND */ \
96 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
98 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
99 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
100 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
101 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
102 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
103 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
104 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
106 /* ONFI NAND Flash mode0 Timing Params */
107 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
108 FTIM0_NAND_TWP(0x18) | \
109 FTIM0_NAND_TWCHT(0x07) | \
110 FTIM0_NAND_TWH(0x0a))
111 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
112 FTIM1_NAND_TWBE(0x39) | \
113 FTIM1_NAND_TRR(0x0e) | \
114 FTIM1_NAND_TRP(0x18))
115 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
116 FTIM2_NAND_TREH(0x0a) | \
117 FTIM2_NAND_TWHRE(0x1e))
118 #define CONFIG_SYS_NAND_FTIM3 0x0
120 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
121 #define CONFIG_SYS_MAX_NAND_DEVICE 1
122 #define CONFIG_MTD_NAND_VERIFY_WRITE
124 #define QIXIS_LBMAP_SWITCH 0x06
125 #define QIXIS_LBMAP_MASK 0x0f
126 #define QIXIS_LBMAP_SHIFT 0
127 #define QIXIS_LBMAP_DFLTBANK 0x00
128 #define QIXIS_LBMAP_ALTBANK 0x04
129 #define QIXIS_LBMAP_NAND 0x09
130 #define QIXIS_LBMAP_SD 0x00
131 #define QIXIS_LBMAP_QSPI 0x0f
132 #define QIXIS_RST_CTL_RESET 0x31
133 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
134 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
135 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
136 #define QIXIS_RCW_SRC_NAND 0x107
137 #define QIXIS_RCW_SRC_SD 0x40
138 #define QIXIS_RCW_SRC_QSPI 0x62
139 #define QIXIS_RST_FORCE_MEM 0x01
141 #define CONFIG_SYS_CSPR3_EXT (0x0)
142 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
146 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
151 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
152 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
153 /* QIXIS Timing parameters for IFC CS3 */
154 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
155 FTIM0_GPCM_TEADC(0x0e) | \
156 FTIM0_GPCM_TEAHC(0x0e))
157 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
158 FTIM1_GPCM_TRAD(0x3f))
159 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
160 FTIM2_GPCM_TCH(0xf) | \
161 FTIM2_GPCM_TWP(0x3E))
162 #define CONFIG_SYS_CS3_FTIM3 0x0
164 #if defined(CONFIG_SPL)
165 #if defined(CONFIG_NAND_BOOT)
166 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
167 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
168 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
169 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
170 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
171 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
172 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
173 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
174 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
175 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
176 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
177 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
178 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
179 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
180 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
181 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
182 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
183 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
184 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
185 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
186 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
187 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
188 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
189 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
190 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
191 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
192 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
194 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
197 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
198 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
199 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
200 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
201 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
202 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
203 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
204 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
205 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
206 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
207 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
208 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
209 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
210 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
211 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
212 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
213 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
214 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
215 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
216 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
217 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
218 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
219 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
220 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
221 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
222 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
223 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
226 /* Debug Server firmware */
227 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
228 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
230 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
235 #define I2C_MUX_PCA_ADDR 0x77
236 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
238 /* I2C bus multiplexer */
239 #define I2C_MUX_CH_DEFAULT 0x8
244 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
245 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
246 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
248 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
254 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
255 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
262 #define CONFIG_RTC_DS3231 1
263 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
266 #define CONFIG_SYS_I2C_EEPROM_NXID
267 #define CONFIG_SYS_EEPROM_BUS_NUM 0
269 #define CONFIG_FSL_MEMAC
272 #define CONFIG_PCI_SCAN_SHOW
275 /* Initial environment variables */
276 #undef CONFIG_EXTRA_ENV_SETTINGS
277 #ifdef CONFIG_NXP_ESBC
278 #define CONFIG_EXTRA_ENV_SETTINGS \
279 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
280 "loadaddr=0x80100000\0" \
281 "kernel_addr=0x100000\0" \
282 "ramdisk_addr=0x800000\0" \
283 "ramdisk_size=0x2000000\0" \
284 "fdt_high=0xa0000000\0" \
285 "initrd_high=0xffffffffffffffff\0" \
286 "kernel_start=0x581000000\0" \
287 "kernel_load=0xa0000000\0" \
288 "kernel_size=0x2800000\0" \
289 "mcmemsize=0x40000000\0" \
290 "mcinitcmd=esbc_validate 0x580640000;" \
291 "esbc_validate 0x580680000;" \
292 "fsl_mc start mc 0x580a00000" \
295 #ifdef CONFIG_TFABOOT
296 #define SD_MC_INIT_CMD \
297 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
298 "mmc read 0x80e00000 0x7000 0x800;" \
299 "fsl_mc start mc 0x80a00000 0x80e00000\0"
300 #define IFC_MC_INIT_CMD \
301 "fsl_mc start mc 0x580a00000" \
303 #define CONFIG_EXTRA_ENV_SETTINGS \
304 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
305 "loadaddr=0x80100000\0" \
306 "loadaddr_sd=0x90100000\0" \
307 "kernel_addr=0x581000000\0" \
308 "kernel_addr_sd=0x8000\0" \
309 "ramdisk_addr=0x800000\0" \
310 "ramdisk_size=0x2000000\0" \
311 "fdt_high=0xa0000000\0" \
312 "initrd_high=0xffffffffffffffff\0" \
313 "kernel_start=0x581000000\0" \
314 "kernel_start_sd=0x8000\0" \
315 "kernel_load=0xa0000000\0" \
316 "kernel_size=0x2800000\0" \
317 "kernel_size_sd=0x14000\0" \
318 "load_addr=0xa0000000\0" \
319 "kernelheader_addr=0x580600000\0" \
320 "kernelheader_addr_r=0x80200000\0" \
321 "kernelheader_size=0x40000\0" \
322 "BOARD=ls2088aqds\0" \
323 "mcmemsize=0x70000000 \0" \
324 "scriptaddr=0x80000000\0" \
325 "scripthdraddr=0x80080000\0" \
328 "boot_scripts=ls2088aqds_boot.scr\0" \
329 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
330 "scan_dev_for_boot_part=" \
331 "part list ${devtype} ${devnum} devplist; " \
332 "env exists devplist || setenv devplist 1; " \
333 "for distro_bootpart in ${devplist}; do " \
334 "if fstype ${devtype} " \
335 "${devnum}:${distro_bootpart} " \
336 "bootfstype; then " \
337 "run scan_dev_for_boot; " \
341 "load ${devtype} ${devnum}:${distro_bootpart} " \
342 "${scriptaddr} ${prefix}${script}; " \
343 "env exists secureboot && load ${devtype} " \
344 "${devnum}:${distro_bootpart} " \
345 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
346 "&& esbc_validate ${scripthdraddr};" \
347 "source ${scriptaddr}\0" \
348 "nor_bootcmd=echo Trying load from nor..;" \
349 "cp.b $kernel_addr $load_addr " \
350 "$kernel_size ; env exists secureboot && " \
351 "cp.b $kernelheader_addr $kernelheader_addr_r " \
352 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
353 "bootm $load_addr#$BOARD\0" \
354 "sd_bootcmd=echo Trying load from SD ..;" \
355 "mmcinfo; mmc read $load_addr " \
356 "$kernel_addr_sd $kernel_size_sd && " \
357 "bootm $load_addr#$BOARD\0"
358 #elif defined(CONFIG_SD_BOOT)
359 #define CONFIG_EXTRA_ENV_SETTINGS \
360 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
361 "loadaddr=0x90100000\0" \
362 "kernel_addr=0x800\0" \
363 "ramdisk_addr=0x800000\0" \
364 "ramdisk_size=0x2000000\0" \
365 "fdt_high=0xa0000000\0" \
366 "initrd_high=0xffffffffffffffff\0" \
367 "kernel_start=0x8000\0" \
368 "kernel_load=0xa0000000\0" \
369 "kernel_size=0x14000\0" \
370 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
371 "mmc read 0x80e00000 0x7000 0x800;" \
372 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
373 "mcmemsize=0x70000000 \0"
375 #define CONFIG_EXTRA_ENV_SETTINGS \
376 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
377 "loadaddr=0x80100000\0" \
378 "kernel_addr=0x100000\0" \
379 "ramdisk_addr=0x800000\0" \
380 "ramdisk_size=0x2000000\0" \
381 "fdt_high=0xa0000000\0" \
382 "initrd_high=0xffffffffffffffff\0" \
383 "kernel_start=0x581000000\0" \
384 "kernel_load=0xa0000000\0" \
385 "kernel_size=0x2800000\0" \
386 "mcmemsize=0x40000000\0" \
387 "mcinitcmd=fsl_mc start mc 0x580a00000" \
389 #endif /* CONFIG_TFABOOT */
390 #endif /* CONFIG_NXP_ESBC */
392 #ifdef CONFIG_TFABOOT
393 #define BOOT_TARGET_DEVICES(func) \
396 func(SCSI, scsi, 0) \
398 #include <config_distro_bootcmd.h>
400 #define SD_BOOTCOMMAND \
401 "env exists mcinitcmd && env exists secureboot "\
402 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
403 "&& esbc_validate $load_addr; " \
404 "env exists mcinitcmd && run mcinitcmd " \
405 "&& mmc read 0x80d00000 0x6800 0x800 " \
406 "&& fsl_mc lazyapply dpl 0x80d00000; " \
407 "run distro_bootcmd;run sd_bootcmd; " \
408 "env exists secureboot && esbc_halt;"
410 #define IFC_NOR_BOOTCOMMAND \
411 "env exists mcinitcmd && env exists secureboot "\
412 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
413 "&& fsl_mc lazyapply dpl 0x580d00000;" \
414 "run distro_bootcmd;run nor_bootcmd; " \
415 "env exists secureboot && esbc_halt;"
418 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
419 #define CONFIG_FSL_MEMAC
420 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
421 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
422 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
423 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
425 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
426 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
427 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
428 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
429 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
430 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
431 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
432 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
433 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
434 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
435 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
436 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
437 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
438 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
439 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
440 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
444 #include <asm/fsl_secure_boot.h>
446 #endif /* __LS2_QDS_H */