include/configs/ls2080aqds.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #define CONFIG_DISPLAY_BOARDINFO
  13
  14 #ifndef __ASSEMBLY__
  15 unsigned long get_board_sys_clk(void);
  16 unsigned long get_board_ddr_clk(void);
  17 #endif
  18
  19 #define CONFIG_SYS_FSL_CLK
  20
  21 #ifdef CONFIG_FSL_QSPI
  22 #define CONFIG_SYS_NO_FLASH
  23 #undef CONFIG_CMD_IMLS
  24 #define CONFIG_QIXIS_I2C_ACCESS
  25 #define CONFIG_SYS_I2C_EARLY_INIT
  26 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  27 #endif
  28
  29 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  30 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  31 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  32 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  33
  34 #define CONFIG_DDR_SPD
  35 #define CONFIG_DDR_ECC
  36 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  37 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  38 #define SPD_EEPROM_ADDRESS1     0x51
  39 #define SPD_EEPROM_ADDRESS2     0x52
  40 #define SPD_EEPROM_ADDRESS3     0x53
  41 #define SPD_EEPROM_ADDRESS4     0x54
  42 #define SPD_EEPROM_ADDRESS5     0x55
  43 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  44 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  45 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  46 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  47 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  48 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  49 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  50 #endif
  51 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  52
  53 /* SATA */
  54 #define CONFIG_LIBATA
  55 #define CONFIG_SCSI_AHCI
  56 #define CONFIG_SCSI_AHCI_PLAT
  57 #define CONFIG_SCSI
  58 #define CONFIG_DOS_PARTITION
  59 #define CONFIG_BOARD_LATE_INIT
  60
  61 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  62 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  63
  64 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  65 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  66 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  67                                                 CONFIG_SYS_SCSI_MAX_LUN)
  68
  69 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  70
  71 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  72 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  73 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  74
  75 #define CONFIG_SYS_NOR0_CSPR                                    \
  76         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  77         CSPR_PORT_SIZE_16                                       | \
  78         CSPR_MSEL_NOR                                           | \
  79         CSPR_V)
  80 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  81         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  82         CSPR_PORT_SIZE_16                                       | \
  83         CSPR_MSEL_NOR                                           | \
  84         CSPR_V)
  85 #define CONFIG_SYS_NOR1_CSPR                                    \
  86         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  87         CSPR_PORT_SIZE_16                                       | \
  88         CSPR_MSEL_NOR                                           | \
  89         CSPR_V)
  90 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  91         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  92         CSPR_PORT_SIZE_16                                       | \
  93         CSPR_MSEL_NOR                                           | \
  94         CSPR_V)
  95 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  96 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  97                                 FTIM0_NOR_TEADC(0x5) | \
  98                                 FTIM0_NOR_TEAHC(0x5))
  99 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 100                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
 101                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 102 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 103                                 FTIM2_NOR_TCH(0x4) | \
 104                                 FTIM2_NOR_TWPH(0x0E) | \
 105                                 FTIM2_NOR_TWP(0x1c))
 106 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 107 #define CONFIG_SYS_IFC_CCR      0x01000000
 108
 109 #ifndef CONFIG_SYS_NO_FLASH
 110 #define CONFIG_FLASH_CFI_DRIVER
 111 #define CONFIG_SYS_FLASH_CFI
 112 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 113 #define CONFIG_SYS_FLASH_QUIET_TEST
 114 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 115
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 118 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 119 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 120
 121 #define CONFIG_SYS_FLASH_EMPTY_INFO
 122 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 123                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 124 #endif
 125
 126 #define CONFIG_NAND_FSL_IFC
 127 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 128 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 129
 130 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 131 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 132                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 133                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 134                                 | CSPR_V)
 135 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 136
 137 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 138                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 139                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 140                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 141                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 142                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 143                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 144
 145 #define CONFIG_SYS_NAND_ONFI_DETECTION
 146
 147 /* ONFI NAND Flash mode0 Timing Params */
 148 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 149                                         FTIM0_NAND_TWP(0x18)   | \
 150                                         FTIM0_NAND_TWCHT(0x07) | \
 151                                         FTIM0_NAND_TWH(0x0a))
 152 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 153                                         FTIM1_NAND_TWBE(0x39)  | \
 154                                         FTIM1_NAND_TRR(0x0e)   | \
 155                                         FTIM1_NAND_TRP(0x18))
 156 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 157                                         FTIM2_NAND_TREH(0x0a) | \
 158                                         FTIM2_NAND_TWHRE(0x1e))
 159 #define CONFIG_SYS_NAND_FTIM3           0x0
 160
 161 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 162 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 163 #define CONFIG_MTD_NAND_VERIFY_WRITE
 164 #define CONFIG_CMD_NAND
 165
 166 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 167
 168 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 169 #define QIXIS_LBMAP_SWITCH              0x06
 170 #define QIXIS_LBMAP_MASK                0x0f
 171 #define QIXIS_LBMAP_SHIFT               0
 172 #define QIXIS_LBMAP_DFLTBANK            0x00
 173 #define QIXIS_LBMAP_ALTBANK             0x04
 174 #define QIXIS_LBMAP_NAND                0x09
 175 #define QIXIS_RST_CTL_RESET             0x31
 176 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 177 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 178 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 179 #define QIXIS_RCW_SRC_NAND              0x107
 180 #define QIXIS_RST_FORCE_MEM             0x01
 181
 182 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 183 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 184                                 | CSPR_PORT_SIZE_8 \
 185                                 | CSPR_MSEL_GPCM \
 186                                 | CSPR_V)
 187 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 188                                 | CSPR_PORT_SIZE_8 \
 189                                 | CSPR_MSEL_GPCM \
 190                                 | CSPR_V)
 191
 192 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 193 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 194 /* QIXIS Timing parameters for IFC CS3 */
 195 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 196                                         FTIM0_GPCM_TEADC(0x0e) | \
 197                                         FTIM0_GPCM_TEAHC(0x0e))
 198 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 199                                         FTIM1_GPCM_TRAD(0x3f))
 200 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 201                                         FTIM2_GPCM_TCH(0xf) | \
 202                                         FTIM2_GPCM_TWP(0x3E))
 203 #define CONFIG_SYS_CS3_FTIM3            0x0
 204
 205 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 206 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 208 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 209 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 210 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 211 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 212 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 213 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 214 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 215 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 216 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 217 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 218 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 219 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 220 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 221 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 222 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 223 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 224 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 225 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 226 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 227 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 228 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 229 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 230 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 231 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 232 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 233
 234 #define CONFIG_ENV_IS_IN_NAND
 235 #define CONFIG_ENV_OFFSET               (896 * 1024)
 236 #define CONFIG_ENV_SECT_SIZE            0x20000
 237 #define CONFIG_ENV_SIZE                 0x2000
 238 #define CONFIG_SPL_PAD_TO               0x20000
 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
 240 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 241 #else
 242 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 243 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 244 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 245 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 246 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 247 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 248 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 249 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 250 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 251 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 252 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 253 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 254 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 255 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 256 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 257 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 258 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 259 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 260 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 261 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 262 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 263 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 264 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 265 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 266 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 267 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 268 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 269
 270 #define CONFIG_ENV_IS_IN_FLASH
 271 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 272 #define CONFIG_ENV_SECT_SIZE            0x20000
 273 #define CONFIG_ENV_SIZE                 0x2000
 274 #endif
 275
 276 /* Debug Server firmware */
 277 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 278 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 279
 280 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 281
 282 /*
 283  * I2C
 284  */
 285 #define I2C_MUX_PCA_ADDR                0x77
 286 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 287
 288 /* I2C bus multiplexer */
 289 #define I2C_MUX_CH_DEFAULT      0x8
 290
 291 /* SPI */
 292 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 293 #define CONFIG_SPI_FLASH
 294
 295 #ifdef CONFIG_FSL_DSPI
 296 #define CONFIG_SPI_FLASH_STMICRO
 297 #define CONFIG_SPI_FLASH_SST
 298 #define CONFIG_SPI_FLASH_EON
 299 #endif
 300
 301 #ifdef CONFIG_FSL_QSPI
 302 #define CONFIG_SPI_FLASH_SPANSION
 303 #define FSL_QSPI_FLASH_SIZE             (1 << 26) /* 64MB */
 304 #define FSL_QSPI_FLASH_NUM              4
 305 #endif
 306 /*
 307  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 308  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 309  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 310  */
 311 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 312
 313 #endif
 314
 315 /*
 316  * MMC
 317  */
 318 #ifdef CONFIG_MMC
 319 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 320         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 321 #endif
 322
 323 /*
 324  * RTC configuration
 325  */
 326 #define RTC
 327 #define CONFIG_RTC_DS3231               1
 328 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 329 #define CONFIG_CMD_DATE
 330
 331 /* EEPROM */
 332 #define CONFIG_ID_EEPROM
 333 #define CONFIG_CMD_EEPROM
 334 #define CONFIG_SYS_I2C_EEPROM_NXID
 335 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 336 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 338 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 340
 341 #define CONFIG_FSL_MEMAC
 342 #define CONFIG_PCI              /* Enable PCIE */
 343 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 344
 345 #ifdef CONFIG_PCI
 346 #define CONFIG_PCI_PNP
 347 #define CONFIG_PCI_SCAN_SHOW
 348 #define CONFIG_CMD_PCI
 349 #endif
 350
 351 /*  MMC  */
 352 #define CONFIG_MMC
 353 #ifdef CONFIG_MMC
 354 #define CONFIG_FSL_ESDHC
 355 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 356 #define CONFIG_GENERIC_MMC
 357 #define CONFIG_DOS_PARTITION
 358 #endif
 359
 360 /* Initial environment variables */
 361 #undef CONFIG_EXTRA_ENV_SETTINGS
 362 #define CONFIG_EXTRA_ENV_SETTINGS               \
 363         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 364         "loadaddr=0x80100000\0"                 \
 365         "kernel_addr=0x100000\0"                \
 366         "ramdisk_addr=0x800000\0"               \
 367         "ramdisk_size=0x2000000\0"              \
 368         "fdt_high=0xa0000000\0"                 \
 369         "initrd_high=0xffffffffffffffff\0"      \
 370         "kernel_start=0x581100000\0"            \
 371         "kernel_load=0xa0000000\0"              \
 372         "kernel_size=0x2800000\0"               \
 373         "mcinitcmd=fsl_mc start mc 0x580300000" \
 374         " 0x580800000 \0"
 375
 376 #ifdef CONFIG_FSL_MC_ENET
 377 #define CONFIG_FSL_MEMAC
 378 #define CONFIG_PHYLIB
 379 #define CONFIG_PHYLIB_10G
 380 #define CONFIG_PHY_VITESSE
 381 #define CONFIG_PHY_REALTEK
 382 #define CONFIG_PHY_TERANETICS
 383 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 384 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 385 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 386 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 387
 388 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 389 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 390 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 391 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 392 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 393 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 394 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 395 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 396 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 397 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 398 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 399 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 400 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 401 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 402 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 403 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 404
 405 #define CONFIG_MII              /* MII PHY management */
 406 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 407 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 408
 409 #endif
 410
 411 /*
 412  * USB
 413  */
 414 #define CONFIG_HAS_FSL_XHCI_USB
 415 #define CONFIG_USB_XHCI_FSL
 416 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 417 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 418 #define CONFIG_USB_STORAGE
 419
 420 #include <asm/fsl_secure_boot.h>
 421
 422 #endif /* __LS2_QDS_H */