1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
16 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
17 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
20 #define SPD_EEPROM_ADDRESS1 0x51
21 #define SPD_EEPROM_ADDRESS2 0x52
22 #define SPD_EEPROM_ADDRESS3 0x53
23 #define SPD_EEPROM_ADDRESS4 0x54
24 #define SPD_EEPROM_ADDRESS5 0x55
25 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
26 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
28 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
29 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
30 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
32 #define CONFIG_SYS_NOR0_CSPR \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
37 #define CONFIG_SYS_NOR0_CSPR_EARLY \
38 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
42 #define CONFIG_SYS_NOR1_CSPR \
43 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
47 #define CONFIG_SYS_NOR1_CSPR_EARLY \
48 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
52 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
53 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
54 FTIM0_NOR_TEADC(0x5) | \
56 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
57 FTIM1_NOR_TRAD_NOR(0x1a) |\
58 FTIM1_NOR_TSEQRAD_NOR(0x13))
59 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
60 FTIM2_NOR_TCH(0x4) | \
61 FTIM2_NOR_TWPH(0x0E) | \
63 #define CONFIG_SYS_NOR_FTIM3 0x04000000
64 #define CONFIG_SYS_IFC_CCR 0x01000000
66 #ifdef CONFIG_MTD_NOR_FLASH
67 #define CONFIG_SYS_FLASH_QUIET_TEST
68 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
70 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
72 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
73 CONFIG_SYS_FLASH_BASE + 0x40000000}
76 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
77 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
79 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
80 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
81 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
82 | CSPR_MSEL_NAND /* MSEL = NAND */ \
84 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
86 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
87 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
88 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
89 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
90 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
91 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
92 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
94 /* ONFI NAND Flash mode0 Timing Params */
95 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
96 FTIM0_NAND_TWP(0x18) | \
97 FTIM0_NAND_TWCHT(0x07) | \
99 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
100 FTIM1_NAND_TWBE(0x39) | \
101 FTIM1_NAND_TRR(0x0e) | \
102 FTIM1_NAND_TRP(0x18))
103 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
104 FTIM2_NAND_TREH(0x0a) | \
105 FTIM2_NAND_TWHRE(0x1e))
106 #define CONFIG_SYS_NAND_FTIM3 0x0
108 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
109 #define CONFIG_SYS_MAX_NAND_DEVICE 1
110 #define CONFIG_MTD_NAND_VERIFY_WRITE
112 #define QIXIS_LBMAP_SWITCH 0x06
113 #define QIXIS_LBMAP_MASK 0x0f
114 #define QIXIS_LBMAP_SHIFT 0
115 #define QIXIS_LBMAP_DFLTBANK 0x00
116 #define QIXIS_LBMAP_ALTBANK 0x04
117 #define QIXIS_LBMAP_NAND 0x09
118 #define QIXIS_LBMAP_SD 0x00
119 #define QIXIS_LBMAP_QSPI 0x0f
120 #define QIXIS_RST_CTL_RESET 0x31
121 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
122 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
123 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
124 #define QIXIS_RCW_SRC_NAND 0x107
125 #define QIXIS_RCW_SRC_SD 0x40
126 #define QIXIS_RCW_SRC_QSPI 0x62
127 #define QIXIS_RST_FORCE_MEM 0x01
129 #define CONFIG_SYS_CSPR3_EXT (0x0)
130 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
134 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
139 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
140 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
141 /* QIXIS Timing parameters for IFC CS3 */
142 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
143 FTIM0_GPCM_TEADC(0x0e) | \
144 FTIM0_GPCM_TEAHC(0x0e))
145 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
146 FTIM1_GPCM_TRAD(0x3f))
147 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
148 FTIM2_GPCM_TCH(0xf) | \
149 FTIM2_GPCM_TWP(0x3E))
150 #define CONFIG_SYS_CS3_FTIM3 0x0
152 #if defined(CONFIG_SPL)
153 #if defined(CONFIG_NAND_BOOT)
154 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
155 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
156 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
157 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
158 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
159 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
160 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
161 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
162 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
163 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
164 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
165 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
166 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
167 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
168 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
169 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
170 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
171 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
172 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
173 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
174 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
175 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
176 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
177 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
178 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
179 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
180 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
182 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
185 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
186 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
187 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
188 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
189 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
190 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
191 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
192 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
193 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
194 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
195 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
196 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
197 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
198 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
199 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
200 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
201 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
202 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
203 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
205 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
206 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
207 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
208 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
209 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
210 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
211 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
214 /* Debug Server firmware */
215 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
216 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
218 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
223 #define I2C_MUX_PCA_ADDR 0x77
224 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
226 /* I2C bus multiplexer */
227 #define I2C_MUX_CH_DEFAULT 0x8
232 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
233 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
234 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
236 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
242 #define CONFIG_RTC_DS3231 1
243 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
246 #define CONFIG_SYS_I2C_EEPROM_NXID
247 #define CONFIG_SYS_EEPROM_BUS_NUM 0
249 #define CONFIG_FSL_MEMAC
251 /* Initial environment variables */
252 #undef CONFIG_EXTRA_ENV_SETTINGS
253 #ifdef CONFIG_NXP_ESBC
254 #define CONFIG_EXTRA_ENV_SETTINGS \
255 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
256 "loadaddr=0x80100000\0" \
257 "kernel_addr=0x100000\0" \
258 "ramdisk_addr=0x800000\0" \
259 "ramdisk_size=0x2000000\0" \
260 "fdt_high=0xa0000000\0" \
261 "initrd_high=0xffffffffffffffff\0" \
262 "kernel_start=0x581000000\0" \
263 "kernel_load=0xa0000000\0" \
264 "kernel_size=0x2800000\0" \
265 "mcmemsize=0x40000000\0" \
266 "mcinitcmd=esbc_validate 0x580640000;" \
267 "esbc_validate 0x580680000;" \
268 "fsl_mc start mc 0x580a00000" \
271 #ifdef CONFIG_TFABOOT
272 #define SD_MC_INIT_CMD \
273 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
274 "mmc read 0x80e00000 0x7000 0x800;" \
275 "fsl_mc start mc 0x80a00000 0x80e00000\0"
276 #define IFC_MC_INIT_CMD \
277 "fsl_mc start mc 0x580a00000" \
279 #define CONFIG_EXTRA_ENV_SETTINGS \
280 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
281 "loadaddr=0x80100000\0" \
282 "loadaddr_sd=0x90100000\0" \
283 "kernel_addr=0x581000000\0" \
284 "kernel_addr_sd=0x8000\0" \
285 "ramdisk_addr=0x800000\0" \
286 "ramdisk_size=0x2000000\0" \
287 "fdt_high=0xa0000000\0" \
288 "initrd_high=0xffffffffffffffff\0" \
289 "kernel_start=0x581000000\0" \
290 "kernel_start_sd=0x8000\0" \
291 "kernel_load=0xa0000000\0" \
292 "kernel_size=0x2800000\0" \
293 "kernel_size_sd=0x14000\0" \
294 "load_addr=0xa0000000\0" \
295 "kernelheader_addr=0x580600000\0" \
296 "kernelheader_addr_r=0x80200000\0" \
297 "kernelheader_size=0x40000\0" \
298 "BOARD=ls2088aqds\0" \
299 "mcmemsize=0x70000000 \0" \
300 "scriptaddr=0x80000000\0" \
301 "scripthdraddr=0x80080000\0" \
304 "boot_scripts=ls2088aqds_boot.scr\0" \
305 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
306 "scan_dev_for_boot_part=" \
307 "part list ${devtype} ${devnum} devplist; " \
308 "env exists devplist || setenv devplist 1; " \
309 "for distro_bootpart in ${devplist}; do " \
310 "if fstype ${devtype} " \
311 "${devnum}:${distro_bootpart} " \
312 "bootfstype; then " \
313 "run scan_dev_for_boot; " \
317 "load ${devtype} ${devnum}:${distro_bootpart} " \
318 "${scriptaddr} ${prefix}${script}; " \
319 "env exists secureboot && load ${devtype} " \
320 "${devnum}:${distro_bootpart} " \
321 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
322 "&& esbc_validate ${scripthdraddr};" \
323 "source ${scriptaddr}\0" \
324 "nor_bootcmd=echo Trying load from nor..;" \
325 "cp.b $kernel_addr $load_addr " \
326 "$kernel_size ; env exists secureboot && " \
327 "cp.b $kernelheader_addr $kernelheader_addr_r " \
328 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
329 "bootm $load_addr#$BOARD\0" \
330 "sd_bootcmd=echo Trying load from SD ..;" \
331 "mmcinfo; mmc read $load_addr " \
332 "$kernel_addr_sd $kernel_size_sd && " \
333 "bootm $load_addr#$BOARD\0"
334 #elif defined(CONFIG_SD_BOOT)
335 #define CONFIG_EXTRA_ENV_SETTINGS \
336 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
337 "loadaddr=0x90100000\0" \
338 "kernel_addr=0x800\0" \
339 "ramdisk_addr=0x800000\0" \
340 "ramdisk_size=0x2000000\0" \
341 "fdt_high=0xa0000000\0" \
342 "initrd_high=0xffffffffffffffff\0" \
343 "kernel_start=0x8000\0" \
344 "kernel_load=0xa0000000\0" \
345 "kernel_size=0x14000\0" \
346 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
347 "mmc read 0x80e00000 0x7000 0x800;" \
348 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
349 "mcmemsize=0x70000000 \0"
351 #define CONFIG_EXTRA_ENV_SETTINGS \
352 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
353 "loadaddr=0x80100000\0" \
354 "kernel_addr=0x100000\0" \
355 "ramdisk_addr=0x800000\0" \
356 "ramdisk_size=0x2000000\0" \
357 "fdt_high=0xa0000000\0" \
358 "initrd_high=0xffffffffffffffff\0" \
359 "kernel_start=0x581000000\0" \
360 "kernel_load=0xa0000000\0" \
361 "kernel_size=0x2800000\0" \
362 "mcmemsize=0x40000000\0" \
363 "mcinitcmd=fsl_mc start mc 0x580a00000" \
365 #endif /* CONFIG_TFABOOT */
366 #endif /* CONFIG_NXP_ESBC */
368 #ifdef CONFIG_TFABOOT
369 #define BOOT_TARGET_DEVICES(func) \
372 func(SCSI, scsi, 0) \
374 #include <config_distro_bootcmd.h>
376 #define SD_BOOTCOMMAND \
377 "env exists mcinitcmd && env exists secureboot "\
378 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
379 "&& esbc_validate $load_addr; " \
380 "env exists mcinitcmd && run mcinitcmd " \
381 "&& mmc read 0x80d00000 0x6800 0x800 " \
382 "&& fsl_mc lazyapply dpl 0x80d00000; " \
383 "run distro_bootcmd;run sd_bootcmd; " \
384 "env exists secureboot && esbc_halt;"
386 #define IFC_NOR_BOOTCOMMAND \
387 "env exists mcinitcmd && env exists secureboot "\
388 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
389 "&& fsl_mc lazyapply dpl 0x580d00000;" \
390 "run distro_bootcmd;run nor_bootcmd; " \
391 "env exists secureboot && esbc_halt;"
394 #if defined(CONFIG_FSL_MC_ENET)
395 #define CONFIG_FSL_MEMAC
396 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
397 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
398 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
399 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
401 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
402 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
403 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
404 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
405 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
406 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
407 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
408 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
409 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
410 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
411 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
412 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
413 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
414 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
415 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
416 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
420 #include <asm/fsl_secure_boot.h>
422 #endif /* __LS2_QDS_H */