include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  14 #endif
  15
  16 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  17 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  18
  19 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  20 #define SPD_EEPROM_ADDRESS1     0x51
  21 #define SPD_EEPROM_ADDRESS2     0x52
  22 #define SPD_EEPROM_ADDRESS3     0x53
  23 #define SPD_EEPROM_ADDRESS4     0x54
  24 #define SPD_EEPROM_ADDRESS5     0x55
  25 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  26 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  27 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  28 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  29 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  30 #endif
  31
  32 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  33 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  34 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  35
  36 #define CONFIG_SYS_NOR0_CSPR                                    \
  37         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  38         CSPR_PORT_SIZE_16                                       | \
  39         CSPR_MSEL_NOR                                           | \
  40         CSPR_V)
  41 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  42         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  43         CSPR_PORT_SIZE_16                                       | \
  44         CSPR_MSEL_NOR                                           | \
  45         CSPR_V)
  46 #define CONFIG_SYS_NOR1_CSPR                                    \
  47         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  48         CSPR_PORT_SIZE_16                                       | \
  49         CSPR_MSEL_NOR                                           | \
  50         CSPR_V)
  51 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  52         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  53         CSPR_PORT_SIZE_16                                       | \
  54         CSPR_MSEL_NOR                                           | \
  55         CSPR_V)
  56 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  57 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  58                                 FTIM0_NOR_TEADC(0x5) | \
  59                                 FTIM0_NOR_TEAHC(0x5))
  60 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  61                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  62                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  63 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  64                                 FTIM2_NOR_TCH(0x4) | \
  65                                 FTIM2_NOR_TWPH(0x0E) | \
  66                                 FTIM2_NOR_TWP(0x1c))
  67 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  68 #define CONFIG_SYS_IFC_CCR      0x01000000
  69
  70 #ifdef CONFIG_MTD_NOR_FLASH
  71 #define CONFIG_SYS_FLASH_QUIET_TEST
  72 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  73
  74 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  75 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  76 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  77
  78 #define CONFIG_SYS_FLASH_EMPTY_INFO
  79 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  80                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  81 #endif
  82
  83 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  84 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  85
  86 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  87 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  88                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  89                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  90                                 | CSPR_V)
  91 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  92
  93 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  94                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  95                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  96                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  97                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  98                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  99                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 100
 101 /* ONFI NAND Flash mode0 Timing Params */
 102 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 103                                         FTIM0_NAND_TWP(0x18)   | \
 104                                         FTIM0_NAND_TWCHT(0x07) | \
 105                                         FTIM0_NAND_TWH(0x0a))
 106 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 107                                         FTIM1_NAND_TWBE(0x39)  | \
 108                                         FTIM1_NAND_TRR(0x0e)   | \
 109                                         FTIM1_NAND_TRP(0x18))
 110 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 111                                         FTIM2_NAND_TREH(0x0a) | \
 112                                         FTIM2_NAND_TWHRE(0x1e))
 113 #define CONFIG_SYS_NAND_FTIM3           0x0
 114
 115 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 116 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 117 #define CONFIG_MTD_NAND_VERIFY_WRITE
 118
 119 #define QIXIS_LBMAP_SWITCH              0x06
 120 #define QIXIS_LBMAP_MASK                0x0f
 121 #define QIXIS_LBMAP_SHIFT               0
 122 #define QIXIS_LBMAP_DFLTBANK            0x00
 123 #define QIXIS_LBMAP_ALTBANK             0x04
 124 #define QIXIS_LBMAP_NAND                0x09
 125 #define QIXIS_LBMAP_SD                  0x00
 126 #define QIXIS_LBMAP_QSPI                0x0f
 127 #define QIXIS_RST_CTL_RESET             0x31
 128 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 129 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 130 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 131 #define QIXIS_RCW_SRC_NAND              0x107
 132 #define QIXIS_RCW_SRC_SD                0x40
 133 #define QIXIS_RCW_SRC_QSPI              0x62
 134 #define QIXIS_RST_FORCE_MEM             0x01
 135
 136 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 137 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 138                                 | CSPR_PORT_SIZE_8 \
 139                                 | CSPR_MSEL_GPCM \
 140                                 | CSPR_V)
 141 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 142                                 | CSPR_PORT_SIZE_8 \
 143                                 | CSPR_MSEL_GPCM \
 144                                 | CSPR_V)
 145
 146 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 147 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 148 /* QIXIS Timing parameters for IFC CS3 */
 149 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 150                                         FTIM0_GPCM_TEADC(0x0e) | \
 151                                         FTIM0_GPCM_TEAHC(0x0e))
 152 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 153                                         FTIM1_GPCM_TRAD(0x3f))
 154 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 155                                         FTIM2_GPCM_TCH(0xf) | \
 156                                         FTIM2_GPCM_TWP(0x3E))
 157 #define CONFIG_SYS_CS3_FTIM3            0x0
 158
 159 #if defined(CONFIG_SPL)
 160 #if defined(CONFIG_NAND_BOOT)
 161 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 162 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 163 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 164 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 165 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 166 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 167 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 168 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 169 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 170 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 171 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 172 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 173 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 174 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 175 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 176 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 177 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 178 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 179 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 180 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 181 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 182 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 183 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 184 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 185 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 186 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 187 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 188
 189 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 190 #endif
 191 #else
 192 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 193 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 194 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 195 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 196 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 197 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 198 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 199 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 200 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 201 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 202 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 203 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 204 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 205 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 206 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 207 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 208 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 209 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 210 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 211 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 212 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 213 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 214 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 215 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 216 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 217 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 218 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 219 #endif
 220
 221 /* Debug Server firmware */
 222 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 223 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 224
 225 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 226
 227 /*
 228  * I2C
 229  */
 230 #define I2C_MUX_PCA_ADDR                0x77
 231 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 232
 233 /* I2C bus multiplexer */
 234 #define I2C_MUX_CH_DEFAULT      0x8
 235
 236 /* SPI */
 237
 238 /*
 239  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 240  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 241  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 242  */
 243 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 244
 245 /*
 246  * MMC
 247  */
 248 #ifdef CONFIG_MMC
 249 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 250         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 251 #endif
 252
 253 /*
 254  * RTC configuration
 255  */
 256 #define RTC
 257 #define CONFIG_RTC_DS3231               1
 258 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 259
 260 /* EEPROM */
 261 #define CONFIG_SYS_I2C_EEPROM_NXID
 262 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 263
 264 #define CONFIG_FSL_MEMAC
 265
 266 #ifdef CONFIG_PCI
 267 #define CONFIG_PCI_SCAN_SHOW
 268 #endif
 269
 270 /* Initial environment variables */
 271 #undef CONFIG_EXTRA_ENV_SETTINGS
 272 #ifdef CONFIG_NXP_ESBC
 273 #define CONFIG_EXTRA_ENV_SETTINGS               \
 274         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 275         "loadaddr=0x80100000\0"                 \
 276         "kernel_addr=0x100000\0"                \
 277         "ramdisk_addr=0x800000\0"               \
 278         "ramdisk_size=0x2000000\0"              \
 279         "fdt_high=0xa0000000\0"                 \
 280         "initrd_high=0xffffffffffffffff\0"      \
 281         "kernel_start=0x581000000\0"            \
 282         "kernel_load=0xa0000000\0"              \
 283         "kernel_size=0x2800000\0"               \
 284         "mcmemsize=0x40000000\0"                \
 285         "mcinitcmd=esbc_validate 0x580640000;"  \
 286         "esbc_validate 0x580680000;"            \
 287         "fsl_mc start mc 0x580a00000"           \
 288         " 0x580e00000 \0"
 289 #else
 290 #ifdef CONFIG_TFABOOT
 291 #define SD_MC_INIT_CMD                          \
 292         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 293         "mmc read 0x80e00000 0x7000 0x800;" \
 294         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 295 #define IFC_MC_INIT_CMD                         \
 296         "fsl_mc start mc 0x580a00000" \
 297         " 0x580e00000 \0"
 298 #define CONFIG_EXTRA_ENV_SETTINGS               \
 299         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 300         "loadaddr=0x80100000\0"                 \
 301         "loadaddr_sd=0x90100000\0"                 \
 302         "kernel_addr=0x581000000\0"                       \
 303         "kernel_addr_sd=0x8000\0"                \
 304         "ramdisk_addr=0x800000\0"               \
 305         "ramdisk_size=0x2000000\0"              \
 306         "fdt_high=0xa0000000\0"                 \
 307         "initrd_high=0xffffffffffffffff\0"      \
 308         "kernel_start=0x581000000\0"            \
 309         "kernel_start_sd=0x8000\0"              \
 310         "kernel_load=0xa0000000\0"              \
 311         "kernel_size=0x2800000\0"               \
 312         "kernel_size_sd=0x14000\0"               \
 313         "load_addr=0xa0000000\0"                            \
 314         "kernelheader_addr=0x580600000\0"       \
 315         "kernelheader_addr_r=0x80200000\0"      \
 316         "kernelheader_size=0x40000\0"           \
 317         "BOARD=ls2088aqds\0" \
 318         "mcmemsize=0x70000000 \0" \
 319         "scriptaddr=0x80000000\0"               \
 320         "scripthdraddr=0x80080000\0"            \
 321         IFC_MC_INIT_CMD                         \
 322         BOOTENV                                 \
 323         "boot_scripts=ls2088aqds_boot.scr\0"    \
 324         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
 325         "scan_dev_for_boot_part="               \
 326                 "part list ${devtype} ${devnum} devplist; "     \
 327                 "env exists devplist || setenv devplist 1; "    \
 328                 "for distro_bootpart in ${devplist}; do "       \
 329                         "if fstype ${devtype} "                 \
 330                                 "${devnum}:${distro_bootpart} " \
 331                                 "bootfstype; then "             \
 332                                 "run scan_dev_for_boot; "       \
 333                         "fi; "                                  \
 334                 "done\0"                                        \
 335         "boot_a_script="                                        \
 336                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 337                         "${scriptaddr} ${prefix}${script}; "    \
 338                 "env exists secureboot && load ${devtype} "     \
 339                         "${devnum}:${distro_bootpart} "         \
 340                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 341                         "&& esbc_validate ${scripthdraddr};"    \
 342                 "source ${scriptaddr}\0"                        \
 343         "nor_bootcmd=echo Trying load from nor..;"              \
 344                 "cp.b $kernel_addr $load_addr "                 \
 345                 "$kernel_size ; env exists secureboot && "      \
 346                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 347                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 348                 "bootm $load_addr#$BOARD\0"     \
 349         "sd_bootcmd=echo Trying load from SD ..;" \
 350         "mmcinfo; mmc read $load_addr "         \
 351         "$kernel_addr_sd $kernel_size_sd && "   \
 352         "bootm $load_addr#$BOARD\0"
 353 #elif defined(CONFIG_SD_BOOT)
 354 #define CONFIG_EXTRA_ENV_SETTINGS               \
 355         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 356         "loadaddr=0x90100000\0"                 \
 357         "kernel_addr=0x800\0"                \
 358         "ramdisk_addr=0x800000\0"               \
 359         "ramdisk_size=0x2000000\0"              \
 360         "fdt_high=0xa0000000\0"                 \
 361         "initrd_high=0xffffffffffffffff\0"      \
 362         "kernel_start=0x8000\0"              \
 363         "kernel_load=0xa0000000\0"              \
 364         "kernel_size=0x14000\0"               \
 365         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 366         "mmc read 0x80e00000 0x7000 0x800;" \
 367         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 368         "mcmemsize=0x70000000 \0"
 369 #else
 370 #define CONFIG_EXTRA_ENV_SETTINGS               \
 371         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 372         "loadaddr=0x80100000\0"                 \
 373         "kernel_addr=0x100000\0"                \
 374         "ramdisk_addr=0x800000\0"               \
 375         "ramdisk_size=0x2000000\0"              \
 376         "fdt_high=0xa0000000\0"                 \
 377         "initrd_high=0xffffffffffffffff\0"      \
 378         "kernel_start=0x581000000\0"            \
 379         "kernel_load=0xa0000000\0"              \
 380         "kernel_size=0x2800000\0"               \
 381         "mcmemsize=0x40000000\0"                \
 382         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 383         " 0x580e00000 \0"
 384 #endif /* CONFIG_TFABOOT */
 385 #endif /* CONFIG_NXP_ESBC */
 386
 387 #ifdef CONFIG_TFABOOT
 388 #define BOOT_TARGET_DEVICES(func) \
 389         func(USB, usb, 0) \
 390         func(MMC, mmc, 0) \
 391         func(SCSI, scsi, 0) \
 392         func(DHCP, dhcp, na)
 393 #include <config_distro_bootcmd.h>
 394
 395 #define SD_BOOTCOMMAND                                          \
 396                         "env exists mcinitcmd && env exists secureboot "\
 397                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 398                         "&& esbc_validate $load_addr; "                 \
 399                         "env exists mcinitcmd && run mcinitcmd "        \
 400                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 401                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 402                         "run distro_bootcmd;run sd_bootcmd; "           \
 403                         "env exists secureboot && esbc_halt;"
 404
 405 #define IFC_NOR_BOOTCOMMAND                                             \
 406                         "env exists mcinitcmd && env exists secureboot "\
 407                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 408                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 409                         "run distro_bootcmd;run nor_bootcmd; "          \
 410                         "env exists secureboot && esbc_halt;"
 411 #endif
 412
 413 #if defined(CONFIG_FSL_MC_ENET)
 414 #define CONFIG_FSL_MEMAC
 415 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 416 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 417 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 418 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 419
 420 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 421 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 422 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 423 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 424 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 425 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 426 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 427 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 428 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 429 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 430 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 431 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 432 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 433 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 434 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 435 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 436
 437 #endif
 438
 439 #include <asm/fsl_secure_boot.h>
 440
 441 #endif /* __LS2_QDS_H */