include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 #endif
  15
  16 #ifdef CONFIG_FSL_QSPI
  17 #define CONFIG_QIXIS_I2C_ACCESS
  18 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  19 #endif
  20
  21 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  22 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  23 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  24
  25 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  26 #define SPD_EEPROM_ADDRESS1     0x51
  27 #define SPD_EEPROM_ADDRESS2     0x52
  28 #define SPD_EEPROM_ADDRESS3     0x53
  29 #define SPD_EEPROM_ADDRESS4     0x54
  30 #define SPD_EEPROM_ADDRESS5     0x55
  31 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  32 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  33 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  34 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  35 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  36 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  37 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  38 #endif
  39
  40 /* SATA */
  41 #define CONFIG_SCSI_AHCI_PLAT
  42
  43 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  44 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  45
  46 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  47 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  48 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  49                                                 CONFIG_SYS_SCSI_MAX_LUN)
  50
  51 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  52 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  53 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  54
  55 #define CONFIG_SYS_NOR0_CSPR                                    \
  56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  57         CSPR_PORT_SIZE_16                                       | \
  58         CSPR_MSEL_NOR                                           | \
  59         CSPR_V)
  60 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  61         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  62         CSPR_PORT_SIZE_16                                       | \
  63         CSPR_MSEL_NOR                                           | \
  64         CSPR_V)
  65 #define CONFIG_SYS_NOR1_CSPR                                    \
  66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  67         CSPR_PORT_SIZE_16                                       | \
  68         CSPR_MSEL_NOR                                           | \
  69         CSPR_V)
  70 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  72         CSPR_PORT_SIZE_16                                       | \
  73         CSPR_MSEL_NOR                                           | \
  74         CSPR_V)
  75 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  76 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  77                                 FTIM0_NOR_TEADC(0x5) | \
  78                                 FTIM0_NOR_TEAHC(0x5))
  79 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  80                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  81                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  82 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  83                                 FTIM2_NOR_TCH(0x4) | \
  84                                 FTIM2_NOR_TWPH(0x0E) | \
  85                                 FTIM2_NOR_TWP(0x1c))
  86 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  87 #define CONFIG_SYS_IFC_CCR      0x01000000
  88
  89 #ifdef CONFIG_MTD_NOR_FLASH
  90 #define CONFIG_SYS_FLASH_QUIET_TEST
  91 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  92
  93 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
  94 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  95 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  96 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  97
  98 #define CONFIG_SYS_FLASH_EMPTY_INFO
  99 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 100                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 101 #endif
 102
 103 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 104 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 105
 106 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 107 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 108                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 109                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 110                                 | CSPR_V)
 111 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 112
 113 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 114                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 115                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 116                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 117                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 118                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 119                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 120
 121 /* ONFI NAND Flash mode0 Timing Params */
 122 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 123                                         FTIM0_NAND_TWP(0x18)   | \
 124                                         FTIM0_NAND_TWCHT(0x07) | \
 125                                         FTIM0_NAND_TWH(0x0a))
 126 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 127                                         FTIM1_NAND_TWBE(0x39)  | \
 128                                         FTIM1_NAND_TRR(0x0e)   | \
 129                                         FTIM1_NAND_TRP(0x18))
 130 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 131                                         FTIM2_NAND_TREH(0x0a) | \
 132                                         FTIM2_NAND_TWHRE(0x1e))
 133 #define CONFIG_SYS_NAND_FTIM3           0x0
 134
 135 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 136 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 137 #define CONFIG_MTD_NAND_VERIFY_WRITE
 138
 139 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 140 #define QIXIS_LBMAP_SWITCH              0x06
 141 #define QIXIS_LBMAP_MASK                0x0f
 142 #define QIXIS_LBMAP_SHIFT               0
 143 #define QIXIS_LBMAP_DFLTBANK            0x00
 144 #define QIXIS_LBMAP_ALTBANK             0x04
 145 #define QIXIS_LBMAP_NAND                0x09
 146 #define QIXIS_LBMAP_SD                  0x00
 147 #define QIXIS_LBMAP_QSPI                0x0f
 148 #define QIXIS_RST_CTL_RESET             0x31
 149 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 150 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 151 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 152 #define QIXIS_RCW_SRC_NAND              0x107
 153 #define QIXIS_RCW_SRC_SD                0x40
 154 #define QIXIS_RCW_SRC_QSPI              0x62
 155 #define QIXIS_RST_FORCE_MEM             0x01
 156
 157 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 158 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 159                                 | CSPR_PORT_SIZE_8 \
 160                                 | CSPR_MSEL_GPCM \
 161                                 | CSPR_V)
 162 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 163                                 | CSPR_PORT_SIZE_8 \
 164                                 | CSPR_MSEL_GPCM \
 165                                 | CSPR_V)
 166
 167 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 168 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 169 /* QIXIS Timing parameters for IFC CS3 */
 170 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 171                                         FTIM0_GPCM_TEADC(0x0e) | \
 172                                         FTIM0_GPCM_TEAHC(0x0e))
 173 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 174                                         FTIM1_GPCM_TRAD(0x3f))
 175 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 176                                         FTIM2_GPCM_TCH(0xf) | \
 177                                         FTIM2_GPCM_TWP(0x3E))
 178 #define CONFIG_SYS_CS3_FTIM3            0x0
 179
 180 #if defined(CONFIG_SPL)
 181 #if defined(CONFIG_NAND_BOOT)
 182 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 183 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 184 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 185 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 186 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 187 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 188 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 189 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 190 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 191 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 192 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 193 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 194 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 195 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 196 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 197 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 198 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 199 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 200 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 201 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 202 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 209
 210 #define CONFIG_SPL_PAD_TO               0x20000
 211 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
 212 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 213 #endif
 214 #else
 215 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 216 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 217 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 218 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 219 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 220 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 221 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 222 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 223 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 224 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 225 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 226 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 227 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 228 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 229 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 230 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 231 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 232 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 233 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 234 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 235 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 236 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 237 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 238 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 239 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 240 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 241 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 242 #endif
 243
 244 /* Debug Server firmware */
 245 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 246 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 247
 248 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 249
 250 /*
 251  * I2C
 252  */
 253 #define I2C_MUX_PCA_ADDR                0x77
 254 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 255
 256 /* I2C bus multiplexer */
 257 #define I2C_MUX_CH_DEFAULT      0x8
 258
 259 /* SPI */
 260 #ifdef CONFIG_FSL_DSPI
 261 #define CONFIG_SPI_FLASH_STMICRO
 262 #define CONFIG_SPI_FLASH_SST
 263 #define CONFIG_SPI_FLASH_EON
 264 #endif
 265
 266 #ifdef CONFIG_FSL_QSPI
 267 #define CONFIG_SPI_FLASH_SPANSION
 268 #endif
 269 /*
 270  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 271  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 272  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 273  */
 274 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 275
 276 /*
 277  * MMC
 278  */
 279 #ifdef CONFIG_MMC
 280 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 281         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 282 #endif
 283
 284 /*
 285  * RTC configuration
 286  */
 287 #define RTC
 288 #define CONFIG_RTC_DS3231               1
 289 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 290 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 291 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 292
 293 /* EEPROM */
 294 #define CONFIG_SYS_I2C_EEPROM_NXID
 295 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 296
 297 #define CONFIG_FSL_MEMAC
 298
 299 #ifdef CONFIG_PCI
 300 #define CONFIG_PCI_SCAN_SHOW
 301 #endif
 302
 303 /* Initial environment variables */
 304 #undef CONFIG_EXTRA_ENV_SETTINGS
 305 #ifdef CONFIG_NXP_ESBC
 306 #define CONFIG_EXTRA_ENV_SETTINGS               \
 307         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 308         "loadaddr=0x80100000\0"                 \
 309         "kernel_addr=0x100000\0"                \
 310         "ramdisk_addr=0x800000\0"               \
 311         "ramdisk_size=0x2000000\0"              \
 312         "fdt_high=0xa0000000\0"                 \
 313         "initrd_high=0xffffffffffffffff\0"      \
 314         "kernel_start=0x581000000\0"            \
 315         "kernel_load=0xa0000000\0"              \
 316         "kernel_size=0x2800000\0"               \
 317         "mcmemsize=0x40000000\0"                \
 318         "mcinitcmd=esbc_validate 0x580640000;"  \
 319         "esbc_validate 0x580680000;"            \
 320         "fsl_mc start mc 0x580a00000"           \
 321         " 0x580e00000 \0"
 322 #else
 323 #ifdef CONFIG_TFABOOT
 324 #define SD_MC_INIT_CMD                          \
 325         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 326         "mmc read 0x80e00000 0x7000 0x800;" \
 327         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 328 #define IFC_MC_INIT_CMD                         \
 329         "fsl_mc start mc 0x580a00000" \
 330         " 0x580e00000 \0"
 331 #define CONFIG_EXTRA_ENV_SETTINGS               \
 332         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 333         "loadaddr=0x80100000\0"                 \
 334         "loadaddr_sd=0x90100000\0"                 \
 335         "kernel_addr=0x581000000\0"                       \
 336         "kernel_addr_sd=0x8000\0"                \
 337         "ramdisk_addr=0x800000\0"               \
 338         "ramdisk_size=0x2000000\0"              \
 339         "fdt_high=0xa0000000\0"                 \
 340         "initrd_high=0xffffffffffffffff\0"      \
 341         "kernel_start=0x581000000\0"            \
 342         "kernel_start_sd=0x8000\0"              \
 343         "kernel_load=0xa0000000\0"              \
 344         "kernel_size=0x2800000\0"               \
 345         "kernel_size_sd=0x14000\0"               \
 346         "load_addr=0xa0000000\0"                            \
 347         "kernelheader_addr=0x580600000\0"       \
 348         "kernelheader_addr_r=0x80200000\0"      \
 349         "kernelheader_size=0x40000\0"           \
 350         "BOARD=ls2088aqds\0" \
 351         "mcmemsize=0x70000000 \0" \
 352         "scriptaddr=0x80000000\0"               \
 353         "scripthdraddr=0x80080000\0"            \
 354         IFC_MC_INIT_CMD                         \
 355         BOOTENV                                 \
 356         "boot_scripts=ls2088aqds_boot.scr\0"    \
 357         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
 358         "scan_dev_for_boot_part="               \
 359                 "part list ${devtype} ${devnum} devplist; "     \
 360                 "env exists devplist || setenv devplist 1; "    \
 361                 "for distro_bootpart in ${devplist}; do "       \
 362                         "if fstype ${devtype} "                 \
 363                                 "${devnum}:${distro_bootpart} " \
 364                                 "bootfstype; then "             \
 365                                 "run scan_dev_for_boot; "       \
 366                         "fi; "                                  \
 367                 "done\0"                                        \
 368         "boot_a_script="                                        \
 369                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 370                         "${scriptaddr} ${prefix}${script}; "    \
 371                 "env exists secureboot && load ${devtype} "     \
 372                         "${devnum}:${distro_bootpart} "         \
 373                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 374                         "&& esbc_validate ${scripthdraddr};"    \
 375                 "source ${scriptaddr}\0"                        \
 376         "nor_bootcmd=echo Trying load from nor..;"              \
 377                 "cp.b $kernel_addr $load_addr "                 \
 378                 "$kernel_size ; env exists secureboot && "      \
 379                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 380                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 381                 "bootm $load_addr#$BOARD\0"     \
 382         "sd_bootcmd=echo Trying load from SD ..;" \
 383         "mmcinfo; mmc read $load_addr "         \
 384         "$kernel_addr_sd $kernel_size_sd && "   \
 385         "bootm $load_addr#$BOARD\0"
 386 #elif defined(CONFIG_SD_BOOT)
 387 #define CONFIG_EXTRA_ENV_SETTINGS               \
 388         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 389         "loadaddr=0x90100000\0"                 \
 390         "kernel_addr=0x800\0"                \
 391         "ramdisk_addr=0x800000\0"               \
 392         "ramdisk_size=0x2000000\0"              \
 393         "fdt_high=0xa0000000\0"                 \
 394         "initrd_high=0xffffffffffffffff\0"      \
 395         "kernel_start=0x8000\0"              \
 396         "kernel_load=0xa0000000\0"              \
 397         "kernel_size=0x14000\0"               \
 398         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 399         "mmc read 0x80e00000 0x7000 0x800;" \
 400         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 401         "mcmemsize=0x70000000 \0"
 402 #else
 403 #define CONFIG_EXTRA_ENV_SETTINGS               \
 404         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 405         "loadaddr=0x80100000\0"                 \
 406         "kernel_addr=0x100000\0"                \
 407         "ramdisk_addr=0x800000\0"               \
 408         "ramdisk_size=0x2000000\0"              \
 409         "fdt_high=0xa0000000\0"                 \
 410         "initrd_high=0xffffffffffffffff\0"      \
 411         "kernel_start=0x581000000\0"            \
 412         "kernel_load=0xa0000000\0"              \
 413         "kernel_size=0x2800000\0"               \
 414         "mcmemsize=0x40000000\0"                \
 415         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 416         " 0x580e00000 \0"
 417 #endif /* CONFIG_TFABOOT */
 418 #endif /* CONFIG_NXP_ESBC */
 419
 420 #ifdef CONFIG_TFABOOT
 421 #define BOOT_TARGET_DEVICES(func) \
 422         func(USB, usb, 0) \
 423         func(MMC, mmc, 0) \
 424         func(SCSI, scsi, 0) \
 425         func(DHCP, dhcp, na)
 426 #include <config_distro_bootcmd.h>
 427
 428 #define SD_BOOTCOMMAND                                          \
 429                         "env exists mcinitcmd && env exists secureboot "\
 430                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 431                         "&& esbc_validate $load_addr; "                 \
 432                         "env exists mcinitcmd && run mcinitcmd "        \
 433                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 434                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 435                         "run distro_bootcmd;run sd_bootcmd; "           \
 436                         "env exists secureboot && esbc_halt;"
 437
 438 #define IFC_NOR_BOOTCOMMAND                                             \
 439                         "env exists mcinitcmd && env exists secureboot "\
 440                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 441                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 442                         "run distro_bootcmd;run nor_bootcmd; "          \
 443                         "env exists secureboot && esbc_halt;"
 444 #endif
 445
 446 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 447 #define CONFIG_FSL_MEMAC
 448 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 449 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 450 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 451 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 452
 453 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 454 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 455 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 456 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 457 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 458 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 459 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 460 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 461 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 462 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 463 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 464 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 465 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 466 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 467 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 468 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 469
 470 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 471
 472 #endif
 473
 474 #include <asm/fsl_secure_boot.h>
 475
 476 #endif /* __LS2_QDS_H */