include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #define CONFIG_QIXIS_I2C_ACCESS
  14 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  15 #endif
  16
  17 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  18 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  19
  20 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  21 #define SPD_EEPROM_ADDRESS1     0x51
  22 #define SPD_EEPROM_ADDRESS2     0x52
  23 #define SPD_EEPROM_ADDRESS3     0x53
  24 #define SPD_EEPROM_ADDRESS4     0x54
  25 #define SPD_EEPROM_ADDRESS5     0x55
  26 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  27 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  28 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  29 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  30 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  31 #endif
  32
  33 /* SATA */
  34
  35 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  36 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  37
  38 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  39 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  40 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  41
  42 #define CONFIG_SYS_NOR0_CSPR                                    \
  43         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  44         CSPR_PORT_SIZE_16                                       | \
  45         CSPR_MSEL_NOR                                           | \
  46         CSPR_V)
  47 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  48         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  49         CSPR_PORT_SIZE_16                                       | \
  50         CSPR_MSEL_NOR                                           | \
  51         CSPR_V)
  52 #define CONFIG_SYS_NOR1_CSPR                                    \
  53         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  54         CSPR_PORT_SIZE_16                                       | \
  55         CSPR_MSEL_NOR                                           | \
  56         CSPR_V)
  57 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  58         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  59         CSPR_PORT_SIZE_16                                       | \
  60         CSPR_MSEL_NOR                                           | \
  61         CSPR_V)
  62 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  63 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  64                                 FTIM0_NOR_TEADC(0x5) | \
  65                                 FTIM0_NOR_TEAHC(0x5))
  66 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  67                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  68                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  69 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  70                                 FTIM2_NOR_TCH(0x4) | \
  71                                 FTIM2_NOR_TWPH(0x0E) | \
  72                                 FTIM2_NOR_TWP(0x1c))
  73 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  74 #define CONFIG_SYS_IFC_CCR      0x01000000
  75
  76 #ifdef CONFIG_MTD_NOR_FLASH
  77 #define CONFIG_SYS_FLASH_QUIET_TEST
  78 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  79
  80 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  81 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  82 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  83
  84 #define CONFIG_SYS_FLASH_EMPTY_INFO
  85 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  86                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  87 #endif
  88
  89 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  90 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  91
  92 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  93 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  94                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  95                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  96                                 | CSPR_V)
  97 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  98
  99 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 100                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 101                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 102                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 103                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 104                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 105                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 106
 107 /* ONFI NAND Flash mode0 Timing Params */
 108 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 109                                         FTIM0_NAND_TWP(0x18)   | \
 110                                         FTIM0_NAND_TWCHT(0x07) | \
 111                                         FTIM0_NAND_TWH(0x0a))
 112 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 113                                         FTIM1_NAND_TWBE(0x39)  | \
 114                                         FTIM1_NAND_TRR(0x0e)   | \
 115                                         FTIM1_NAND_TRP(0x18))
 116 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 117                                         FTIM2_NAND_TREH(0x0a) | \
 118                                         FTIM2_NAND_TWHRE(0x1e))
 119 #define CONFIG_SYS_NAND_FTIM3           0x0
 120
 121 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 122 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 123 #define CONFIG_MTD_NAND_VERIFY_WRITE
 124
 125 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 126 #define QIXIS_LBMAP_SWITCH              0x06
 127 #define QIXIS_LBMAP_MASK                0x0f
 128 #define QIXIS_LBMAP_SHIFT               0
 129 #define QIXIS_LBMAP_DFLTBANK            0x00
 130 #define QIXIS_LBMAP_ALTBANK             0x04
 131 #define QIXIS_LBMAP_NAND                0x09
 132 #define QIXIS_LBMAP_SD                  0x00
 133 #define QIXIS_LBMAP_QSPI                0x0f
 134 #define QIXIS_RST_CTL_RESET             0x31
 135 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 136 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 137 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 138 #define QIXIS_RCW_SRC_NAND              0x107
 139 #define QIXIS_RCW_SRC_SD                0x40
 140 #define QIXIS_RCW_SRC_QSPI              0x62
 141 #define QIXIS_RST_FORCE_MEM             0x01
 142
 143 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 144 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 145                                 | CSPR_PORT_SIZE_8 \
 146                                 | CSPR_MSEL_GPCM \
 147                                 | CSPR_V)
 148 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 149                                 | CSPR_PORT_SIZE_8 \
 150                                 | CSPR_MSEL_GPCM \
 151                                 | CSPR_V)
 152
 153 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 154 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 155 /* QIXIS Timing parameters for IFC CS3 */
 156 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 157                                         FTIM0_GPCM_TEADC(0x0e) | \
 158                                         FTIM0_GPCM_TEAHC(0x0e))
 159 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 160                                         FTIM1_GPCM_TRAD(0x3f))
 161 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 162                                         FTIM2_GPCM_TCH(0xf) | \
 163                                         FTIM2_GPCM_TWP(0x3E))
 164 #define CONFIG_SYS_CS3_FTIM3            0x0
 165
 166 #if defined(CONFIG_SPL)
 167 #if defined(CONFIG_NAND_BOOT)
 168 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 169 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 170 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 171 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 172 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 173 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 174 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 175 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 176 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 177 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 178 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 179 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 180 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 181 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 182 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 183 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 184 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 185 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 186 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 187 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 188 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 189 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 190 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 191 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 192 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 193 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 194 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 195
 196 #define CONFIG_SPL_PAD_TO               0x20000
 197 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 198 #endif
 199 #else
 200 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 201 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 202 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 203 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 204 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 205 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 206 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 207 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 208 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 209 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 210 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 211 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 212 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 213 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 214 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 215 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 216 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 217 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 218 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 219 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 220 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 221 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 222 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 223 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 224 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 225 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 226 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 227 #endif
 228
 229 /* Debug Server firmware */
 230 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 231 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 232
 233 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 234
 235 /*
 236  * I2C
 237  */
 238 #define I2C_MUX_PCA_ADDR                0x77
 239 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 240
 241 /* I2C bus multiplexer */
 242 #define I2C_MUX_CH_DEFAULT      0x8
 243
 244 /* SPI */
 245
 246 /*
 247  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 248  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 249  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 250  */
 251 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 252
 253 /*
 254  * MMC
 255  */
 256 #ifdef CONFIG_MMC
 257 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 258         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 259 #endif
 260
 261 /*
 262  * RTC configuration
 263  */
 264 #define RTC
 265 #define CONFIG_RTC_DS3231               1
 266 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 267
 268 /* EEPROM */
 269 #define CONFIG_SYS_I2C_EEPROM_NXID
 270 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 271
 272 #define CONFIG_FSL_MEMAC
 273
 274 #ifdef CONFIG_PCI
 275 #define CONFIG_PCI_SCAN_SHOW
 276 #endif
 277
 278 /* Initial environment variables */
 279 #undef CONFIG_EXTRA_ENV_SETTINGS
 280 #ifdef CONFIG_NXP_ESBC
 281 #define CONFIG_EXTRA_ENV_SETTINGS               \
 282         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 283         "loadaddr=0x80100000\0"                 \
 284         "kernel_addr=0x100000\0"                \
 285         "ramdisk_addr=0x800000\0"               \
 286         "ramdisk_size=0x2000000\0"              \
 287         "fdt_high=0xa0000000\0"                 \
 288         "initrd_high=0xffffffffffffffff\0"      \
 289         "kernel_start=0x581000000\0"            \
 290         "kernel_load=0xa0000000\0"              \
 291         "kernel_size=0x2800000\0"               \
 292         "mcmemsize=0x40000000\0"                \
 293         "mcinitcmd=esbc_validate 0x580640000;"  \
 294         "esbc_validate 0x580680000;"            \
 295         "fsl_mc start mc 0x580a00000"           \
 296         " 0x580e00000 \0"
 297 #else
 298 #ifdef CONFIG_TFABOOT
 299 #define SD_MC_INIT_CMD                          \
 300         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 301         "mmc read 0x80e00000 0x7000 0x800;" \
 302         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 303 #define IFC_MC_INIT_CMD                         \
 304         "fsl_mc start mc 0x580a00000" \
 305         " 0x580e00000 \0"
 306 #define CONFIG_EXTRA_ENV_SETTINGS               \
 307         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 308         "loadaddr=0x80100000\0"                 \
 309         "loadaddr_sd=0x90100000\0"                 \
 310         "kernel_addr=0x581000000\0"                       \
 311         "kernel_addr_sd=0x8000\0"                \
 312         "ramdisk_addr=0x800000\0"               \
 313         "ramdisk_size=0x2000000\0"              \
 314         "fdt_high=0xa0000000\0"                 \
 315         "initrd_high=0xffffffffffffffff\0"      \
 316         "kernel_start=0x581000000\0"            \
 317         "kernel_start_sd=0x8000\0"              \
 318         "kernel_load=0xa0000000\0"              \
 319         "kernel_size=0x2800000\0"               \
 320         "kernel_size_sd=0x14000\0"               \
 321         "load_addr=0xa0000000\0"                            \
 322         "kernelheader_addr=0x580600000\0"       \
 323         "kernelheader_addr_r=0x80200000\0"      \
 324         "kernelheader_size=0x40000\0"           \
 325         "BOARD=ls2088aqds\0" \
 326         "mcmemsize=0x70000000 \0" \
 327         "scriptaddr=0x80000000\0"               \
 328         "scripthdraddr=0x80080000\0"            \
 329         IFC_MC_INIT_CMD                         \
 330         BOOTENV                                 \
 331         "boot_scripts=ls2088aqds_boot.scr\0"    \
 332         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
 333         "scan_dev_for_boot_part="               \
 334                 "part list ${devtype} ${devnum} devplist; "     \
 335                 "env exists devplist || setenv devplist 1; "    \
 336                 "for distro_bootpart in ${devplist}; do "       \
 337                         "if fstype ${devtype} "                 \
 338                                 "${devnum}:${distro_bootpart} " \
 339                                 "bootfstype; then "             \
 340                                 "run scan_dev_for_boot; "       \
 341                         "fi; "                                  \
 342                 "done\0"                                        \
 343         "boot_a_script="                                        \
 344                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 345                         "${scriptaddr} ${prefix}${script}; "    \
 346                 "env exists secureboot && load ${devtype} "     \
 347                         "${devnum}:${distro_bootpart} "         \
 348                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 349                         "&& esbc_validate ${scripthdraddr};"    \
 350                 "source ${scriptaddr}\0"                        \
 351         "nor_bootcmd=echo Trying load from nor..;"              \
 352                 "cp.b $kernel_addr $load_addr "                 \
 353                 "$kernel_size ; env exists secureboot && "      \
 354                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 355                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 356                 "bootm $load_addr#$BOARD\0"     \
 357         "sd_bootcmd=echo Trying load from SD ..;" \
 358         "mmcinfo; mmc read $load_addr "         \
 359         "$kernel_addr_sd $kernel_size_sd && "   \
 360         "bootm $load_addr#$BOARD\0"
 361 #elif defined(CONFIG_SD_BOOT)
 362 #define CONFIG_EXTRA_ENV_SETTINGS               \
 363         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 364         "loadaddr=0x90100000\0"                 \
 365         "kernel_addr=0x800\0"                \
 366         "ramdisk_addr=0x800000\0"               \
 367         "ramdisk_size=0x2000000\0"              \
 368         "fdt_high=0xa0000000\0"                 \
 369         "initrd_high=0xffffffffffffffff\0"      \
 370         "kernel_start=0x8000\0"              \
 371         "kernel_load=0xa0000000\0"              \
 372         "kernel_size=0x14000\0"               \
 373         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 374         "mmc read 0x80e00000 0x7000 0x800;" \
 375         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 376         "mcmemsize=0x70000000 \0"
 377 #else
 378 #define CONFIG_EXTRA_ENV_SETTINGS               \
 379         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 380         "loadaddr=0x80100000\0"                 \
 381         "kernel_addr=0x100000\0"                \
 382         "ramdisk_addr=0x800000\0"               \
 383         "ramdisk_size=0x2000000\0"              \
 384         "fdt_high=0xa0000000\0"                 \
 385         "initrd_high=0xffffffffffffffff\0"      \
 386         "kernel_start=0x581000000\0"            \
 387         "kernel_load=0xa0000000\0"              \
 388         "kernel_size=0x2800000\0"               \
 389         "mcmemsize=0x40000000\0"                \
 390         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 391         " 0x580e00000 \0"
 392 #endif /* CONFIG_TFABOOT */
 393 #endif /* CONFIG_NXP_ESBC */
 394
 395 #ifdef CONFIG_TFABOOT
 396 #define BOOT_TARGET_DEVICES(func) \
 397         func(USB, usb, 0) \
 398         func(MMC, mmc, 0) \
 399         func(SCSI, scsi, 0) \
 400         func(DHCP, dhcp, na)
 401 #include <config_distro_bootcmd.h>
 402
 403 #define SD_BOOTCOMMAND                                          \
 404                         "env exists mcinitcmd && env exists secureboot "\
 405                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 406                         "&& esbc_validate $load_addr; "                 \
 407                         "env exists mcinitcmd && run mcinitcmd "        \
 408                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 409                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 410                         "run distro_bootcmd;run sd_bootcmd; "           \
 411                         "env exists secureboot && esbc_halt;"
 412
 413 #define IFC_NOR_BOOTCOMMAND                                             \
 414                         "env exists mcinitcmd && env exists secureboot "\
 415                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 416                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 417                         "run distro_bootcmd;run nor_bootcmd; "          \
 418                         "env exists secureboot && esbc_halt;"
 419 #endif
 420
 421 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 422 #define CONFIG_FSL_MEMAC
 423 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 424 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 425 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 426 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 427
 428 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 429 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 430 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 431 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 432 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 433 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 434 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 435 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 436 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 437 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 438 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 439 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 440 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 441 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 442 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 443 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 444
 445 #endif
 446
 447 #include <asm/fsl_secure_boot.h>
 448
 449 #endif /* __LS2_QDS_H */