1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
16 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
17 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
20 #define SPD_EEPROM_ADDRESS1 0x51
21 #define SPD_EEPROM_ADDRESS2 0x52
22 #define SPD_EEPROM_ADDRESS3 0x53
23 #define SPD_EEPROM_ADDRESS4 0x54
24 #define SPD_EEPROM_ADDRESS5 0x55
25 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
26 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
27 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
29 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
30 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
31 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
33 #define CONFIG_SYS_NOR0_CSPR \
34 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
38 #define CONFIG_SYS_NOR0_CSPR_EARLY \
39 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
43 #define CONFIG_SYS_NOR1_CSPR \
44 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
48 #define CONFIG_SYS_NOR1_CSPR_EARLY \
49 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
53 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
54 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
55 FTIM0_NOR_TEADC(0x5) | \
57 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
58 FTIM1_NOR_TRAD_NOR(0x1a) |\
59 FTIM1_NOR_TSEQRAD_NOR(0x13))
60 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
61 FTIM2_NOR_TCH(0x4) | \
62 FTIM2_NOR_TWPH(0x0E) | \
64 #define CONFIG_SYS_NOR_FTIM3 0x04000000
65 #define CONFIG_SYS_IFC_CCR 0x01000000
67 #ifdef CONFIG_MTD_NOR_FLASH
68 #define CONFIG_SYS_FLASH_QUIET_TEST
69 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
71 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
72 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
73 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
75 #define CONFIG_SYS_FLASH_EMPTY_INFO
76 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
77 CONFIG_SYS_FLASH_BASE + 0x40000000}
80 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
81 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
83 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
84 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
85 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
86 | CSPR_MSEL_NAND /* MSEL = NAND */ \
88 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
90 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
91 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
92 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
93 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
94 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
95 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
96 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
98 /* ONFI NAND Flash mode0 Timing Params */
99 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
100 FTIM0_NAND_TWP(0x18) | \
101 FTIM0_NAND_TWCHT(0x07) | \
102 FTIM0_NAND_TWH(0x0a))
103 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
104 FTIM1_NAND_TWBE(0x39) | \
105 FTIM1_NAND_TRR(0x0e) | \
106 FTIM1_NAND_TRP(0x18))
107 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
108 FTIM2_NAND_TREH(0x0a) | \
109 FTIM2_NAND_TWHRE(0x1e))
110 #define CONFIG_SYS_NAND_FTIM3 0x0
112 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
113 #define CONFIG_SYS_MAX_NAND_DEVICE 1
114 #define CONFIG_MTD_NAND_VERIFY_WRITE
116 #define QIXIS_LBMAP_SWITCH 0x06
117 #define QIXIS_LBMAP_MASK 0x0f
118 #define QIXIS_LBMAP_SHIFT 0
119 #define QIXIS_LBMAP_DFLTBANK 0x00
120 #define QIXIS_LBMAP_ALTBANK 0x04
121 #define QIXIS_LBMAP_NAND 0x09
122 #define QIXIS_LBMAP_SD 0x00
123 #define QIXIS_LBMAP_QSPI 0x0f
124 #define QIXIS_RST_CTL_RESET 0x31
125 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
126 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
127 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
128 #define QIXIS_RCW_SRC_NAND 0x107
129 #define QIXIS_RCW_SRC_SD 0x40
130 #define QIXIS_RCW_SRC_QSPI 0x62
131 #define QIXIS_RST_FORCE_MEM 0x01
133 #define CONFIG_SYS_CSPR3_EXT (0x0)
134 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
138 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
143 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
144 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
145 /* QIXIS Timing parameters for IFC CS3 */
146 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
147 FTIM0_GPCM_TEADC(0x0e) | \
148 FTIM0_GPCM_TEAHC(0x0e))
149 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
150 FTIM1_GPCM_TRAD(0x3f))
151 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
152 FTIM2_GPCM_TCH(0xf) | \
153 FTIM2_GPCM_TWP(0x3E))
154 #define CONFIG_SYS_CS3_FTIM3 0x0
156 #if defined(CONFIG_SPL)
157 #if defined(CONFIG_NAND_BOOT)
158 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
159 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
160 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
161 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
162 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
163 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
164 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
165 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
166 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
167 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
168 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
169 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
170 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
171 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
172 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
173 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
174 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
175 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
176 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
177 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
178 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
179 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
180 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
181 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
182 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
183 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
184 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
186 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
189 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
190 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
191 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
192 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
193 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
194 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
195 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
196 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
197 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
198 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
199 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
200 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
201 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
202 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
203 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
204 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
205 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
206 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
207 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
208 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
209 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
210 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
211 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
212 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
213 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
214 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
215 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
218 /* Debug Server firmware */
219 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
220 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
222 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
227 #define I2C_MUX_PCA_ADDR 0x77
228 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
230 /* I2C bus multiplexer */
231 #define I2C_MUX_CH_DEFAULT 0x8
236 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
237 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
238 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
240 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
246 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
247 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
254 #define CONFIG_RTC_DS3231 1
255 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
258 #define CONFIG_SYS_I2C_EEPROM_NXID
259 #define CONFIG_SYS_EEPROM_BUS_NUM 0
261 #define CONFIG_FSL_MEMAC
264 #define CONFIG_PCI_SCAN_SHOW
267 /* Initial environment variables */
268 #undef CONFIG_EXTRA_ENV_SETTINGS
269 #ifdef CONFIG_NXP_ESBC
270 #define CONFIG_EXTRA_ENV_SETTINGS \
271 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
272 "loadaddr=0x80100000\0" \
273 "kernel_addr=0x100000\0" \
274 "ramdisk_addr=0x800000\0" \
275 "ramdisk_size=0x2000000\0" \
276 "fdt_high=0xa0000000\0" \
277 "initrd_high=0xffffffffffffffff\0" \
278 "kernel_start=0x581000000\0" \
279 "kernel_load=0xa0000000\0" \
280 "kernel_size=0x2800000\0" \
281 "mcmemsize=0x40000000\0" \
282 "mcinitcmd=esbc_validate 0x580640000;" \
283 "esbc_validate 0x580680000;" \
284 "fsl_mc start mc 0x580a00000" \
287 #ifdef CONFIG_TFABOOT
288 #define SD_MC_INIT_CMD \
289 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
290 "mmc read 0x80e00000 0x7000 0x800;" \
291 "fsl_mc start mc 0x80a00000 0x80e00000\0"
292 #define IFC_MC_INIT_CMD \
293 "fsl_mc start mc 0x580a00000" \
295 #define CONFIG_EXTRA_ENV_SETTINGS \
296 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
297 "loadaddr=0x80100000\0" \
298 "loadaddr_sd=0x90100000\0" \
299 "kernel_addr=0x581000000\0" \
300 "kernel_addr_sd=0x8000\0" \
301 "ramdisk_addr=0x800000\0" \
302 "ramdisk_size=0x2000000\0" \
303 "fdt_high=0xa0000000\0" \
304 "initrd_high=0xffffffffffffffff\0" \
305 "kernel_start=0x581000000\0" \
306 "kernel_start_sd=0x8000\0" \
307 "kernel_load=0xa0000000\0" \
308 "kernel_size=0x2800000\0" \
309 "kernel_size_sd=0x14000\0" \
310 "load_addr=0xa0000000\0" \
311 "kernelheader_addr=0x580600000\0" \
312 "kernelheader_addr_r=0x80200000\0" \
313 "kernelheader_size=0x40000\0" \
314 "BOARD=ls2088aqds\0" \
315 "mcmemsize=0x70000000 \0" \
316 "scriptaddr=0x80000000\0" \
317 "scripthdraddr=0x80080000\0" \
320 "boot_scripts=ls2088aqds_boot.scr\0" \
321 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
322 "scan_dev_for_boot_part=" \
323 "part list ${devtype} ${devnum} devplist; " \
324 "env exists devplist || setenv devplist 1; " \
325 "for distro_bootpart in ${devplist}; do " \
326 "if fstype ${devtype} " \
327 "${devnum}:${distro_bootpart} " \
328 "bootfstype; then " \
329 "run scan_dev_for_boot; " \
333 "load ${devtype} ${devnum}:${distro_bootpart} " \
334 "${scriptaddr} ${prefix}${script}; " \
335 "env exists secureboot && load ${devtype} " \
336 "${devnum}:${distro_bootpart} " \
337 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
338 "&& esbc_validate ${scripthdraddr};" \
339 "source ${scriptaddr}\0" \
340 "nor_bootcmd=echo Trying load from nor..;" \
341 "cp.b $kernel_addr $load_addr " \
342 "$kernel_size ; env exists secureboot && " \
343 "cp.b $kernelheader_addr $kernelheader_addr_r " \
344 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
345 "bootm $load_addr#$BOARD\0" \
346 "sd_bootcmd=echo Trying load from SD ..;" \
347 "mmcinfo; mmc read $load_addr " \
348 "$kernel_addr_sd $kernel_size_sd && " \
349 "bootm $load_addr#$BOARD\0"
350 #elif defined(CONFIG_SD_BOOT)
351 #define CONFIG_EXTRA_ENV_SETTINGS \
352 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
353 "loadaddr=0x90100000\0" \
354 "kernel_addr=0x800\0" \
355 "ramdisk_addr=0x800000\0" \
356 "ramdisk_size=0x2000000\0" \
357 "fdt_high=0xa0000000\0" \
358 "initrd_high=0xffffffffffffffff\0" \
359 "kernel_start=0x8000\0" \
360 "kernel_load=0xa0000000\0" \
361 "kernel_size=0x14000\0" \
362 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
363 "mmc read 0x80e00000 0x7000 0x800;" \
364 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
365 "mcmemsize=0x70000000 \0"
367 #define CONFIG_EXTRA_ENV_SETTINGS \
368 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
369 "loadaddr=0x80100000\0" \
370 "kernel_addr=0x100000\0" \
371 "ramdisk_addr=0x800000\0" \
372 "ramdisk_size=0x2000000\0" \
373 "fdt_high=0xa0000000\0" \
374 "initrd_high=0xffffffffffffffff\0" \
375 "kernel_start=0x581000000\0" \
376 "kernel_load=0xa0000000\0" \
377 "kernel_size=0x2800000\0" \
378 "mcmemsize=0x40000000\0" \
379 "mcinitcmd=fsl_mc start mc 0x580a00000" \
381 #endif /* CONFIG_TFABOOT */
382 #endif /* CONFIG_NXP_ESBC */
384 #ifdef CONFIG_TFABOOT
385 #define BOOT_TARGET_DEVICES(func) \
388 func(SCSI, scsi, 0) \
390 #include <config_distro_bootcmd.h>
392 #define SD_BOOTCOMMAND \
393 "env exists mcinitcmd && env exists secureboot "\
394 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
395 "&& esbc_validate $load_addr; " \
396 "env exists mcinitcmd && run mcinitcmd " \
397 "&& mmc read 0x80d00000 0x6800 0x800 " \
398 "&& fsl_mc lazyapply dpl 0x80d00000; " \
399 "run distro_bootcmd;run sd_bootcmd; " \
400 "env exists secureboot && esbc_halt;"
402 #define IFC_NOR_BOOTCOMMAND \
403 "env exists mcinitcmd && env exists secureboot "\
404 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
405 "&& fsl_mc lazyapply dpl 0x580d00000;" \
406 "run distro_bootcmd;run nor_bootcmd; " \
407 "env exists secureboot && esbc_halt;"
410 #if defined(CONFIG_FSL_MC_ENET)
411 #define CONFIG_FSL_MEMAC
412 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
413 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
414 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
415 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
417 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
418 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
419 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
420 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
421 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
422 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
423 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
424 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
425 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
426 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
427 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
428 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
429 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
430 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
431 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
432 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
436 #include <asm/fsl_secure_boot.h>
438 #endif /* __LS2_QDS_H */