1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
16 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
17 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
20 #define SPD_EEPROM_ADDRESS1 0x51
21 #define SPD_EEPROM_ADDRESS2 0x52
22 #define SPD_EEPROM_ADDRESS3 0x53
23 #define SPD_EEPROM_ADDRESS4 0x54
24 #define SPD_EEPROM_ADDRESS5 0x55
25 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
26 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
28 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
29 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
30 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
32 #define CONFIG_SYS_NOR0_CSPR \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
37 #define CONFIG_SYS_NOR0_CSPR_EARLY \
38 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
42 #define CONFIG_SYS_NOR1_CSPR \
43 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
47 #define CONFIG_SYS_NOR1_CSPR_EARLY \
48 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
52 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
53 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
54 FTIM0_NOR_TEADC(0x5) | \
56 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
57 FTIM1_NOR_TRAD_NOR(0x1a) |\
58 FTIM1_NOR_TSEQRAD_NOR(0x13))
59 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
60 FTIM2_NOR_TCH(0x4) | \
61 FTIM2_NOR_TWPH(0x0E) | \
63 #define CONFIG_SYS_NOR_FTIM3 0x04000000
64 #define CONFIG_SYS_IFC_CCR 0x01000000
66 #ifdef CONFIG_MTD_NOR_FLASH
67 #define CONFIG_SYS_FLASH_QUIET_TEST
68 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
70 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
71 CONFIG_SYS_FLASH_BASE + 0x40000000}
74 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
75 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
77 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
78 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
79 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
80 | CSPR_MSEL_NAND /* MSEL = NAND */ \
82 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
84 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
85 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
86 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
87 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
88 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
89 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
90 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
92 /* ONFI NAND Flash mode0 Timing Params */
93 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
94 FTIM0_NAND_TWP(0x18) | \
95 FTIM0_NAND_TWCHT(0x07) | \
97 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
98 FTIM1_NAND_TWBE(0x39) | \
99 FTIM1_NAND_TRR(0x0e) | \
100 FTIM1_NAND_TRP(0x18))
101 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
102 FTIM2_NAND_TREH(0x0a) | \
103 FTIM2_NAND_TWHRE(0x1e))
104 #define CONFIG_SYS_NAND_FTIM3 0x0
106 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
107 #define CONFIG_SYS_MAX_NAND_DEVICE 1
108 #define CONFIG_MTD_NAND_VERIFY_WRITE
110 #define QIXIS_LBMAP_SWITCH 0x06
111 #define QIXIS_LBMAP_MASK 0x0f
112 #define QIXIS_LBMAP_SHIFT 0
113 #define QIXIS_LBMAP_DFLTBANK 0x00
114 #define QIXIS_LBMAP_ALTBANK 0x04
115 #define QIXIS_LBMAP_NAND 0x09
116 #define QIXIS_LBMAP_SD 0x00
117 #define QIXIS_LBMAP_QSPI 0x0f
118 #define QIXIS_RST_CTL_RESET 0x31
119 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
120 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
121 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
122 #define QIXIS_RCW_SRC_NAND 0x107
123 #define QIXIS_RCW_SRC_SD 0x40
124 #define QIXIS_RCW_SRC_QSPI 0x62
125 #define QIXIS_RST_FORCE_MEM 0x01
127 #define CONFIG_SYS_CSPR3_EXT (0x0)
128 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
132 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
137 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
138 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
139 /* QIXIS Timing parameters for IFC CS3 */
140 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
141 FTIM0_GPCM_TEADC(0x0e) | \
142 FTIM0_GPCM_TEAHC(0x0e))
143 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
144 FTIM1_GPCM_TRAD(0x3f))
145 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
146 FTIM2_GPCM_TCH(0xf) | \
147 FTIM2_GPCM_TWP(0x3E))
148 #define CONFIG_SYS_CS3_FTIM3 0x0
150 #if defined(CONFIG_SPL)
151 #if defined(CONFIG_NAND_BOOT)
152 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
153 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
154 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
155 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
156 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
157 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
158 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
159 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
160 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
161 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
162 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
163 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
164 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
165 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
166 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
167 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
168 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
169 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
170 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
171 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
172 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
173 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
174 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
175 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
176 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
177 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
178 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
180 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
183 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
184 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
185 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
186 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
187 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
188 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
189 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
190 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
191 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
192 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
193 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
194 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
195 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
196 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
197 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
198 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
199 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
200 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
201 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
202 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
203 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
204 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
205 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
206 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
207 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
208 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
209 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
212 /* Debug Server firmware */
213 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
214 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
216 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
221 #define I2C_MUX_PCA_ADDR 0x77
222 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
224 /* I2C bus multiplexer */
225 #define I2C_MUX_CH_DEFAULT 0x8
230 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
231 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
232 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
234 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
240 #define CONFIG_RTC_DS3231 1
241 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
244 #define CONFIG_SYS_I2C_EEPROM_NXID
245 #define CONFIG_SYS_EEPROM_BUS_NUM 0
247 #define CONFIG_FSL_MEMAC
249 /* Initial environment variables */
250 #undef CONFIG_EXTRA_ENV_SETTINGS
251 #ifdef CONFIG_NXP_ESBC
252 #define CONFIG_EXTRA_ENV_SETTINGS \
253 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
254 "loadaddr=0x80100000\0" \
255 "kernel_addr=0x100000\0" \
256 "ramdisk_addr=0x800000\0" \
257 "ramdisk_size=0x2000000\0" \
258 "fdt_high=0xa0000000\0" \
259 "initrd_high=0xffffffffffffffff\0" \
260 "kernel_start=0x581000000\0" \
261 "kernel_load=0xa0000000\0" \
262 "kernel_size=0x2800000\0" \
263 "mcmemsize=0x40000000\0" \
264 "mcinitcmd=esbc_validate 0x580640000;" \
265 "esbc_validate 0x580680000;" \
266 "fsl_mc start mc 0x580a00000" \
269 #ifdef CONFIG_TFABOOT
270 #define SD_MC_INIT_CMD \
271 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
272 "mmc read 0x80e00000 0x7000 0x800;" \
273 "fsl_mc start mc 0x80a00000 0x80e00000\0"
274 #define IFC_MC_INIT_CMD \
275 "fsl_mc start mc 0x580a00000" \
277 #define CONFIG_EXTRA_ENV_SETTINGS \
278 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
279 "loadaddr=0x80100000\0" \
280 "loadaddr_sd=0x90100000\0" \
281 "kernel_addr=0x581000000\0" \
282 "kernel_addr_sd=0x8000\0" \
283 "ramdisk_addr=0x800000\0" \
284 "ramdisk_size=0x2000000\0" \
285 "fdt_high=0xa0000000\0" \
286 "initrd_high=0xffffffffffffffff\0" \
287 "kernel_start=0x581000000\0" \
288 "kernel_start_sd=0x8000\0" \
289 "kernel_load=0xa0000000\0" \
290 "kernel_size=0x2800000\0" \
291 "kernel_size_sd=0x14000\0" \
292 "load_addr=0xa0000000\0" \
293 "kernelheader_addr=0x580600000\0" \
294 "kernelheader_addr_r=0x80200000\0" \
295 "kernelheader_size=0x40000\0" \
296 "BOARD=ls2088aqds\0" \
297 "mcmemsize=0x70000000 \0" \
298 "scriptaddr=0x80000000\0" \
299 "scripthdraddr=0x80080000\0" \
302 "boot_scripts=ls2088aqds_boot.scr\0" \
303 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
304 "scan_dev_for_boot_part=" \
305 "part list ${devtype} ${devnum} devplist; " \
306 "env exists devplist || setenv devplist 1; " \
307 "for distro_bootpart in ${devplist}; do " \
308 "if fstype ${devtype} " \
309 "${devnum}:${distro_bootpart} " \
310 "bootfstype; then " \
311 "run scan_dev_for_boot; " \
315 "load ${devtype} ${devnum}:${distro_bootpart} " \
316 "${scriptaddr} ${prefix}${script}; " \
317 "env exists secureboot && load ${devtype} " \
318 "${devnum}:${distro_bootpart} " \
319 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
320 "&& esbc_validate ${scripthdraddr};" \
321 "source ${scriptaddr}\0" \
322 "nor_bootcmd=echo Trying load from nor..;" \
323 "cp.b $kernel_addr $load_addr " \
324 "$kernel_size ; env exists secureboot && " \
325 "cp.b $kernelheader_addr $kernelheader_addr_r " \
326 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
327 "bootm $load_addr#$BOARD\0" \
328 "sd_bootcmd=echo Trying load from SD ..;" \
329 "mmcinfo; mmc read $load_addr " \
330 "$kernel_addr_sd $kernel_size_sd && " \
331 "bootm $load_addr#$BOARD\0"
332 #elif defined(CONFIG_SD_BOOT)
333 #define CONFIG_EXTRA_ENV_SETTINGS \
334 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
335 "loadaddr=0x90100000\0" \
336 "kernel_addr=0x800\0" \
337 "ramdisk_addr=0x800000\0" \
338 "ramdisk_size=0x2000000\0" \
339 "fdt_high=0xa0000000\0" \
340 "initrd_high=0xffffffffffffffff\0" \
341 "kernel_start=0x8000\0" \
342 "kernel_load=0xa0000000\0" \
343 "kernel_size=0x14000\0" \
344 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
345 "mmc read 0x80e00000 0x7000 0x800;" \
346 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
347 "mcmemsize=0x70000000 \0"
349 #define CONFIG_EXTRA_ENV_SETTINGS \
350 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
351 "loadaddr=0x80100000\0" \
352 "kernel_addr=0x100000\0" \
353 "ramdisk_addr=0x800000\0" \
354 "ramdisk_size=0x2000000\0" \
355 "fdt_high=0xa0000000\0" \
356 "initrd_high=0xffffffffffffffff\0" \
357 "kernel_start=0x581000000\0" \
358 "kernel_load=0xa0000000\0" \
359 "kernel_size=0x2800000\0" \
360 "mcmemsize=0x40000000\0" \
361 "mcinitcmd=fsl_mc start mc 0x580a00000" \
363 #endif /* CONFIG_TFABOOT */
364 #endif /* CONFIG_NXP_ESBC */
366 #ifdef CONFIG_TFABOOT
367 #define BOOT_TARGET_DEVICES(func) \
370 func(SCSI, scsi, 0) \
372 #include <config_distro_bootcmd.h>
374 #define SD_BOOTCOMMAND \
375 "env exists mcinitcmd && env exists secureboot "\
376 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
377 "&& esbc_validate $load_addr; " \
378 "env exists mcinitcmd && run mcinitcmd " \
379 "&& mmc read 0x80d00000 0x6800 0x800 " \
380 "&& fsl_mc lazyapply dpl 0x80d00000; " \
381 "run distro_bootcmd;run sd_bootcmd; " \
382 "env exists secureboot && esbc_halt;"
384 #define IFC_NOR_BOOTCOMMAND \
385 "env exists mcinitcmd && env exists secureboot "\
386 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
387 "&& fsl_mc lazyapply dpl 0x580d00000;" \
388 "run distro_bootcmd;run nor_bootcmd; " \
389 "env exists secureboot && esbc_halt;"
392 #if defined(CONFIG_FSL_MC_ENET)
393 #define CONFIG_FSL_MEMAC
394 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
395 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
396 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
397 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
399 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
400 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
401 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
402 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
403 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
404 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
405 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
406 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
407 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
408 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
409 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
410 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
411 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
412 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
413 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
414 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
418 #include <asm/fsl_secure_boot.h>
420 #endif /* __LS2_QDS_H */