1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #define CONFIG_QIXIS_I2C_ACCESS
14 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
17 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
18 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
20 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
21 #define SPD_EEPROM_ADDRESS1 0x51
22 #define SPD_EEPROM_ADDRESS2 0x52
23 #define SPD_EEPROM_ADDRESS3 0x53
24 #define SPD_EEPROM_ADDRESS4 0x54
25 #define SPD_EEPROM_ADDRESS5 0x55
26 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
27 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
28 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
29 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
30 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
31 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
32 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
36 #define CONFIG_SCSI_AHCI_PLAT
38 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
39 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
41 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
42 #define CONFIG_SYS_SCSI_MAX_LUN 1
43 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
44 CONFIG_SYS_SCSI_MAX_LUN)
46 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
47 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
48 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
50 #define CONFIG_SYS_NOR0_CSPR \
51 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
55 #define CONFIG_SYS_NOR0_CSPR_EARLY \
56 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
60 #define CONFIG_SYS_NOR1_CSPR \
61 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
65 #define CONFIG_SYS_NOR1_CSPR_EARLY \
66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
70 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
71 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
72 FTIM0_NOR_TEADC(0x5) | \
74 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
75 FTIM1_NOR_TRAD_NOR(0x1a) |\
76 FTIM1_NOR_TSEQRAD_NOR(0x13))
77 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
78 FTIM2_NOR_TCH(0x4) | \
79 FTIM2_NOR_TWPH(0x0E) | \
81 #define CONFIG_SYS_NOR_FTIM3 0x04000000
82 #define CONFIG_SYS_IFC_CCR 0x01000000
84 #ifdef CONFIG_MTD_NOR_FLASH
85 #define CONFIG_SYS_FLASH_QUIET_TEST
86 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
88 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
89 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
90 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
91 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
93 #define CONFIG_SYS_FLASH_EMPTY_INFO
94 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
95 CONFIG_SYS_FLASH_BASE + 0x40000000}
98 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
99 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
101 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
102 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
103 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
104 | CSPR_MSEL_NAND /* MSEL = NAND */ \
106 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
108 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
109 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
110 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
111 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
112 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
113 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
114 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
116 /* ONFI NAND Flash mode0 Timing Params */
117 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
118 FTIM0_NAND_TWP(0x18) | \
119 FTIM0_NAND_TWCHT(0x07) | \
120 FTIM0_NAND_TWH(0x0a))
121 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
122 FTIM1_NAND_TWBE(0x39) | \
123 FTIM1_NAND_TRR(0x0e) | \
124 FTIM1_NAND_TRP(0x18))
125 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
126 FTIM2_NAND_TREH(0x0a) | \
127 FTIM2_NAND_TWHRE(0x1e))
128 #define CONFIG_SYS_NAND_FTIM3 0x0
130 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
131 #define CONFIG_SYS_MAX_NAND_DEVICE 1
132 #define CONFIG_MTD_NAND_VERIFY_WRITE
134 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
135 #define QIXIS_LBMAP_SWITCH 0x06
136 #define QIXIS_LBMAP_MASK 0x0f
137 #define QIXIS_LBMAP_SHIFT 0
138 #define QIXIS_LBMAP_DFLTBANK 0x00
139 #define QIXIS_LBMAP_ALTBANK 0x04
140 #define QIXIS_LBMAP_NAND 0x09
141 #define QIXIS_LBMAP_SD 0x00
142 #define QIXIS_LBMAP_QSPI 0x0f
143 #define QIXIS_RST_CTL_RESET 0x31
144 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
145 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
146 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
147 #define QIXIS_RCW_SRC_NAND 0x107
148 #define QIXIS_RCW_SRC_SD 0x40
149 #define QIXIS_RCW_SRC_QSPI 0x62
150 #define QIXIS_RST_FORCE_MEM 0x01
152 #define CONFIG_SYS_CSPR3_EXT (0x0)
153 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
157 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
162 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
163 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
164 /* QIXIS Timing parameters for IFC CS3 */
165 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
166 FTIM0_GPCM_TEADC(0x0e) | \
167 FTIM0_GPCM_TEAHC(0x0e))
168 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
169 FTIM1_GPCM_TRAD(0x3f))
170 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
171 FTIM2_GPCM_TCH(0xf) | \
172 FTIM2_GPCM_TWP(0x3E))
173 #define CONFIG_SYS_CS3_FTIM3 0x0
175 #if defined(CONFIG_SPL)
176 #if defined(CONFIG_NAND_BOOT)
177 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
178 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
179 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
180 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
181 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
182 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
183 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
184 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
185 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
186 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
187 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
188 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
189 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
190 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
196 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
197 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
198 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
199 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
200 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
201 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
202 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
203 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
205 #define CONFIG_SPL_PAD_TO 0x20000
206 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
209 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
210 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
211 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
212 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
213 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
214 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
215 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
216 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
217 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
218 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
219 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
220 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
221 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
222 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
223 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
224 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
225 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
226 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
227 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
228 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
229 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
230 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
231 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
232 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
233 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
234 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
235 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
238 /* Debug Server firmware */
239 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
240 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
242 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
247 #define I2C_MUX_PCA_ADDR 0x77
248 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
250 /* I2C bus multiplexer */
251 #define I2C_MUX_CH_DEFAULT 0x8
256 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
257 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
258 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
260 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
266 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
267 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
274 #define CONFIG_RTC_DS3231 1
275 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
278 #define CONFIG_SYS_I2C_EEPROM_NXID
279 #define CONFIG_SYS_EEPROM_BUS_NUM 0
281 #define CONFIG_FSL_MEMAC
284 #define CONFIG_PCI_SCAN_SHOW
287 /* Initial environment variables */
288 #undef CONFIG_EXTRA_ENV_SETTINGS
289 #ifdef CONFIG_NXP_ESBC
290 #define CONFIG_EXTRA_ENV_SETTINGS \
291 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
292 "loadaddr=0x80100000\0" \
293 "kernel_addr=0x100000\0" \
294 "ramdisk_addr=0x800000\0" \
295 "ramdisk_size=0x2000000\0" \
296 "fdt_high=0xa0000000\0" \
297 "initrd_high=0xffffffffffffffff\0" \
298 "kernel_start=0x581000000\0" \
299 "kernel_load=0xa0000000\0" \
300 "kernel_size=0x2800000\0" \
301 "mcmemsize=0x40000000\0" \
302 "mcinitcmd=esbc_validate 0x580640000;" \
303 "esbc_validate 0x580680000;" \
304 "fsl_mc start mc 0x580a00000" \
307 #ifdef CONFIG_TFABOOT
308 #define SD_MC_INIT_CMD \
309 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
310 "mmc read 0x80e00000 0x7000 0x800;" \
311 "fsl_mc start mc 0x80a00000 0x80e00000\0"
312 #define IFC_MC_INIT_CMD \
313 "fsl_mc start mc 0x580a00000" \
315 #define CONFIG_EXTRA_ENV_SETTINGS \
316 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
317 "loadaddr=0x80100000\0" \
318 "loadaddr_sd=0x90100000\0" \
319 "kernel_addr=0x581000000\0" \
320 "kernel_addr_sd=0x8000\0" \
321 "ramdisk_addr=0x800000\0" \
322 "ramdisk_size=0x2000000\0" \
323 "fdt_high=0xa0000000\0" \
324 "initrd_high=0xffffffffffffffff\0" \
325 "kernel_start=0x581000000\0" \
326 "kernel_start_sd=0x8000\0" \
327 "kernel_load=0xa0000000\0" \
328 "kernel_size=0x2800000\0" \
329 "kernel_size_sd=0x14000\0" \
330 "load_addr=0xa0000000\0" \
331 "kernelheader_addr=0x580600000\0" \
332 "kernelheader_addr_r=0x80200000\0" \
333 "kernelheader_size=0x40000\0" \
334 "BOARD=ls2088aqds\0" \
335 "mcmemsize=0x70000000 \0" \
336 "scriptaddr=0x80000000\0" \
337 "scripthdraddr=0x80080000\0" \
340 "boot_scripts=ls2088aqds_boot.scr\0" \
341 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
342 "scan_dev_for_boot_part=" \
343 "part list ${devtype} ${devnum} devplist; " \
344 "env exists devplist || setenv devplist 1; " \
345 "for distro_bootpart in ${devplist}; do " \
346 "if fstype ${devtype} " \
347 "${devnum}:${distro_bootpart} " \
348 "bootfstype; then " \
349 "run scan_dev_for_boot; " \
353 "load ${devtype} ${devnum}:${distro_bootpart} " \
354 "${scriptaddr} ${prefix}${script}; " \
355 "env exists secureboot && load ${devtype} " \
356 "${devnum}:${distro_bootpart} " \
357 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
358 "&& esbc_validate ${scripthdraddr};" \
359 "source ${scriptaddr}\0" \
360 "nor_bootcmd=echo Trying load from nor..;" \
361 "cp.b $kernel_addr $load_addr " \
362 "$kernel_size ; env exists secureboot && " \
363 "cp.b $kernelheader_addr $kernelheader_addr_r " \
364 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
365 "bootm $load_addr#$BOARD\0" \
366 "sd_bootcmd=echo Trying load from SD ..;" \
367 "mmcinfo; mmc read $load_addr " \
368 "$kernel_addr_sd $kernel_size_sd && " \
369 "bootm $load_addr#$BOARD\0"
370 #elif defined(CONFIG_SD_BOOT)
371 #define CONFIG_EXTRA_ENV_SETTINGS \
372 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
373 "loadaddr=0x90100000\0" \
374 "kernel_addr=0x800\0" \
375 "ramdisk_addr=0x800000\0" \
376 "ramdisk_size=0x2000000\0" \
377 "fdt_high=0xa0000000\0" \
378 "initrd_high=0xffffffffffffffff\0" \
379 "kernel_start=0x8000\0" \
380 "kernel_load=0xa0000000\0" \
381 "kernel_size=0x14000\0" \
382 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
383 "mmc read 0x80e00000 0x7000 0x800;" \
384 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
385 "mcmemsize=0x70000000 \0"
387 #define CONFIG_EXTRA_ENV_SETTINGS \
388 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
389 "loadaddr=0x80100000\0" \
390 "kernel_addr=0x100000\0" \
391 "ramdisk_addr=0x800000\0" \
392 "ramdisk_size=0x2000000\0" \
393 "fdt_high=0xa0000000\0" \
394 "initrd_high=0xffffffffffffffff\0" \
395 "kernel_start=0x581000000\0" \
396 "kernel_load=0xa0000000\0" \
397 "kernel_size=0x2800000\0" \
398 "mcmemsize=0x40000000\0" \
399 "mcinitcmd=fsl_mc start mc 0x580a00000" \
401 #endif /* CONFIG_TFABOOT */
402 #endif /* CONFIG_NXP_ESBC */
404 #ifdef CONFIG_TFABOOT
405 #define BOOT_TARGET_DEVICES(func) \
408 func(SCSI, scsi, 0) \
410 #include <config_distro_bootcmd.h>
412 #define SD_BOOTCOMMAND \
413 "env exists mcinitcmd && env exists secureboot "\
414 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
415 "&& esbc_validate $load_addr; " \
416 "env exists mcinitcmd && run mcinitcmd " \
417 "&& mmc read 0x80d00000 0x6800 0x800 " \
418 "&& fsl_mc lazyapply dpl 0x80d00000; " \
419 "run distro_bootcmd;run sd_bootcmd; " \
420 "env exists secureboot && esbc_halt;"
422 #define IFC_NOR_BOOTCOMMAND \
423 "env exists mcinitcmd && env exists secureboot "\
424 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
425 "&& fsl_mc lazyapply dpl 0x580d00000;" \
426 "run distro_bootcmd;run nor_bootcmd; " \
427 "env exists secureboot && esbc_halt;"
430 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
431 #define CONFIG_FSL_MEMAC
432 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
433 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
434 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
435 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
437 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
438 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
439 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
440 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
441 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
442 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
443 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
444 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
445 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
446 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
447 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
448 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
449 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
450 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
451 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
452 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
454 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
458 #include <asm/fsl_secure_boot.h>
460 #endif /* __LS2_QDS_H */