1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
13 unsigned long get_board_sys_clk(void);
16 #ifdef CONFIG_FSL_QSPI
17 #define CONFIG_QIXIS_I2C_ACCESS
18 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
21 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
22 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
23 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
25 #define CONFIG_DDR_SPD
26 #define CONFIG_DDR_ECC
27 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
28 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
29 #define SPD_EEPROM_ADDRESS1 0x51
30 #define SPD_EEPROM_ADDRESS2 0x52
31 #define SPD_EEPROM_ADDRESS3 0x53
32 #define SPD_EEPROM_ADDRESS4 0x54
33 #define SPD_EEPROM_ADDRESS5 0x55
34 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
35 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
36 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
37 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
38 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
39 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
40 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44 #define CONFIG_SCSI_AHCI_PLAT
46 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
47 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
49 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
50 #define CONFIG_SYS_SCSI_MAX_LUN 1
51 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
52 CONFIG_SYS_SCSI_MAX_LUN)
54 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
55 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
56 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
58 #define CONFIG_SYS_NOR0_CSPR \
59 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
63 #define CONFIG_SYS_NOR0_CSPR_EARLY \
64 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
68 #define CONFIG_SYS_NOR1_CSPR \
69 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
73 #define CONFIG_SYS_NOR1_CSPR_EARLY \
74 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
78 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
79 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
80 FTIM0_NOR_TEADC(0x5) | \
82 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
83 FTIM1_NOR_TRAD_NOR(0x1a) |\
84 FTIM1_NOR_TSEQRAD_NOR(0x13))
85 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
86 FTIM2_NOR_TCH(0x4) | \
87 FTIM2_NOR_TWPH(0x0E) | \
89 #define CONFIG_SYS_NOR_FTIM3 0x04000000
90 #define CONFIG_SYS_IFC_CCR 0x01000000
92 #ifdef CONFIG_MTD_NOR_FLASH
93 #define CONFIG_SYS_FLASH_QUIET_TEST
94 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
96 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
97 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
98 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
99 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
101 #define CONFIG_SYS_FLASH_EMPTY_INFO
102 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
103 CONFIG_SYS_FLASH_BASE + 0x40000000}
106 #define CONFIG_NAND_FSL_IFC
107 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
108 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
110 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
111 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
112 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
113 | CSPR_MSEL_NAND /* MSEL = NAND */ \
115 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
117 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
118 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
119 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
120 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
121 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
122 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
123 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
125 #define CONFIG_SYS_NAND_ONFI_DETECTION
127 /* ONFI NAND Flash mode0 Timing Params */
128 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
129 FTIM0_NAND_TWP(0x18) | \
130 FTIM0_NAND_TWCHT(0x07) | \
131 FTIM0_NAND_TWH(0x0a))
132 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
133 FTIM1_NAND_TWBE(0x39) | \
134 FTIM1_NAND_TRR(0x0e) | \
135 FTIM1_NAND_TRP(0x18))
136 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
137 FTIM2_NAND_TREH(0x0a) | \
138 FTIM2_NAND_TWHRE(0x1e))
139 #define CONFIG_SYS_NAND_FTIM3 0x0
141 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
142 #define CONFIG_SYS_MAX_NAND_DEVICE 1
143 #define CONFIG_MTD_NAND_VERIFY_WRITE
145 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
147 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
148 #define QIXIS_LBMAP_SWITCH 0x06
149 #define QIXIS_LBMAP_MASK 0x0f
150 #define QIXIS_LBMAP_SHIFT 0
151 #define QIXIS_LBMAP_DFLTBANK 0x00
152 #define QIXIS_LBMAP_ALTBANK 0x04
153 #define QIXIS_LBMAP_NAND 0x09
154 #define QIXIS_LBMAP_SD 0x00
155 #define QIXIS_LBMAP_QSPI 0x0f
156 #define QIXIS_RST_CTL_RESET 0x31
157 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
158 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
159 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
160 #define QIXIS_RCW_SRC_NAND 0x107
161 #define QIXIS_RCW_SRC_SD 0x40
162 #define QIXIS_RCW_SRC_QSPI 0x62
163 #define QIXIS_RST_FORCE_MEM 0x01
165 #define CONFIG_SYS_CSPR3_EXT (0x0)
166 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
170 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
175 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
176 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
177 /* QIXIS Timing parameters for IFC CS3 */
178 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
179 FTIM0_GPCM_TEADC(0x0e) | \
180 FTIM0_GPCM_TEAHC(0x0e))
181 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
182 FTIM1_GPCM_TRAD(0x3f))
183 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
184 FTIM2_GPCM_TCH(0xf) | \
185 FTIM2_GPCM_TWP(0x3E))
186 #define CONFIG_SYS_CS3_FTIM3 0x0
188 #if defined(CONFIG_SPL)
189 #if defined(CONFIG_NAND_BOOT)
190 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
191 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
192 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
193 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
194 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
195 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
196 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
197 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
198 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
199 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
200 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
201 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
202 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
203 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
204 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
205 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
206 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
207 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
208 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
209 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
210 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
211 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
212 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
213 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
214 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
215 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
216 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
218 #define CONFIG_SPL_PAD_TO 0x20000
219 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
220 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
223 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
224 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
225 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
226 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
227 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
228 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
229 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
230 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
231 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
232 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
233 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
234 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
235 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
236 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
237 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
238 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
239 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
240 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
241 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
242 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
243 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
244 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
245 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
246 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
247 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
248 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
249 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
252 /* Debug Server firmware */
253 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
254 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
256 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
261 #define I2C_MUX_PCA_ADDR 0x77
262 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
264 /* I2C bus multiplexer */
265 #define I2C_MUX_CH_DEFAULT 0x8
268 #ifdef CONFIG_FSL_DSPI
269 #define CONFIG_SPI_FLASH_STMICRO
270 #define CONFIG_SPI_FLASH_SST
271 #define CONFIG_SPI_FLASH_EON
274 #ifdef CONFIG_FSL_QSPI
275 #define CONFIG_SPI_FLASH_SPANSION
278 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
279 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
280 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
282 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
288 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
289 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
296 #define CONFIG_RTC_DS3231 1
297 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
298 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
299 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
302 #define CONFIG_SYS_I2C_EEPROM_NXID
303 #define CONFIG_SYS_EEPROM_BUS_NUM 0
305 #define CONFIG_FSL_MEMAC
308 #define CONFIG_PCI_SCAN_SHOW
311 /* Initial environment variables */
312 #undef CONFIG_EXTRA_ENV_SETTINGS
313 #ifdef CONFIG_NXP_ESBC
314 #define CONFIG_EXTRA_ENV_SETTINGS \
315 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
316 "loadaddr=0x80100000\0" \
317 "kernel_addr=0x100000\0" \
318 "ramdisk_addr=0x800000\0" \
319 "ramdisk_size=0x2000000\0" \
320 "fdt_high=0xa0000000\0" \
321 "initrd_high=0xffffffffffffffff\0" \
322 "kernel_start=0x581000000\0" \
323 "kernel_load=0xa0000000\0" \
324 "kernel_size=0x2800000\0" \
325 "mcmemsize=0x40000000\0" \
326 "mcinitcmd=esbc_validate 0x580640000;" \
327 "esbc_validate 0x580680000;" \
328 "fsl_mc start mc 0x580a00000" \
331 #ifdef CONFIG_TFABOOT
332 #define SD_MC_INIT_CMD \
333 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
334 "mmc read 0x80e00000 0x7000 0x800;" \
335 "fsl_mc start mc 0x80a00000 0x80e00000\0"
336 #define IFC_MC_INIT_CMD \
337 "fsl_mc start mc 0x580a00000" \
339 #define CONFIG_EXTRA_ENV_SETTINGS \
340 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
341 "loadaddr=0x80100000\0" \
342 "loadaddr_sd=0x90100000\0" \
343 "kernel_addr=0x581000000\0" \
344 "kernel_addr_sd=0x8000\0" \
345 "ramdisk_addr=0x800000\0" \
346 "ramdisk_size=0x2000000\0" \
347 "fdt_high=0xa0000000\0" \
348 "initrd_high=0xffffffffffffffff\0" \
349 "kernel_start=0x581000000\0" \
350 "kernel_start_sd=0x8000\0" \
351 "kernel_load=0xa0000000\0" \
352 "kernel_size=0x2800000\0" \
353 "kernel_size_sd=0x14000\0" \
354 "load_addr=0xa0000000\0" \
355 "kernelheader_addr=0x580600000\0" \
356 "kernelheader_addr_r=0x80200000\0" \
357 "kernelheader_size=0x40000\0" \
358 "BOARD=ls2088aqds\0" \
359 "mcmemsize=0x70000000 \0" \
360 "scriptaddr=0x80000000\0" \
361 "scripthdraddr=0x80080000\0" \
364 "boot_scripts=ls2088aqds_boot.scr\0" \
365 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
366 "scan_dev_for_boot_part=" \
367 "part list ${devtype} ${devnum} devplist; " \
368 "env exists devplist || setenv devplist 1; " \
369 "for distro_bootpart in ${devplist}; do " \
370 "if fstype ${devtype} " \
371 "${devnum}:${distro_bootpart} " \
372 "bootfstype; then " \
373 "run scan_dev_for_boot; " \
377 "load ${devtype} ${devnum}:${distro_bootpart} " \
378 "${scriptaddr} ${prefix}${script}; " \
379 "env exists secureboot && load ${devtype} " \
380 "${devnum}:${distro_bootpart} " \
381 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
382 "&& esbc_validate ${scripthdraddr};" \
383 "source ${scriptaddr}\0" \
384 "nor_bootcmd=echo Trying load from nor..;" \
385 "cp.b $kernel_addr $load_addr " \
386 "$kernel_size ; env exists secureboot && " \
387 "cp.b $kernelheader_addr $kernelheader_addr_r " \
388 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
389 "bootm $load_addr#$BOARD\0" \
390 "sd_bootcmd=echo Trying load from SD ..;" \
391 "mmcinfo; mmc read $load_addr " \
392 "$kernel_addr_sd $kernel_size_sd && " \
393 "bootm $load_addr#$BOARD\0"
394 #elif defined(CONFIG_SD_BOOT)
395 #define CONFIG_EXTRA_ENV_SETTINGS \
396 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
397 "loadaddr=0x90100000\0" \
398 "kernel_addr=0x800\0" \
399 "ramdisk_addr=0x800000\0" \
400 "ramdisk_size=0x2000000\0" \
401 "fdt_high=0xa0000000\0" \
402 "initrd_high=0xffffffffffffffff\0" \
403 "kernel_start=0x8000\0" \
404 "kernel_load=0xa0000000\0" \
405 "kernel_size=0x14000\0" \
406 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
407 "mmc read 0x80e00000 0x7000 0x800;" \
408 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
409 "mcmemsize=0x70000000 \0"
411 #define CONFIG_EXTRA_ENV_SETTINGS \
412 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
413 "loadaddr=0x80100000\0" \
414 "kernel_addr=0x100000\0" \
415 "ramdisk_addr=0x800000\0" \
416 "ramdisk_size=0x2000000\0" \
417 "fdt_high=0xa0000000\0" \
418 "initrd_high=0xffffffffffffffff\0" \
419 "kernel_start=0x581000000\0" \
420 "kernel_load=0xa0000000\0" \
421 "kernel_size=0x2800000\0" \
422 "mcmemsize=0x40000000\0" \
423 "mcinitcmd=fsl_mc start mc 0x580a00000" \
425 #endif /* CONFIG_TFABOOT */
426 #endif /* CONFIG_NXP_ESBC */
428 #ifdef CONFIG_TFABOOT
429 #define BOOT_TARGET_DEVICES(func) \
432 func(SCSI, scsi, 0) \
434 #include <config_distro_bootcmd.h>
436 #define SD_BOOTCOMMAND \
437 "env exists mcinitcmd && env exists secureboot "\
438 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
439 "&& esbc_validate $load_addr; " \
440 "env exists mcinitcmd && run mcinitcmd " \
441 "&& mmc read 0x80d00000 0x6800 0x800 " \
442 "&& fsl_mc lazyapply dpl 0x80d00000; " \
443 "run distro_bootcmd;run sd_bootcmd; " \
444 "env exists secureboot && esbc_halt;"
446 #define IFC_NOR_BOOTCOMMAND \
447 "env exists mcinitcmd && env exists secureboot "\
448 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
449 "&& fsl_mc lazyapply dpl 0x580d00000;" \
450 "run distro_bootcmd;run nor_bootcmd; " \
451 "env exists secureboot && esbc_halt;"
454 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
455 #define CONFIG_FSL_MEMAC
456 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
457 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
458 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
459 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
461 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
462 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
463 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
464 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
465 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
466 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
467 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
468 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
469 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
470 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
471 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
472 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
473 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
474 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
475 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
476 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
478 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
482 #include <asm/fsl_secure_boot.h>
484 #endif /* __LS2_QDS_H */