include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 unsigned long get_board_ddr_clk(void);
  15 #endif
  16
  17 #ifdef CONFIG_FSL_QSPI
  18 #define CONFIG_QIXIS_I2C_ACCESS
  19 #ifndef CONFIG_DM_I2C
  20 #define CONFIG_SYS_I2C_EARLY_INIT
  21 #endif
  22 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
  23 #endif
  24
  25 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
  26 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  27 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  28 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  29
  30 #define CONFIG_DDR_SPD
  31 #define CONFIG_DDR_ECC
  32 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  33 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  34 #define SPD_EEPROM_ADDRESS1     0x51
  35 #define SPD_EEPROM_ADDRESS2     0x52
  36 #define SPD_EEPROM_ADDRESS3     0x53
  37 #define SPD_EEPROM_ADDRESS4     0x54
  38 #define SPD_EEPROM_ADDRESS5     0x55
  39 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  40 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  41 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  42 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  43 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  44 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  45 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  46 #endif
  47
  48 /* SATA */
  49 #define CONFIG_SCSI_AHCI_PLAT
  50
  51 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  52 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  53
  54 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  55 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  56 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  57                                                 CONFIG_SYS_SCSI_MAX_LUN)
  58
  59 #ifdef CONFIG_TFABOOT
  60 #define CONFIG_SYS_MMC_ENV_DEV          0
  61 #define CONFIG_ENV_SIZE                 0x20000
  62 #define CONFIG_ENV_OFFSET               0x500000
  63 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
  64                                          CONFIG_ENV_OFFSET)
  65 #define CONFIG_ENV_SECT_SIZE            0x20000
  66 #endif
  67
  68 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  69 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  70 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  71
  72 #define CONFIG_SYS_NOR0_CSPR                                    \
  73         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  74         CSPR_PORT_SIZE_16                                       | \
  75         CSPR_MSEL_NOR                                           | \
  76         CSPR_V)
  77 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  78         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  79         CSPR_PORT_SIZE_16                                       | \
  80         CSPR_MSEL_NOR                                           | \
  81         CSPR_V)
  82 #define CONFIG_SYS_NOR1_CSPR                                    \
  83         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  84         CSPR_PORT_SIZE_16                                       | \
  85         CSPR_MSEL_NOR                                           | \
  86         CSPR_V)
  87 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  88         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  89         CSPR_PORT_SIZE_16                                       | \
  90         CSPR_MSEL_NOR                                           | \
  91         CSPR_V)
  92 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  93 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  94                                 FTIM0_NOR_TEADC(0x5) | \
  95                                 FTIM0_NOR_TEAHC(0x5))
  96 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  97                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  98                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  99 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 100                                 FTIM2_NOR_TCH(0x4) | \
 101                                 FTIM2_NOR_TWPH(0x0E) | \
 102                                 FTIM2_NOR_TWP(0x1c))
 103 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 104 #define CONFIG_SYS_IFC_CCR      0x01000000
 105
 106 #ifdef CONFIG_MTD_NOR_FLASH
 107 #define CONFIG_SYS_FLASH_QUIET_TEST
 108 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 109
 110 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 111 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 112 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 113 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 114
 115 #define CONFIG_SYS_FLASH_EMPTY_INFO
 116 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 117                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 118 #endif
 119
 120 #define CONFIG_NAND_FSL_IFC
 121 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 122 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 123
 124 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 125 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 126                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 127                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 128                                 | CSPR_V)
 129 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 130
 131 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 132                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 133                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 134                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 135                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 136                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 137                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 138
 139 #define CONFIG_SYS_NAND_ONFI_DETECTION
 140
 141 /* ONFI NAND Flash mode0 Timing Params */
 142 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 143                                         FTIM0_NAND_TWP(0x18)   | \
 144                                         FTIM0_NAND_TWCHT(0x07) | \
 145                                         FTIM0_NAND_TWH(0x0a))
 146 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 147                                         FTIM1_NAND_TWBE(0x39)  | \
 148                                         FTIM1_NAND_TRR(0x0e)   | \
 149                                         FTIM1_NAND_TRP(0x18))
 150 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 151                                         FTIM2_NAND_TREH(0x0a) | \
 152                                         FTIM2_NAND_TWHRE(0x1e))
 153 #define CONFIG_SYS_NAND_FTIM3           0x0
 154
 155 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 156 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 157 #define CONFIG_MTD_NAND_VERIFY_WRITE
 158
 159 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 160
 161 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 162 #define QIXIS_LBMAP_SWITCH              0x06
 163 #define QIXIS_LBMAP_MASK                0x0f
 164 #define QIXIS_LBMAP_SHIFT               0
 165 #define QIXIS_LBMAP_DFLTBANK            0x00
 166 #define QIXIS_LBMAP_ALTBANK             0x04
 167 #define QIXIS_LBMAP_NAND                0x09
 168 #define QIXIS_LBMAP_SD                  0x00
 169 #define QIXIS_LBMAP_QSPI                0x0f
 170 #define QIXIS_RST_CTL_RESET             0x31
 171 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 172 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 173 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 174 #define QIXIS_RCW_SRC_NAND              0x107
 175 #define QIXIS_RCW_SRC_SD                0x40
 176 #define QIXIS_RCW_SRC_QSPI              0x62
 177 #define QIXIS_RST_FORCE_MEM             0x01
 178
 179 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 180 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 181                                 | CSPR_PORT_SIZE_8 \
 182                                 | CSPR_MSEL_GPCM \
 183                                 | CSPR_V)
 184 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 185                                 | CSPR_PORT_SIZE_8 \
 186                                 | CSPR_MSEL_GPCM \
 187                                 | CSPR_V)
 188
 189 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 190 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 191 /* QIXIS Timing parameters for IFC CS3 */
 192 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 193                                         FTIM0_GPCM_TEADC(0x0e) | \
 194                                         FTIM0_GPCM_TEAHC(0x0e))
 195 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 196                                         FTIM1_GPCM_TRAD(0x3f))
 197 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 198                                         FTIM2_GPCM_TCH(0xf) | \
 199                                         FTIM2_GPCM_TWP(0x3E))
 200 #define CONFIG_SYS_CS3_FTIM3            0x0
 201
 202 #if defined(CONFIG_SPL)
 203 #if defined(CONFIG_NAND_BOOT)
 204 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 205 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
 206 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
 207 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 208 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 209 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 210 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 211 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 212 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 213 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 214 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
 215 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
 216 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
 217 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
 218 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 219 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 220 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 221 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 222 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 223 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 224 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 225 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 226 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 227 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 228 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 229 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 230 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 231
 232 #define CONFIG_ENV_OFFSET               (896 * 1024)
 233 #define CONFIG_ENV_SECT_SIZE            0x20000
 234 #define CONFIG_ENV_SIZE                 0x2000
 235 #define CONFIG_SPL_PAD_TO               0x20000
 236 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
 237 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
 238 #elif defined(CONFIG_SD_BOOT)
 239 #define CONFIG_ENV_OFFSET               0x300000
 240 #define CONFIG_SYS_MMC_ENV_DEV          0
 241 #define CONFIG_ENV_SIZE                 0x20000
 242 #endif
 243 #else
 244 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 245 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 246 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 247 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 248 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 249 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 250 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 251 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 252 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 253 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 254 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 255 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 256 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 257 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 258 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 259 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 260 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 261 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 262 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 263 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 264 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 265 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 266 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 267 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 268 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 269 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 270 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 271
 272 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT)
 273 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 274 #define CONFIG_ENV_SECT_SIZE            0x20000
 275 #define CONFIG_ENV_SIZE                 0x2000
 276 #endif
 277 #endif
 278
 279 /* Debug Server firmware */
 280 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 281 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 282
 283 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 284
 285 /*
 286  * I2C
 287  */
 288 #define I2C_MUX_PCA_ADDR                0x77
 289 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 290
 291 /* I2C bus multiplexer */
 292 #define I2C_MUX_CH_DEFAULT      0x8
 293
 294 /* SPI */
 295 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
 296 #ifdef CONFIG_FSL_DSPI
 297 #define CONFIG_SPI_FLASH_STMICRO
 298 #define CONFIG_SPI_FLASH_SST
 299 #define CONFIG_SPI_FLASH_EON
 300 #endif
 301
 302 #ifdef CONFIG_FSL_QSPI
 303 #define CONFIG_SPI_FLASH_SPANSION
 304 #define FSL_QSPI_FLASH_SIZE             (1 << 26) /* 64MB */
 305 #define FSL_QSPI_FLASH_NUM              4
 306 #endif
 307 /*
 308  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 309  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 310  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 311  */
 312 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 313
 314 #endif
 315
 316 /*
 317  * MMC
 318  */
 319 #ifdef CONFIG_MMC
 320 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 321         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 322 #endif
 323
 324 /*
 325  * RTC configuration
 326  */
 327 #define RTC
 328 #define CONFIG_RTC_DS3231               1
 329 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 330 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 331 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
 332
 333 /* EEPROM */
 334 #define CONFIG_ID_EEPROM
 335 #define CONFIG_SYS_I2C_EEPROM_NXID
 336 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 338 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 339 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 340 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 341
 342 #define CONFIG_FSL_MEMAC
 343
 344 #ifdef CONFIG_PCI
 345 #define CONFIG_PCI_SCAN_SHOW
 346 #endif
 347
 348 /*  MMC  */
 349 #ifdef CONFIG_MMC
 350 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 351 #endif
 352
 353 /* Initial environment variables */
 354 #undef CONFIG_EXTRA_ENV_SETTINGS
 355 #ifdef CONFIG_SECURE_BOOT
 356 #define CONFIG_EXTRA_ENV_SETTINGS               \
 357         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 358         "loadaddr=0x80100000\0"                 \
 359         "kernel_addr=0x100000\0"                \
 360         "ramdisk_addr=0x800000\0"               \
 361         "ramdisk_size=0x2000000\0"              \
 362         "fdt_high=0xa0000000\0"                 \
 363         "initrd_high=0xffffffffffffffff\0"      \
 364         "kernel_start=0x581000000\0"            \
 365         "kernel_load=0xa0000000\0"              \
 366         "kernel_size=0x2800000\0"               \
 367         "mcmemsize=0x40000000\0"                \
 368         "mcinitcmd=esbc_validate 0x580700000;"  \
 369         "esbc_validate 0x580740000;"            \
 370         "fsl_mc start mc 0x580a00000"           \
 371         " 0x580e00000 \0"
 372 #else
 373 #ifdef CONFIG_TFABOOT
 374 #define SD_MC_INIT_CMD                          \
 375         "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;"  \
 376         "mmc read 0x80e00000 0x7000 0x800;" \
 377         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 378 #define IFC_MC_INIT_CMD                         \
 379         "fsl_mc start mc 0x580a00000" \
 380         " 0x580e00000 \0"
 381 #define CONFIG_EXTRA_ENV_SETTINGS               \
 382         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 383         "loadaddr=0x80100000\0"                 \
 384         "loadaddr_sd=0x90100000\0"                 \
 385         "kernel_addr=0x581000000\0"                       \
 386         "kernel_addr_sd=0x8000\0"                \
 387         "ramdisk_addr=0x800000\0"               \
 388         "ramdisk_size=0x2000000\0"              \
 389         "fdt_high=0xa0000000\0"                 \
 390         "initrd_high=0xffffffffffffffff\0"      \
 391         "kernel_start=0x581000000\0"            \
 392         "kernel_start_sd=0x8000\0"              \
 393         "kernel_load=0xa0000000\0"              \
 394         "kernel_size=0x2800000\0"               \
 395         "kernel_size_sd=0x14000\0"               \
 396         "load_addr=0xa0000000\0"                            \
 397         "kernelheader_addr=0x580800000\0"       \
 398         "kernelheader_addr_r=0x80200000\0"      \
 399         "kernelheader_size=0x40000\0"           \
 400         "BOARD=ls2088aqds\0" \
 401         "mcmemsize=0x70000000 \0" \
 402         IFC_MC_INIT_CMD                         \
 403         "nor_bootcmd=echo Trying load from nor..;"              \
 404                 "cp.b $kernel_addr $load_addr "                 \
 405                 "$kernel_size ; env exists secureboot && "      \
 406                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 407                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 408                 "bootm $load_addr#$BOARD\0"     \
 409         "sd_bootcmd=echo Trying load from SD ..;" \
 410         "mmcinfo; mmc read $load_addr "         \
 411         "$kernel_addr_sd $kernel_size_sd && "   \
 412         "bootm $load_addr#$BOARD\0"
 413 #elif defined(CONFIG_SD_BOOT)
 414 #define CONFIG_EXTRA_ENV_SETTINGS               \
 415         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 416         "loadaddr=0x90100000\0"                 \
 417         "kernel_addr=0x800\0"                \
 418         "ramdisk_addr=0x800000\0"               \
 419         "ramdisk_size=0x2000000\0"              \
 420         "fdt_high=0xa0000000\0"                 \
 421         "initrd_high=0xffffffffffffffff\0"      \
 422         "kernel_start=0x8000\0"              \
 423         "kernel_load=0xa0000000\0"              \
 424         "kernel_size=0x14000\0"               \
 425         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
 426         "mmc read 0x80100000 0x7000 0x800;" \
 427         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 428         "mcmemsize=0x70000000 \0"
 429 #else
 430 #define CONFIG_EXTRA_ENV_SETTINGS               \
 431         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 432         "loadaddr=0x80100000\0"                 \
 433         "kernel_addr=0x100000\0"                \
 434         "ramdisk_addr=0x800000\0"               \
 435         "ramdisk_size=0x2000000\0"              \
 436         "fdt_high=0xa0000000\0"                 \
 437         "initrd_high=0xffffffffffffffff\0"      \
 438         "kernel_start=0x581000000\0"            \
 439         "kernel_load=0xa0000000\0"              \
 440         "kernel_size=0x2800000\0"               \
 441         "mcmemsize=0x40000000\0"                \
 442         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 443         " 0x580e00000 \0"
 444 #endif /* CONFIG_TFABOOT */
 445 #endif /* CONFIG_SECURE_BOOT */
 446
 447 #ifdef CONFIG_TFABOOT
 448 #define SD_BOOTCOMMAND                                          \
 449                         "env exists mcinitcmd && env exists secureboot "\
 450                         "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
 451                         "&& esbc_validate $load_addr; "                 \
 452                         "env exists mcinitcmd && run mcinitcmd "        \
 453                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 454                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 455                         "run sd_bootcmd; "              \
 456                         "env exists secureboot && esbc_halt;"
 457
 458 #define IFC_NOR_BOOTCOMMAND                                             \
 459                         "env exists mcinitcmd && env exists secureboot "\
 460                         "&& esbc_validate 0x580780000; env exists mcinitcmd "\
 461                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 462                         "run nor_bootcmd; "             \
 463                         "env exists secureboot && esbc_halt;"
 464 #endif
 465
 466 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 467 #define CONFIG_FSL_MEMAC
 468 #define CONFIG_PHYLIB_10G
 469 #define CONFIG_PHY_VITESSE
 470 #define CONFIG_PHY_REALTEK
 471 #define CONFIG_PHY_TERANETICS
 472 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 473 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 474 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 475 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 476
 477 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 478 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 479 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 480 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 481 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 482 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 483 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 484 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 485 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 486 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 487 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 488 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 489 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 490 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 491 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 492 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 493
 494 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 495
 496 #endif
 497
 498 #include <asm/fsl_secure_boot.h>
 499
 500 #endif /* __LS2_QDS_H */