1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void);
17 #ifdef CONFIG_FSL_QSPI
18 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_I2C_IFDR_DIV 0x7e
22 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
23 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
24 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
25 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
27 #define CONFIG_DDR_SPD
28 #define CONFIG_DDR_ECC
29 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
30 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
31 #define SPD_EEPROM_ADDRESS1 0x51
32 #define SPD_EEPROM_ADDRESS2 0x52
33 #define SPD_EEPROM_ADDRESS3 0x53
34 #define SPD_EEPROM_ADDRESS4 0x54
35 #define SPD_EEPROM_ADDRESS5 0x55
36 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
37 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
38 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
39 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
40 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
41 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
42 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
46 #define CONFIG_SCSI_AHCI_PLAT
48 #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
49 #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
51 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
52 #define CONFIG_SYS_SCSI_MAX_LUN 1
53 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
54 CONFIG_SYS_SCSI_MAX_LUN)
56 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
57 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
58 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
60 #define CONFIG_SYS_NOR0_CSPR \
61 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
65 #define CONFIG_SYS_NOR0_CSPR_EARLY \
66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
70 #define CONFIG_SYS_NOR1_CSPR \
71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
75 #define CONFIG_SYS_NOR1_CSPR_EARLY \
76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
80 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
81 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
82 FTIM0_NOR_TEADC(0x5) | \
84 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
85 FTIM1_NOR_TRAD_NOR(0x1a) |\
86 FTIM1_NOR_TSEQRAD_NOR(0x13))
87 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
88 FTIM2_NOR_TCH(0x4) | \
89 FTIM2_NOR_TWPH(0x0E) | \
91 #define CONFIG_SYS_NOR_FTIM3 0x04000000
92 #define CONFIG_SYS_IFC_CCR 0x01000000
94 #ifdef CONFIG_MTD_NOR_FLASH
95 #define CONFIG_SYS_FLASH_QUIET_TEST
96 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
98 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
99 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
100 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
101 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
103 #define CONFIG_SYS_FLASH_EMPTY_INFO
104 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
105 CONFIG_SYS_FLASH_BASE + 0x40000000}
108 #define CONFIG_NAND_FSL_IFC
109 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
110 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
112 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
113 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
114 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
115 | CSPR_MSEL_NAND /* MSEL = NAND */ \
117 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
119 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
120 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
121 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
122 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
123 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
124 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
125 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
127 #define CONFIG_SYS_NAND_ONFI_DETECTION
129 /* ONFI NAND Flash mode0 Timing Params */
130 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
131 FTIM0_NAND_TWP(0x18) | \
132 FTIM0_NAND_TWCHT(0x07) | \
133 FTIM0_NAND_TWH(0x0a))
134 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
135 FTIM1_NAND_TWBE(0x39) | \
136 FTIM1_NAND_TRR(0x0e) | \
137 FTIM1_NAND_TRP(0x18))
138 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
139 FTIM2_NAND_TREH(0x0a) | \
140 FTIM2_NAND_TWHRE(0x1e))
141 #define CONFIG_SYS_NAND_FTIM3 0x0
143 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
144 #define CONFIG_SYS_MAX_NAND_DEVICE 1
145 #define CONFIG_MTD_NAND_VERIFY_WRITE
147 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
149 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
150 #define QIXIS_LBMAP_SWITCH 0x06
151 #define QIXIS_LBMAP_MASK 0x0f
152 #define QIXIS_LBMAP_SHIFT 0
153 #define QIXIS_LBMAP_DFLTBANK 0x00
154 #define QIXIS_LBMAP_ALTBANK 0x04
155 #define QIXIS_LBMAP_NAND 0x09
156 #define QIXIS_LBMAP_SD 0x00
157 #define QIXIS_LBMAP_QSPI 0x0f
158 #define QIXIS_RST_CTL_RESET 0x31
159 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
160 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
161 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
162 #define QIXIS_RCW_SRC_NAND 0x107
163 #define QIXIS_RCW_SRC_SD 0x40
164 #define QIXIS_RCW_SRC_QSPI 0x62
165 #define QIXIS_RST_FORCE_MEM 0x01
167 #define CONFIG_SYS_CSPR3_EXT (0x0)
168 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
172 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
177 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
178 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
179 /* QIXIS Timing parameters for IFC CS3 */
180 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
181 FTIM0_GPCM_TEADC(0x0e) | \
182 FTIM0_GPCM_TEAHC(0x0e))
183 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
184 FTIM1_GPCM_TRAD(0x3f))
185 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
186 FTIM2_GPCM_TCH(0xf) | \
187 FTIM2_GPCM_TWP(0x3E))
188 #define CONFIG_SYS_CS3_FTIM3 0x0
190 #if defined(CONFIG_SPL)
191 #if defined(CONFIG_NAND_BOOT)
192 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
193 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
194 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
195 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
196 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
197 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
198 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
199 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
200 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
201 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
202 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
203 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
204 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
205 #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
206 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
207 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
208 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
209 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
210 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
211 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
212 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
213 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
214 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
215 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
216 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
217 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
218 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
220 #define CONFIG_SPL_PAD_TO 0x20000
221 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
222 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
225 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
226 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
227 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
228 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
229 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
230 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
231 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
232 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
233 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
234 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
235 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
236 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
237 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
238 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
239 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
240 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
241 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
242 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
243 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
244 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
245 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
246 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
247 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
248 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
249 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
250 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
251 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
254 /* Debug Server firmware */
255 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
256 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
258 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
263 #define I2C_MUX_PCA_ADDR 0x77
264 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
266 /* I2C bus multiplexer */
267 #define I2C_MUX_CH_DEFAULT 0x8
270 #ifdef CONFIG_FSL_DSPI
271 #define CONFIG_SPI_FLASH_STMICRO
272 #define CONFIG_SPI_FLASH_SST
273 #define CONFIG_SPI_FLASH_EON
276 #ifdef CONFIG_FSL_QSPI
277 #define CONFIG_SPI_FLASH_SPANSION
280 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
281 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
282 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
284 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
290 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
291 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
298 #define CONFIG_RTC_DS3231 1
299 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
300 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
301 #define CONFIG_RTC_ENABLE_32KHZ_OUTPUT
304 #define CONFIG_SYS_I2C_EEPROM_NXID
305 #define CONFIG_SYS_EEPROM_BUS_NUM 0
307 #define CONFIG_FSL_MEMAC
310 #define CONFIG_PCI_SCAN_SHOW
313 /* Initial environment variables */
314 #undef CONFIG_EXTRA_ENV_SETTINGS
315 #ifdef CONFIG_NXP_ESBC
316 #define CONFIG_EXTRA_ENV_SETTINGS \
317 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
318 "loadaddr=0x80100000\0" \
319 "kernel_addr=0x100000\0" \
320 "ramdisk_addr=0x800000\0" \
321 "ramdisk_size=0x2000000\0" \
322 "fdt_high=0xa0000000\0" \
323 "initrd_high=0xffffffffffffffff\0" \
324 "kernel_start=0x581000000\0" \
325 "kernel_load=0xa0000000\0" \
326 "kernel_size=0x2800000\0" \
327 "mcmemsize=0x40000000\0" \
328 "mcinitcmd=esbc_validate 0x580640000;" \
329 "esbc_validate 0x580680000;" \
330 "fsl_mc start mc 0x580a00000" \
333 #ifdef CONFIG_TFABOOT
334 #define SD_MC_INIT_CMD \
335 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
336 "mmc read 0x80e00000 0x7000 0x800;" \
337 "fsl_mc start mc 0x80a00000 0x80e00000\0"
338 #define IFC_MC_INIT_CMD \
339 "fsl_mc start mc 0x580a00000" \
341 #define CONFIG_EXTRA_ENV_SETTINGS \
342 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
343 "loadaddr=0x80100000\0" \
344 "loadaddr_sd=0x90100000\0" \
345 "kernel_addr=0x581000000\0" \
346 "kernel_addr_sd=0x8000\0" \
347 "ramdisk_addr=0x800000\0" \
348 "ramdisk_size=0x2000000\0" \
349 "fdt_high=0xa0000000\0" \
350 "initrd_high=0xffffffffffffffff\0" \
351 "kernel_start=0x581000000\0" \
352 "kernel_start_sd=0x8000\0" \
353 "kernel_load=0xa0000000\0" \
354 "kernel_size=0x2800000\0" \
355 "kernel_size_sd=0x14000\0" \
356 "load_addr=0xa0000000\0" \
357 "kernelheader_addr=0x580600000\0" \
358 "kernelheader_addr_r=0x80200000\0" \
359 "kernelheader_size=0x40000\0" \
360 "BOARD=ls2088aqds\0" \
361 "mcmemsize=0x70000000 \0" \
362 "scriptaddr=0x80000000\0" \
363 "scripthdraddr=0x80080000\0" \
366 "boot_scripts=ls2088aqds_boot.scr\0" \
367 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
368 "scan_dev_for_boot_part=" \
369 "part list ${devtype} ${devnum} devplist; " \
370 "env exists devplist || setenv devplist 1; " \
371 "for distro_bootpart in ${devplist}; do " \
372 "if fstype ${devtype} " \
373 "${devnum}:${distro_bootpart} " \
374 "bootfstype; then " \
375 "run scan_dev_for_boot; " \
379 "load ${devtype} ${devnum}:${distro_bootpart} " \
380 "${scriptaddr} ${prefix}${script}; " \
381 "env exists secureboot && load ${devtype} " \
382 "${devnum}:${distro_bootpart} " \
383 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
384 "&& esbc_validate ${scripthdraddr};" \
385 "source ${scriptaddr}\0" \
386 "nor_bootcmd=echo Trying load from nor..;" \
387 "cp.b $kernel_addr $load_addr " \
388 "$kernel_size ; env exists secureboot && " \
389 "cp.b $kernelheader_addr $kernelheader_addr_r " \
390 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
391 "bootm $load_addr#$BOARD\0" \
392 "sd_bootcmd=echo Trying load from SD ..;" \
393 "mmcinfo; mmc read $load_addr " \
394 "$kernel_addr_sd $kernel_size_sd && " \
395 "bootm $load_addr#$BOARD\0"
396 #elif defined(CONFIG_SD_BOOT)
397 #define CONFIG_EXTRA_ENV_SETTINGS \
398 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
399 "loadaddr=0x90100000\0" \
400 "kernel_addr=0x800\0" \
401 "ramdisk_addr=0x800000\0" \
402 "ramdisk_size=0x2000000\0" \
403 "fdt_high=0xa0000000\0" \
404 "initrd_high=0xffffffffffffffff\0" \
405 "kernel_start=0x8000\0" \
406 "kernel_load=0xa0000000\0" \
407 "kernel_size=0x14000\0" \
408 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
409 "mmc read 0x80e00000 0x7000 0x800;" \
410 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
411 "mcmemsize=0x70000000 \0"
413 #define CONFIG_EXTRA_ENV_SETTINGS \
414 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
415 "loadaddr=0x80100000\0" \
416 "kernel_addr=0x100000\0" \
417 "ramdisk_addr=0x800000\0" \
418 "ramdisk_size=0x2000000\0" \
419 "fdt_high=0xa0000000\0" \
420 "initrd_high=0xffffffffffffffff\0" \
421 "kernel_start=0x581000000\0" \
422 "kernel_load=0xa0000000\0" \
423 "kernel_size=0x2800000\0" \
424 "mcmemsize=0x40000000\0" \
425 "mcinitcmd=fsl_mc start mc 0x580a00000" \
427 #endif /* CONFIG_TFABOOT */
428 #endif /* CONFIG_NXP_ESBC */
430 #ifdef CONFIG_TFABOOT
431 #define BOOT_TARGET_DEVICES(func) \
434 func(SCSI, scsi, 0) \
436 #include <config_distro_bootcmd.h>
438 #define SD_BOOTCOMMAND \
439 "env exists mcinitcmd && env exists secureboot "\
440 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
441 "&& esbc_validate $load_addr; " \
442 "env exists mcinitcmd && run mcinitcmd " \
443 "&& mmc read 0x80d00000 0x6800 0x800 " \
444 "&& fsl_mc lazyapply dpl 0x80d00000; " \
445 "run distro_bootcmd;run sd_bootcmd; " \
446 "env exists secureboot && esbc_halt;"
448 #define IFC_NOR_BOOTCOMMAND \
449 "env exists mcinitcmd && env exists secureboot "\
450 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
451 "&& fsl_mc lazyapply dpl 0x580d00000;" \
452 "run distro_bootcmd;run nor_bootcmd; " \
453 "env exists secureboot && esbc_halt;"
456 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
457 #define CONFIG_FSL_MEMAC
458 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
459 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
460 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
461 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
463 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
464 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
465 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
466 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
467 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
468 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
469 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
470 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
471 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
472 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
473 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
474 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
475 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
476 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
477 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
478 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
480 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
484 #include <asm/fsl_secure_boot.h>
486 #endif /* __LS2_QDS_H */