1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #ifdef CONFIG_FSL_QSPI
13 #define CFG_SYS_I2C_IFDR_DIV 0x7e
16 #define CFG_SYS_I2C_FPGA_ADDR 0x66
17 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
19 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
20 #define SPD_EEPROM_ADDRESS1 0x51
21 #define SPD_EEPROM_ADDRESS2 0x52
22 #define SPD_EEPROM_ADDRESS3 0x53
23 #define SPD_EEPROM_ADDRESS4 0x54
24 #define SPD_EEPROM_ADDRESS5 0x55
25 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
26 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
28 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
29 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
30 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
32 #define CFG_SYS_NOR0_CSPR \
33 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
37 #define CFG_SYS_NOR0_CSPR_EARLY \
38 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
42 #define CFG_SYS_NOR1_CSPR \
43 (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \
47 #define CFG_SYS_NOR1_CSPR_EARLY \
48 (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
52 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
53 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
54 FTIM0_NOR_TEADC(0x5) | \
56 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
57 FTIM1_NOR_TRAD_NOR(0x1a) |\
58 FTIM1_NOR_TSEQRAD_NOR(0x13))
59 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
60 FTIM2_NOR_TCH(0x4) | \
61 FTIM2_NOR_TWPH(0x0E) | \
63 #define CFG_SYS_NOR_FTIM3 0x04000000
64 #define CFG_SYS_IFC_CCR 0x01000000
66 #ifdef CONFIG_MTD_NOR_FLASH
67 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
69 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
70 CFG_SYS_FLASH_BASE + 0x40000000}
73 #define CFG_SYS_NAND_CSPR_EXT (0x0)
74 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
75 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
76 | CSPR_MSEL_NAND /* MSEL = NAND */ \
78 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
80 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
81 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
82 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
83 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
84 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
85 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
86 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
88 /* ONFI NAND Flash mode0 Timing Params */
89 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
90 FTIM0_NAND_TWP(0x18) | \
91 FTIM0_NAND_TWCHT(0x07) | \
93 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
94 FTIM1_NAND_TWBE(0x39) | \
95 FTIM1_NAND_TRR(0x0e) | \
97 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
98 FTIM2_NAND_TREH(0x0a) | \
99 FTIM2_NAND_TWHRE(0x1e))
100 #define CFG_SYS_NAND_FTIM3 0x0
102 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
103 #define CONFIG_MTD_NAND_VERIFY_WRITE
105 #define QIXIS_LBMAP_SWITCH 0x06
106 #define QIXIS_LBMAP_MASK 0x0f
107 #define QIXIS_LBMAP_SHIFT 0
108 #define QIXIS_LBMAP_DFLTBANK 0x00
109 #define QIXIS_LBMAP_ALTBANK 0x04
110 #define QIXIS_LBMAP_NAND 0x09
111 #define QIXIS_LBMAP_SD 0x00
112 #define QIXIS_LBMAP_QSPI 0x0f
113 #define QIXIS_RST_CTL_RESET 0x31
114 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
115 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
116 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
117 #define QIXIS_RCW_SRC_NAND 0x107
118 #define QIXIS_RCW_SRC_SD 0x40
119 #define QIXIS_RCW_SRC_QSPI 0x62
120 #define QIXIS_RST_FORCE_MEM 0x01
122 #define CFG_SYS_CSPR3_EXT (0x0)
123 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
127 #define CFG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
132 #define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
133 #define CFG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
134 /* QIXIS Timing parameters for IFC CS3 */
135 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
136 FTIM0_GPCM_TEADC(0x0e) | \
137 FTIM0_GPCM_TEAHC(0x0e))
138 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
139 FTIM1_GPCM_TRAD(0x3f))
140 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
141 FTIM2_GPCM_TCH(0xf) | \
142 FTIM2_GPCM_TWP(0x3E))
143 #define CFG_SYS_CS3_FTIM3 0x0
145 #if defined(CONFIG_SPL)
146 #if defined(CONFIG_NAND_BOOT)
147 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
148 #define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR_EARLY
149 #define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR0_CSPR
150 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
151 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
152 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
153 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
154 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
155 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
156 #define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
157 #define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR_EARLY
158 #define CFG_SYS_CSPR2_FINAL CFG_SYS_NOR1_CSPR
159 #define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY
160 #define CFG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK
161 #define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
162 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
163 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
164 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
165 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
166 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
167 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
168 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
169 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
170 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
171 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
172 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
173 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
175 #define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
178 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
179 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
180 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
181 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
182 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
183 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
184 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
185 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
186 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
187 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
188 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
189 #define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
190 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
191 #define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
192 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
193 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
194 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
195 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
196 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
197 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
198 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
199 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
200 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
201 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
202 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
203 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
204 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
207 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
212 #define I2C_MUX_PCA_ADDR 0x77
213 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
215 /* I2C bus multiplexer */
216 #define I2C_MUX_CH_DEFAULT 0x8
221 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
222 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
223 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
225 #define FSL_QIXIS_BRDCFG9_QSPI 0x1
230 #define CFG_SYS_I2C_RTC_ADDR 0x68
232 /* Initial environment variables */
233 #undef CONFIG_EXTRA_ENV_SETTINGS
234 #ifdef CONFIG_NXP_ESBC
235 #define CONFIG_EXTRA_ENV_SETTINGS \
236 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
237 "loadaddr=0x80100000\0" \
238 "kernel_addr=0x100000\0" \
239 "ramdisk_addr=0x800000\0" \
240 "ramdisk_size=0x2000000\0" \
241 "fdt_high=0xa0000000\0" \
242 "initrd_high=0xffffffffffffffff\0" \
243 "kernel_start=0x581000000\0" \
244 "kernel_load=0xa0000000\0" \
245 "kernel_size=0x2800000\0" \
246 "mcmemsize=0x40000000\0" \
247 "mcinitcmd=esbc_validate 0x580640000;" \
248 "esbc_validate 0x580680000;" \
249 "fsl_mc start mc 0x580a00000" \
252 #ifdef CONFIG_TFABOOT
253 #define SD_MC_INIT_CMD \
254 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
255 "mmc read 0x80e00000 0x7000 0x800;" \
256 "fsl_mc start mc 0x80a00000 0x80e00000\0"
257 #define IFC_MC_INIT_CMD \
258 "fsl_mc start mc 0x580a00000" \
260 #define CONFIG_EXTRA_ENV_SETTINGS \
261 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
262 "loadaddr=0x80100000\0" \
263 "loadaddr_sd=0x90100000\0" \
264 "kernel_addr=0x581000000\0" \
265 "kernel_addr_sd=0x8000\0" \
266 "ramdisk_addr=0x800000\0" \
267 "ramdisk_size=0x2000000\0" \
268 "fdt_high=0xa0000000\0" \
269 "initrd_high=0xffffffffffffffff\0" \
270 "kernel_start=0x581000000\0" \
271 "kernel_start_sd=0x8000\0" \
272 "kernel_load=0xa0000000\0" \
273 "kernel_size=0x2800000\0" \
274 "kernel_size_sd=0x14000\0" \
275 "load_addr=0xa0000000\0" \
276 "kernelheader_addr=0x580600000\0" \
277 "kernelheader_addr_r=0x80200000\0" \
278 "kernelheader_size=0x40000\0" \
279 "BOARD=ls2088aqds\0" \
280 "mcmemsize=0x70000000 \0" \
281 "scriptaddr=0x80000000\0" \
282 "scripthdraddr=0x80080000\0" \
285 "boot_scripts=ls2088aqds_boot.scr\0" \
286 "boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
287 "scan_dev_for_boot_part=" \
288 "part list ${devtype} ${devnum} devplist; " \
289 "env exists devplist || setenv devplist 1; " \
290 "for distro_bootpart in ${devplist}; do " \
291 "if fstype ${devtype} " \
292 "${devnum}:${distro_bootpart} " \
293 "bootfstype; then " \
294 "run scan_dev_for_boot; " \
298 "load ${devtype} ${devnum}:${distro_bootpart} " \
299 "${scriptaddr} ${prefix}${script}; " \
300 "env exists secureboot && load ${devtype} " \
301 "${devnum}:${distro_bootpart} " \
302 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
303 "&& esbc_validate ${scripthdraddr};" \
304 "source ${scriptaddr}\0" \
305 "nor_bootcmd=echo Trying load from nor..;" \
306 "cp.b $kernel_addr $load_addr " \
307 "$kernel_size ; env exists secureboot && " \
308 "cp.b $kernelheader_addr $kernelheader_addr_r " \
309 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
310 "bootm $load_addr#$BOARD\0" \
311 "sd_bootcmd=echo Trying load from SD ..;" \
312 "mmcinfo; mmc read $load_addr " \
313 "$kernel_addr_sd $kernel_size_sd && " \
314 "bootm $load_addr#$BOARD\0"
315 #elif defined(CONFIG_SD_BOOT)
316 #define CONFIG_EXTRA_ENV_SETTINGS \
317 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
318 "loadaddr=0x90100000\0" \
319 "kernel_addr=0x800\0" \
320 "ramdisk_addr=0x800000\0" \
321 "ramdisk_size=0x2000000\0" \
322 "fdt_high=0xa0000000\0" \
323 "initrd_high=0xffffffffffffffff\0" \
324 "kernel_start=0x8000\0" \
325 "kernel_load=0xa0000000\0" \
326 "kernel_size=0x14000\0" \
327 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
328 "mmc read 0x80e00000 0x7000 0x800;" \
329 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
330 "mcmemsize=0x70000000 \0"
332 #define CONFIG_EXTRA_ENV_SETTINGS \
333 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
334 "loadaddr=0x80100000\0" \
335 "kernel_addr=0x100000\0" \
336 "ramdisk_addr=0x800000\0" \
337 "ramdisk_size=0x2000000\0" \
338 "fdt_high=0xa0000000\0" \
339 "initrd_high=0xffffffffffffffff\0" \
340 "kernel_start=0x581000000\0" \
341 "kernel_load=0xa0000000\0" \
342 "kernel_size=0x2800000\0" \
343 "mcmemsize=0x40000000\0" \
344 "mcinitcmd=fsl_mc start mc 0x580a00000" \
346 #endif /* CONFIG_TFABOOT */
347 #endif /* CONFIG_NXP_ESBC */
349 #ifdef CONFIG_TFABOOT
350 #define BOOT_TARGET_DEVICES(func) \
353 func(SCSI, scsi, 0) \
355 #include <config_distro_bootcmd.h>
357 #define SD_BOOTCOMMAND \
358 "env exists mcinitcmd && env exists secureboot "\
359 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
360 "&& esbc_validate $load_addr; " \
361 "env exists mcinitcmd && run mcinitcmd " \
362 "&& mmc read 0x80d00000 0x6800 0x800 " \
363 "&& fsl_mc lazyapply dpl 0x80d00000; " \
364 "run distro_bootcmd;run sd_bootcmd; " \
365 "env exists secureboot && esbc_halt;"
367 #define IFC_NOR_BOOTCOMMAND \
368 "env exists mcinitcmd && env exists secureboot "\
369 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
370 "&& fsl_mc lazyapply dpl 0x580d00000;" \
371 "run distro_bootcmd;run nor_bootcmd; " \
372 "env exists secureboot && esbc_halt;"
375 #if defined(CONFIG_FSL_MC_ENET)
376 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
377 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
378 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
379 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
381 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
382 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
383 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
384 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
385 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
386 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
387 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
388 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
389 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
390 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
391 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
392 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
393 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
394 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
395 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
396 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
400 #include <asm/fsl_secure_boot.h>
402 #endif /* __LS2_QDS_H */