Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / ls2080aqds.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2017 NXP
4  * Copyright 2015 Freescale Semiconductor
5  */
6
7 #ifndef __LS2_QDS_H
8 #define __LS2_QDS_H
9
10 #include "ls2080a_common.h"
11
12 #ifndef __ASSEMBLY__
13 unsigned long get_board_sys_clk(void);
14 unsigned long get_board_ddr_clk(void);
15 #endif
16
17 #ifdef CONFIG_FSL_QSPI
18 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_I2C_EARLY_INIT
20 #define CONFIG_SYS_I2C_IFDR_DIV         0x7e
21 #endif
22
23 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
24 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
25 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
26 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
27
28 #define CONFIG_DDR_SPD
29 #define CONFIG_DDR_ECC
30 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
31 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
32 #define SPD_EEPROM_ADDRESS1     0x51
33 #define SPD_EEPROM_ADDRESS2     0x52
34 #define SPD_EEPROM_ADDRESS3     0x53
35 #define SPD_EEPROM_ADDRESS4     0x54
36 #define SPD_EEPROM_ADDRESS5     0x55
37 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
38 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
39 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
40 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
41 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
42 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
43 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
44 #endif
45
46 /* SATA */
47 #define CONFIG_SCSI_AHCI_PLAT
48
49 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
50 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
51
52 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
53 #define CONFIG_SYS_SCSI_MAX_LUN                 1
54 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
55                                                 CONFIG_SYS_SCSI_MAX_LUN)
56
57 #ifdef CONFIG_TFABOOT
58 #define CONFIG_SYS_MMC_ENV_DEV          0
59 #define CONFIG_ENV_SIZE                 0x20000
60 #define CONFIG_ENV_OFFSET               0x500000
61 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
62                                          CONFIG_ENV_OFFSET)
63 #define CONFIG_ENV_SECT_SIZE            0x20000
64 #endif
65
66 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
67 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
68 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
69
70 #define CONFIG_SYS_NOR0_CSPR                                    \
71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
72         CSPR_PORT_SIZE_16                                       | \
73         CSPR_MSEL_NOR                                           | \
74         CSPR_V)
75 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
76         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
77         CSPR_PORT_SIZE_16                                       | \
78         CSPR_MSEL_NOR                                           | \
79         CSPR_V)
80 #define CONFIG_SYS_NOR1_CSPR                                    \
81         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
82         CSPR_PORT_SIZE_16                                       | \
83         CSPR_MSEL_NOR                                           | \
84         CSPR_V)
85 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
86         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
87         CSPR_PORT_SIZE_16                                       | \
88         CSPR_MSEL_NOR                                           | \
89         CSPR_V)
90 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
91 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
92                                 FTIM0_NOR_TEADC(0x5) | \
93                                 FTIM0_NOR_TEAHC(0x5))
94 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
95                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
96                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
97 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
98                                 FTIM2_NOR_TCH(0x4) | \
99                                 FTIM2_NOR_TWPH(0x0E) | \
100                                 FTIM2_NOR_TWP(0x1c))
101 #define CONFIG_SYS_NOR_FTIM3    0x04000000
102 #define CONFIG_SYS_IFC_CCR      0x01000000
103
104 #ifdef CONFIG_MTD_NOR_FLASH
105 #define CONFIG_SYS_FLASH_QUIET_TEST
106 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
107
108 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
109 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
110 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
111 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
112
113 #define CONFIG_SYS_FLASH_EMPTY_INFO
114 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
115                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
116 #endif
117
118 #define CONFIG_NAND_FSL_IFC
119 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
120 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
121
122 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
123 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
124                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
125                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
126                                 | CSPR_V)
127 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
128
129 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
130                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
131                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
132                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
133                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
134                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
135                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
136
137 #define CONFIG_SYS_NAND_ONFI_DETECTION
138
139 /* ONFI NAND Flash mode0 Timing Params */
140 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
141                                         FTIM0_NAND_TWP(0x18)   | \
142                                         FTIM0_NAND_TWCHT(0x07) | \
143                                         FTIM0_NAND_TWH(0x0a))
144 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
145                                         FTIM1_NAND_TWBE(0x39)  | \
146                                         FTIM1_NAND_TRR(0x0e)   | \
147                                         FTIM1_NAND_TRP(0x18))
148 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
149                                         FTIM2_NAND_TREH(0x0a) | \
150                                         FTIM2_NAND_TWHRE(0x1e))
151 #define CONFIG_SYS_NAND_FTIM3           0x0
152
153 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
154 #define CONFIG_SYS_MAX_NAND_DEVICE      1
155 #define CONFIG_MTD_NAND_VERIFY_WRITE
156
157 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
158
159 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
160 #define QIXIS_LBMAP_SWITCH              0x06
161 #define QIXIS_LBMAP_MASK                0x0f
162 #define QIXIS_LBMAP_SHIFT               0
163 #define QIXIS_LBMAP_DFLTBANK            0x00
164 #define QIXIS_LBMAP_ALTBANK             0x04
165 #define QIXIS_LBMAP_NAND                0x09
166 #define QIXIS_LBMAP_SD                  0x00
167 #define QIXIS_LBMAP_QSPI                0x0f
168 #define QIXIS_RST_CTL_RESET             0x31
169 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
170 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
171 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
172 #define QIXIS_RCW_SRC_NAND              0x107
173 #define QIXIS_RCW_SRC_SD                0x40
174 #define QIXIS_RCW_SRC_QSPI              0x62
175 #define QIXIS_RST_FORCE_MEM             0x01
176
177 #define CONFIG_SYS_CSPR3_EXT    (0x0)
178 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
179                                 | CSPR_PORT_SIZE_8 \
180                                 | CSPR_MSEL_GPCM \
181                                 | CSPR_V)
182 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
183                                 | CSPR_PORT_SIZE_8 \
184                                 | CSPR_MSEL_GPCM \
185                                 | CSPR_V)
186
187 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
188 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
189 /* QIXIS Timing parameters for IFC CS3 */
190 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
191                                         FTIM0_GPCM_TEADC(0x0e) | \
192                                         FTIM0_GPCM_TEAHC(0x0e))
193 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
194                                         FTIM1_GPCM_TRAD(0x3f))
195 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
196                                         FTIM2_GPCM_TCH(0xf) | \
197                                         FTIM2_GPCM_TWP(0x3E))
198 #define CONFIG_SYS_CS3_FTIM3            0x0
199
200 #if defined(CONFIG_SPL)
201 #if defined(CONFIG_NAND_BOOT)
202 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
203 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR_EARLY
204 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR0_CSPR
205 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
206 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
207 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
208 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
209 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
210 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
211 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
212 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR_EARLY
213 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR1_CSPR
214 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK_EARLY
215 #define CONFIG_SYS_AMASK2_FINAL         CONFIG_SYS_NOR_AMASK
216 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
217 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
218 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
219 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
220 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
221 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
222 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
223 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
224 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
225 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
226 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
227 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
228 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
229
230 #define CONFIG_ENV_OFFSET               (896 * 1024)
231 #define CONFIG_ENV_SECT_SIZE            0x20000
232 #define CONFIG_ENV_SIZE                 0x2000
233 #define CONFIG_SPL_PAD_TO               0x20000
234 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 * 1024)
235 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 * 1024)
236 #elif defined(CONFIG_SD_BOOT)
237 #define CONFIG_ENV_OFFSET               0x300000
238 #define CONFIG_SYS_MMC_ENV_DEV          0
239 #define CONFIG_ENV_SIZE                 0x20000
240 #endif
241 #else
242 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
243 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
244 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
245 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
246 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
247 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
248 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
249 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
250 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
251 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
252 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
253 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
254 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
255 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
256 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
257 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
258 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
259 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
260 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
261 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
262 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
263 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
264 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
265 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
266 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
267 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
268 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
269
270 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT)
271 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
272 #define CONFIG_ENV_SECT_SIZE            0x20000
273 #define CONFIG_ENV_SIZE                 0x2000
274 #endif
275 #endif
276
277 /* Debug Server firmware */
278 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
279 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
280
281 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
282
283 /*
284  * I2C
285  */
286 #define I2C_MUX_PCA_ADDR                0x77
287 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
288
289 /* I2C bus multiplexer */
290 #define I2C_MUX_CH_DEFAULT      0x8
291
292 /* SPI */
293 #if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
294 #ifdef CONFIG_FSL_DSPI
295 #define CONFIG_SPI_FLASH_STMICRO
296 #define CONFIG_SPI_FLASH_SST
297 #define CONFIG_SPI_FLASH_EON
298 #endif
299
300 #ifdef CONFIG_FSL_QSPI
301 #define CONFIG_SPI_FLASH_SPANSION
302 #define FSL_QSPI_FLASH_SIZE             (1 << 26) /* 64MB */
303 #define FSL_QSPI_FLASH_NUM              4
304 #endif
305 /*
306  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
307  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
308  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
309  */
310 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
311
312 #endif
313
314 /*
315  * MMC
316  */
317 #ifdef CONFIG_MMC
318 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
319         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
320 #endif
321
322 /*
323  * RTC configuration
324  */
325 #define RTC
326 #define CONFIG_RTC_DS3231               1
327 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
328
329 /* EEPROM */
330 #define CONFIG_ID_EEPROM
331 #define CONFIG_SYS_I2C_EEPROM_NXID
332 #define CONFIG_SYS_EEPROM_BUS_NUM       0
333 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
335 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
336 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
337
338 #define CONFIG_FSL_MEMAC
339
340 #ifdef CONFIG_PCI
341 #define CONFIG_PCI_SCAN_SHOW
342 #endif
343
344 /*  MMC  */
345 #ifdef CONFIG_MMC
346 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
347 #endif
348
349 /* Initial environment variables */
350 #undef CONFIG_EXTRA_ENV_SETTINGS
351 #ifdef CONFIG_SECURE_BOOT
352 #define CONFIG_EXTRA_ENV_SETTINGS               \
353         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
354         "loadaddr=0x80100000\0"                 \
355         "kernel_addr=0x100000\0"                \
356         "ramdisk_addr=0x800000\0"               \
357         "ramdisk_size=0x2000000\0"              \
358         "fdt_high=0xa0000000\0"                 \
359         "initrd_high=0xffffffffffffffff\0"      \
360         "kernel_start=0x581000000\0"            \
361         "kernel_load=0xa0000000\0"              \
362         "kernel_size=0x2800000\0"               \
363         "mcmemsize=0x40000000\0"                \
364         "mcinitcmd=esbc_validate 0x580700000;"  \
365         "esbc_validate 0x580740000;"            \
366         "fsl_mc start mc 0x580a00000"           \
367         " 0x580e00000 \0"
368 #else
369 #ifdef CONFIG_TFABOOT
370 #define SD_MC_INIT_CMD                          \
371         "mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
372         "mmc read 0x80100000 0x7000 0x800;" \
373         "fsl_mc start mc 0x80000000 0x80100000\0"
374 #define IFC_MC_INIT_CMD                         \
375         "fsl_mc start mc 0x580a00000" \
376         " 0x580e00000 \0"
377 #define CONFIG_EXTRA_ENV_SETTINGS               \
378         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
379         "loadaddr=0x80100000\0"                 \
380         "loadaddr_sd=0x90100000\0"                 \
381         "kernel_addr=0x100000\0"                \
382         "kernel_addr_sd=0x800\0"                \
383         "ramdisk_addr=0x800000\0"               \
384         "ramdisk_size=0x2000000\0"              \
385         "fdt_high=0xa0000000\0"                 \
386         "initrd_high=0xffffffffffffffff\0"      \
387         "kernel_start=0x581000000\0"            \
388         "kernel_start_sd=0x8000\0"              \
389         "kernel_load=0xa0000000\0"              \
390         "kernel_size=0x2800000\0"               \
391         "kernel_size_sd=0x14000\0"               \
392         "mcinitcmd=fsl_mc start mc 0x580a00000" \
393         " 0x580e00000 \0"                       \
394         "mcmemsize=0x70000000 \0"
395 #elif defined(CONFIG_SD_BOOT)
396 #define CONFIG_EXTRA_ENV_SETTINGS               \
397         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
398         "loadaddr=0x90100000\0"                 \
399         "kernel_addr=0x800\0"                \
400         "ramdisk_addr=0x800000\0"               \
401         "ramdisk_size=0x2000000\0"              \
402         "fdt_high=0xa0000000\0"                 \
403         "initrd_high=0xffffffffffffffff\0"      \
404         "kernel_start=0x8000\0"              \
405         "kernel_load=0xa0000000\0"              \
406         "kernel_size=0x14000\0"               \
407         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
408         "mmc read 0x80100000 0x7000 0x800;" \
409         "fsl_mc start mc 0x80000000 0x80100000\0"       \
410         "mcmemsize=0x70000000 \0"
411 #else
412 #define CONFIG_EXTRA_ENV_SETTINGS               \
413         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
414         "loadaddr=0x80100000\0"                 \
415         "kernel_addr=0x100000\0"                \
416         "ramdisk_addr=0x800000\0"               \
417         "ramdisk_size=0x2000000\0"              \
418         "fdt_high=0xa0000000\0"                 \
419         "initrd_high=0xffffffffffffffff\0"      \
420         "kernel_start=0x581000000\0"            \
421         "kernel_load=0xa0000000\0"              \
422         "kernel_size=0x2800000\0"               \
423         "mcmemsize=0x40000000\0"                \
424         "mcinitcmd=fsl_mc start mc 0x580a00000" \
425         " 0x580e00000 \0"
426 #endif /* CONFIG_TFABOOT */
427 #endif /* CONFIG_SECURE_BOOT */
428
429 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
430 #define CONFIG_FSL_MEMAC
431 #define CONFIG_PHYLIB_10G
432 #define CONFIG_PHY_VITESSE
433 #define CONFIG_PHY_REALTEK
434 #define CONFIG_PHY_TERANETICS
435 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
436 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
437 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
438 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
439
440 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
441 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
442 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
443 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
444 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
445 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
446 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
447 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
448 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
449 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
450 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
451 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
452 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
453 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
454 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
455 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
456
457 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
458
459 #endif
460
461 #include <asm/fsl_secure_boot.h>
462
463 #endif /* __LS2_QDS_H */