include/configs/ls2080aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_QDS_H
   8 #define __LS2_QDS_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #define CFG_SYS_I2C_IFDR_DIV            0x7e
  14 #endif
  15
  16 #define CFG_SYS_I2C_FPGA_ADDR   0x66
  17 #define COUNTER_FREQUENCY_REAL          (get_board_sys_clk()/4)
  18
  19 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  20 #define SPD_EEPROM_ADDRESS1     0x51
  21 #define SPD_EEPROM_ADDRESS2     0x52
  22 #define SPD_EEPROM_ADDRESS3     0x53
  23 #define SPD_EEPROM_ADDRESS4     0x54
  24 #define SPD_EEPROM_ADDRESS5     0x55
  25 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  26 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  27
  28 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  29 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128*1024*1024)
  30 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  31
  32 #define CFG_SYS_NOR0_CSPR                                       \
  33         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)                | \
  34         CSPR_PORT_SIZE_16                                       | \
  35         CSPR_MSEL_NOR                                           | \
  36         CSPR_V)
  37 #define CFG_SYS_NOR0_CSPR_EARLY                         \
  38         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)  | \
  39         CSPR_PORT_SIZE_16                                       | \
  40         CSPR_MSEL_NOR                                           | \
  41         CSPR_V)
  42 #define CFG_SYS_NOR1_CSPR                                       \
  43         (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS)               | \
  44         CSPR_PORT_SIZE_16                                       | \
  45         CSPR_MSEL_NOR                                           | \
  46         CSPR_V)
  47 #define CFG_SYS_NOR1_CSPR_EARLY                         \
  48         (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  49         CSPR_PORT_SIZE_16                                       | \
  50         CSPR_MSEL_NOR                                           | \
  51         CSPR_V)
  52 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(12)
  53 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
  54                                 FTIM0_NOR_TEADC(0x5) | \
  55                                 FTIM0_NOR_TEAHC(0x5))
  56 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
  57                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  58                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  59 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
  60                                 FTIM2_NOR_TCH(0x4) | \
  61                                 FTIM2_NOR_TWPH(0x0E) | \
  62                                 FTIM2_NOR_TWP(0x1c))
  63 #define CFG_SYS_NOR_FTIM3       0x04000000
  64 #define CFG_SYS_IFC_CCR 0x01000000
  65
  66 #ifdef CONFIG_MTD_NOR_FLASH
  67 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE,\
  68                                          CFG_SYS_FLASH_BASE + 0x40000000}
  69 #endif
  70
  71 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  72 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  73                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  74                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  75                                 | CSPR_V)
  76 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  77
  78 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  79                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  80                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  81                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  82                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  83                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  84                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  85
  86 /* ONFI NAND Flash mode0 Timing Params */
  87 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
  88                                         FTIM0_NAND_TWP(0x18)   | \
  89                                         FTIM0_NAND_TWCHT(0x07) | \
  90                                         FTIM0_NAND_TWH(0x0a))
  91 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  92                                         FTIM1_NAND_TWBE(0x39)  | \
  93                                         FTIM1_NAND_TRR(0x0e)   | \
  94                                         FTIM1_NAND_TRP(0x18))
  95 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
  96                                         FTIM2_NAND_TREH(0x0a) | \
  97                                         FTIM2_NAND_TWHRE(0x1e))
  98 #define CFG_SYS_NAND_FTIM3              0x0
  99
 100 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 101 #define CONFIG_MTD_NAND_VERIFY_WRITE
 102
 103 #define QIXIS_LBMAP_SWITCH              0x06
 104 #define QIXIS_LBMAP_MASK                0x0f
 105 #define QIXIS_LBMAP_SHIFT               0
 106 #define QIXIS_LBMAP_DFLTBANK            0x00
 107 #define QIXIS_LBMAP_ALTBANK             0x04
 108 #define QIXIS_LBMAP_NAND                0x09
 109 #define QIXIS_LBMAP_SD                  0x00
 110 #define QIXIS_LBMAP_QSPI                0x0f
 111 #define QIXIS_RST_CTL_RESET             0x31
 112 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 113 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 114 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 115 #define QIXIS_RCW_SRC_NAND              0x107
 116 #define QIXIS_RCW_SRC_SD                0x40
 117 #define QIXIS_RCW_SRC_QSPI              0x62
 118 #define QIXIS_RST_FORCE_MEM             0x01
 119
 120 #define CFG_SYS_CSPR3_EXT       (0x0)
 121 #define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 122                                 | CSPR_PORT_SIZE_8 \
 123                                 | CSPR_MSEL_GPCM \
 124                                 | CSPR_V)
 125 #define CFG_SYS_CSPR3_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 126                                 | CSPR_PORT_SIZE_8 \
 127                                 | CSPR_MSEL_GPCM \
 128                                 | CSPR_V)
 129
 130 #define CFG_SYS_AMASK3  IFC_AMASK(64*1024)
 131 #define CFG_SYS_CSOR3   CSOR_GPCM_ADM_SHIFT(12)
 132 /* QIXIS Timing parameters for IFC CS3 */
 133 #define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 134                                         FTIM0_GPCM_TEADC(0x0e) | \
 135                                         FTIM0_GPCM_TEAHC(0x0e))
 136 #define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0xff) | \
 137                                         FTIM1_GPCM_TRAD(0x3f))
 138 #define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0xf) | \
 139                                         FTIM2_GPCM_TCH(0xf) | \
 140                                         FTIM2_GPCM_TWP(0x3E))
 141 #define CFG_SYS_CS3_FTIM3               0x0
 142
 143 #if defined(CONFIG_SPL)
 144 #if defined(CONFIG_NAND_BOOT)
 145 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 146 #define CFG_SYS_CSPR1           CFG_SYS_NOR0_CSPR_EARLY
 147 #define CFG_SYS_CSPR1_FINAL             CFG_SYS_NOR0_CSPR
 148 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK
 149 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 150 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 151 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 152 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 153 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 154 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR0_CSPR_EXT
 155 #define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR_EARLY
 156 #define CFG_SYS_CSPR2_FINAL             CFG_SYS_NOR1_CSPR
 157 #define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK_EARLY
 158 #define CFG_SYS_AMASK2_FINAL            CFG_SYS_NOR_AMASK
 159 #define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 160 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 161 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 162 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 163 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 164 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 165 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 166 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 167 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 168 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 169 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 170 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 171 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 172
 173 #define CFG_SYS_NAND_U_BOOT_SIZE        (640 * 1024)
 174 #endif
 175 #else
 176 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 177 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 178 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 179 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 180 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 181 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 182 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 183 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 184 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 185 #define CFG_SYS_CSPR1_EXT               CFG_SYS_NOR0_CSPR_EXT
 186 #define CFG_SYS_CSPR1           CFG_SYS_NOR1_CSPR_EARLY
 187 #define CFG_SYS_CSPR1_FINAL             CFG_SYS_NOR1_CSPR
 188 #define CFG_SYS_AMASK1          CFG_SYS_NOR_AMASK_EARLY
 189 #define CFG_SYS_AMASK1_FINAL            CFG_SYS_NOR_AMASK
 190 #define CFG_SYS_CSOR1           CFG_SYS_NOR_CSOR
 191 #define CFG_SYS_CS1_FTIM0               CFG_SYS_NOR_FTIM0
 192 #define CFG_SYS_CS1_FTIM1               CFG_SYS_NOR_FTIM1
 193 #define CFG_SYS_CS1_FTIM2               CFG_SYS_NOR_FTIM2
 194 #define CFG_SYS_CS1_FTIM3               CFG_SYS_NOR_FTIM3
 195 #define CFG_SYS_CSPR2_EXT               CFG_SYS_NAND_CSPR_EXT
 196 #define CFG_SYS_CSPR2           CFG_SYS_NAND_CSPR
 197 #define CFG_SYS_AMASK2          CFG_SYS_NAND_AMASK
 198 #define CFG_SYS_CSOR2           CFG_SYS_NAND_CSOR
 199 #define CFG_SYS_CS2_FTIM0               CFG_SYS_NAND_FTIM0
 200 #define CFG_SYS_CS2_FTIM1               CFG_SYS_NAND_FTIM1
 201 #define CFG_SYS_CS2_FTIM2               CFG_SYS_NAND_FTIM2
 202 #define CFG_SYS_CS2_FTIM3               CFG_SYS_NAND_FTIM3
 203 #endif
 204
 205 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 206
 207 /*
 208  * I2C
 209  */
 210 #define I2C_MUX_PCA_ADDR                0x77
 211 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 212
 213 /* I2C bus multiplexer */
 214 #define I2C_MUX_CH_DEFAULT      0x8
 215
 216 /* SPI */
 217
 218 /*
 219  * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 220  * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 221  * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 222  */
 223 #define FSL_QIXIS_BRDCFG9_QSPI          0x1
 224
 225 /*
 226  * RTC configuration
 227  */
 228 #define CFG_SYS_I2C_RTC_ADDR         0x68
 229
 230 /* Initial environment variables */
 231 #undef CONFIG_EXTRA_ENV_SETTINGS
 232 #ifdef CONFIG_NXP_ESBC
 233 #define CONFIG_EXTRA_ENV_SETTINGS               \
 234         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 235         "loadaddr=0x80100000\0"                 \
 236         "kernel_addr=0x100000\0"                \
 237         "ramdisk_addr=0x800000\0"               \
 238         "ramdisk_size=0x2000000\0"              \
 239         "fdt_high=0xa0000000\0"                 \
 240         "initrd_high=0xffffffffffffffff\0"      \
 241         "kernel_start=0x581000000\0"            \
 242         "kernel_load=0xa0000000\0"              \
 243         "kernel_size=0x2800000\0"               \
 244         "mcmemsize=0x40000000\0"                \
 245         "mcinitcmd=esbc_validate 0x580640000;"  \
 246         "esbc_validate 0x580680000;"            \
 247         "fsl_mc start mc 0x580a00000"           \
 248         " 0x580e00000 \0"
 249 #else
 250 #ifdef CONFIG_TFABOOT
 251 #define SD_MC_INIT_CMD                          \
 252         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 253         "mmc read 0x80e00000 0x7000 0x800;" \
 254         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 255 #define IFC_MC_INIT_CMD                         \
 256         "fsl_mc start mc 0x580a00000" \
 257         " 0x580e00000 \0"
 258 #define CONFIG_EXTRA_ENV_SETTINGS               \
 259         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 260         "loadaddr=0x80100000\0"                 \
 261         "loadaddr_sd=0x90100000\0"                 \
 262         "kernel_addr=0x581000000\0"                       \
 263         "kernel_addr_sd=0x8000\0"                \
 264         "ramdisk_addr=0x800000\0"               \
 265         "ramdisk_size=0x2000000\0"              \
 266         "fdt_high=0xa0000000\0"                 \
 267         "initrd_high=0xffffffffffffffff\0"      \
 268         "kernel_start=0x581000000\0"            \
 269         "kernel_start_sd=0x8000\0"              \
 270         "kernel_load=0xa0000000\0"              \
 271         "kernel_size=0x2800000\0"               \
 272         "kernel_size_sd=0x14000\0"               \
 273         "load_addr=0xa0000000\0"                            \
 274         "kernelheader_addr=0x580600000\0"       \
 275         "kernelheader_addr_r=0x80200000\0"      \
 276         "kernelheader_size=0x40000\0"           \
 277         "BOARD=ls2088aqds\0" \
 278         "mcmemsize=0x70000000 \0" \
 279         "scriptaddr=0x80000000\0"               \
 280         "scripthdraddr=0x80080000\0"            \
 281         IFC_MC_INIT_CMD                         \
 282         BOOTENV                                 \
 283         "boot_scripts=ls2088aqds_boot.scr\0"    \
 284         "boot_script_hdr=hdr_ls2088aqds_bs.out\0"       \
 285         "scan_dev_for_boot_part="               \
 286                 "part list ${devtype} ${devnum} devplist; "     \
 287                 "env exists devplist || setenv devplist 1; "    \
 288                 "for distro_bootpart in ${devplist}; do "       \
 289                         "if fstype ${devtype} "                 \
 290                                 "${devnum}:${distro_bootpart} " \
 291                                 "bootfstype; then "             \
 292                                 "run scan_dev_for_boot; "       \
 293                         "fi; "                                  \
 294                 "done\0"                                        \
 295         "boot_a_script="                                        \
 296                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 297                         "${scriptaddr} ${prefix}${script}; "    \
 298                 "env exists secureboot && load ${devtype} "     \
 299                         "${devnum}:${distro_bootpart} "         \
 300                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 301                         "&& esbc_validate ${scripthdraddr};"    \
 302                 "source ${scriptaddr}\0"                        \
 303         "nor_bootcmd=echo Trying load from nor..;"              \
 304                 "cp.b $kernel_addr $load_addr "                 \
 305                 "$kernel_size ; env exists secureboot && "      \
 306                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 307                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 308                 "bootm $load_addr#$BOARD\0"     \
 309         "sd_bootcmd=echo Trying load from SD ..;" \
 310         "mmcinfo; mmc read $load_addr "         \
 311         "$kernel_addr_sd $kernel_size_sd && "   \
 312         "bootm $load_addr#$BOARD\0"
 313 #elif defined(CONFIG_SD_BOOT)
 314 #define CONFIG_EXTRA_ENV_SETTINGS               \
 315         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 316         "loadaddr=0x90100000\0"                 \
 317         "kernel_addr=0x800\0"                \
 318         "ramdisk_addr=0x800000\0"               \
 319         "ramdisk_size=0x2000000\0"              \
 320         "fdt_high=0xa0000000\0"                 \
 321         "initrd_high=0xffffffffffffffff\0"      \
 322         "kernel_start=0x8000\0"              \
 323         "kernel_load=0xa0000000\0"              \
 324         "kernel_size=0x14000\0"               \
 325         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 326         "mmc read 0x80e00000 0x7000 0x800;" \
 327         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 328         "mcmemsize=0x70000000 \0"
 329 #else
 330 #define CONFIG_EXTRA_ENV_SETTINGS               \
 331         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 332         "loadaddr=0x80100000\0"                 \
 333         "kernel_addr=0x100000\0"                \
 334         "ramdisk_addr=0x800000\0"               \
 335         "ramdisk_size=0x2000000\0"              \
 336         "fdt_high=0xa0000000\0"                 \
 337         "initrd_high=0xffffffffffffffff\0"      \
 338         "kernel_start=0x581000000\0"            \
 339         "kernel_load=0xa0000000\0"              \
 340         "kernel_size=0x2800000\0"               \
 341         "mcmemsize=0x40000000\0"                \
 342         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 343         " 0x580e00000 \0"
 344 #endif /* CONFIG_TFABOOT */
 345 #endif /* CONFIG_NXP_ESBC */
 346
 347 #ifdef CONFIG_TFABOOT
 348 #define BOOT_TARGET_DEVICES(func) \
 349         func(USB, usb, 0) \
 350         func(MMC, mmc, 0) \
 351         func(SCSI, scsi, 0) \
 352         func(DHCP, dhcp, na)
 353 #include <config_distro_bootcmd.h>
 354
 355 #define SD_BOOTCOMMAND                                          \
 356                         "env exists mcinitcmd && env exists secureboot "\
 357                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 358                         "&& esbc_validate $load_addr; "                 \
 359                         "env exists mcinitcmd && run mcinitcmd "        \
 360                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 361                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 362                         "run distro_bootcmd;run sd_bootcmd; "           \
 363                         "env exists secureboot && esbc_halt;"
 364
 365 #define IFC_NOR_BOOTCOMMAND                                             \
 366                         "env exists mcinitcmd && env exists secureboot "\
 367                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 368                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 369                         "run distro_bootcmd;run nor_bootcmd; "          \
 370                         "env exists secureboot && esbc_halt;"
 371 #endif
 372
 373 #if defined(CONFIG_FSL_MC_ENET)
 374 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 375 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 376 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 377 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 378
 379 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 380 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 381 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 382 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 383 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 384 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 385 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 386 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 387 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 388 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 389 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 390 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 391 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 392 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 393 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 394 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 395
 396 #endif
 397
 398 #include <asm/fsl_secure_boot.h>
 399
 400 #endif /* __LS2_QDS_H */