1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 2014 Freescale Semiconductor
10 #define CONFIG_REMAKE_ELF
12 #include <asm/arch/stream_id_lsch3.h>
13 #include <asm/arch/config.h>
15 /* Link Definitions */
17 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
22 /* We need architecture specific misc initializations */
24 /* Link Definitions */
26 #ifndef CONFIG_SYS_FSL_DDR4
27 #define CONFIG_SYS_DDR_RAW_TIMING
30 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
32 #define CONFIG_VERY_BIG_RAM
33 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
34 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
35 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
36 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
37 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
42 #define CPU_RELEASE_ADDR secondary_boot_addr
44 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
45 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
46 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
48 * DDR controller use 0 as the base address for binding.
49 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
51 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
52 #define CONFIG_DP_DDR_CTRL 2
53 #define CONFIG_DP_DDR_NUM_CTRLS 1
56 /* Generic Timer Definitions */
58 * This is not an accurate number. It is used in start.S. The frequency
59 * will be udpated later when get_bus_freq(0) is available.
61 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
65 #ifndef CONFIG_MPC8XXX_GPIO
66 #define CONFIG_MPC8XXX_GPIO
73 #define CONFIG_SYS_NS16550_SERIAL
74 #define CONFIG_SYS_NS16550_REG_SIZE 1
75 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
78 * During booting, IFC is mapped at the region of 0x30000000.
79 * But this region is limited to 256MB. To accommodate NOR, promjet
80 * and FPGA. This region is divided as below:
81 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
82 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
83 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
85 * To accommodate bigger NOR flash and other devices, we will map IFC
86 * chip selects to as below:
87 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
88 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
89 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
90 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
91 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
93 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
94 * CONFIG_SYS_FLASH_BASE has the final address (core view)
95 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
96 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
97 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
100 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
101 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
102 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
104 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
105 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
108 unsigned long long get_qixis_addr(void);
110 #define QIXIS_BASE get_qixis_addr()
111 #define QIXIS_BASE_PHYS 0x20000000
112 #define QIXIS_BASE_PHYS_EARLY 0xC000000
113 #define QIXIS_STAT_PRES1 0xb
114 #define QIXIS_SDID_MASK 0x07
115 #define QIXIS_ESDHC_NO_ADAPTER 0x7
117 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
118 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
121 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
122 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
123 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
124 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
125 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
127 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
128 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
130 /* Define phy_reset function to boot the MC based on mcinitcmd.
131 * This happens late enough to properly fixup u-boot env MAC addresses.
133 #define CONFIG_RESET_PHY_R
136 * Carve out a DDR region which will not be used by u-boot/Linux
138 * It will be used by MC and Debug Server. The MC region must be
139 * 512MB aligned, so the min size to hide is 512MB.
141 #ifdef CONFIG_FSL_MC_ENET
142 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
145 /* Miscellaneous configurable options */
147 /* Physical Memory Map */
148 /* fixme: these need to be checked against the board */
149 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
151 #define CONFIG_HWCONFIG
152 #define HWCONFIG_BUFFER_SIZE 128
154 /* Initial environment variables */
155 #define CONFIG_EXTRA_ENV_SETTINGS \
156 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
157 "loadaddr=0x80100000\0" \
158 "kernel_addr=0x100000\0" \
159 "ramdisk_addr=0x800000\0" \
160 "ramdisk_size=0x2000000\0" \
161 "fdt_high=0xa0000000\0" \
162 "initrd_high=0xffffffffffffffff\0" \
163 "kernel_start=0x581000000\0" \
164 "kernel_load=0xa0000000\0" \
165 "kernel_size=0x2800000\0" \
166 "console=ttyAMA0,38400n8\0" \
167 "mcinitcmd=fsl_mc start mc 0x580a00000" \
170 /* Monitor Command Prompt */
171 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
172 #define CONFIG_SYS_MAXARGS 64 /* max command args */
174 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
175 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
176 #define CONFIG_SPL_MAX_SIZE 0x16000
177 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
178 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
180 #ifdef CONFIG_NAND_BOOT
181 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
182 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
184 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
185 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
186 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
188 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
190 #include <asm/arch/soc.h>
192 #endif /* __LS2_COMMON_H */