1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 2014 Freescale Semiconductor
10 #include <asm/arch/stream_id_lsch3.h>
11 #include <asm/arch/config.h>
13 /* Link Definitions */
15 /* We need architecture specific misc initializations */
17 /* Link Definitions */
19 #ifndef CONFIG_SYS_FSL_DDR4
20 #define CONFIG_SYS_DDR_RAW_TIMING
23 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
25 #define CONFIG_VERY_BIG_RAM
26 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
27 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
28 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
29 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
30 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
35 #define CPU_RELEASE_ADDR secondary_boot_addr
37 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
40 * This is not an accurate number. It is used in start.S. The frequency
41 * will be udpated later when get_bus_freq(0) is available.
49 #define CONFIG_SYS_NS16550_SERIAL
50 #define CONFIG_SYS_NS16550_REG_SIZE 1
51 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
54 * During booting, IFC is mapped at the region of 0x30000000.
55 * But this region is limited to 256MB. To accommodate NOR, promjet
56 * and FPGA. This region is divided as below:
57 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
58 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
59 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
61 * To accommodate bigger NOR flash and other devices, we will map IFC
62 * chip selects to as below:
63 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
64 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
65 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
66 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
67 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
69 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
70 * CONFIG_SYS_FLASH_BASE has the final address (core view)
71 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
72 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
73 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
76 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
77 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
78 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
80 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
81 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
84 unsigned long long get_qixis_addr(void);
86 #define QIXIS_BASE get_qixis_addr()
87 #define QIXIS_BASE_PHYS 0x20000000
88 #define QIXIS_BASE_PHYS_EARLY 0xC000000
89 #define QIXIS_STAT_PRES1 0xb
90 #define QIXIS_SDID_MASK 0x07
91 #define QIXIS_ESDHC_NO_ADAPTER 0x7
93 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
94 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
97 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
98 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
99 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
100 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
101 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
103 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
104 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
107 * Carve out a DDR region which will not be used by u-boot/Linux
109 * It will be used by MC and Debug Server. The MC region must be
110 * 512MB aligned, so the min size to hide is 512MB.
112 #ifdef CONFIG_FSL_MC_ENET
113 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
116 /* Miscellaneous configurable options */
118 /* Physical Memory Map */
119 /* fixme: these need to be checked against the board */
121 #define CONFIG_HWCONFIG
122 #define HWCONFIG_BUFFER_SIZE 128
124 /* Initial environment variables */
125 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
127 "loadaddr=0x80100000\0" \
128 "kernel_addr=0x100000\0" \
129 "ramdisk_addr=0x800000\0" \
130 "ramdisk_size=0x2000000\0" \
131 "fdt_high=0xa0000000\0" \
132 "initrd_high=0xffffffffffffffff\0" \
133 "kernel_start=0x581000000\0" \
134 "kernel_load=0xa0000000\0" \
135 "kernel_size=0x2800000\0" \
136 "console=ttyAMA0,38400n8\0" \
137 "mcinitcmd=fsl_mc start mc 0x580a00000" \
140 #ifdef CONFIG_NAND_BOOT
141 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
142 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
144 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
146 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
148 #include <asm/arch/soc.h>
150 #endif /* __LS2_COMMON_H */