1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 2014 Freescale Semiconductor
10 #include <asm/arch/stream_id_lsch3.h>
11 #include <asm/arch/config.h>
13 /* Link Definitions */
15 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
17 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
20 /* We need architecture specific misc initializations */
22 /* Link Definitions */
24 #ifndef CONFIG_SYS_FSL_DDR4
25 #define CONFIG_SYS_DDR_RAW_TIMING
28 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
30 #define CONFIG_VERY_BIG_RAM
31 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
32 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
33 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
34 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
35 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
40 #define CPU_RELEASE_ADDR secondary_boot_addr
42 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
43 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
44 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
46 * DDR controller use 0 as the base address for binding.
47 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
49 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
50 #define CONFIG_DP_DDR_CTRL 2
51 #define CONFIG_DP_DDR_NUM_CTRLS 1
54 /* Generic Timer Definitions */
56 * This is not an accurate number. It is used in start.S. The frequency
57 * will be udpated later when get_bus_freq(0) is available.
59 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
66 #define CONFIG_SYS_NS16550_SERIAL
67 #define CONFIG_SYS_NS16550_REG_SIZE 1
68 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
71 * During booting, IFC is mapped at the region of 0x30000000.
72 * But this region is limited to 256MB. To accommodate NOR, promjet
73 * and FPGA. This region is divided as below:
74 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
75 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
76 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
78 * To accommodate bigger NOR flash and other devices, we will map IFC
79 * chip selects to as below:
80 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
81 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
82 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
83 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
84 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
86 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
87 * CONFIG_SYS_FLASH_BASE has the final address (core view)
88 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
89 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
90 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
93 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
94 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
95 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
97 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
98 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
101 unsigned long long get_qixis_addr(void);
103 #define QIXIS_BASE get_qixis_addr()
104 #define QIXIS_BASE_PHYS 0x20000000
105 #define QIXIS_BASE_PHYS_EARLY 0xC000000
106 #define QIXIS_STAT_PRES1 0xb
107 #define QIXIS_SDID_MASK 0x07
108 #define QIXIS_ESDHC_NO_ADAPTER 0x7
110 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
111 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
114 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
115 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
116 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
117 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
118 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
120 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
121 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
123 /* Define phy_reset function to boot the MC based on mcinitcmd.
124 * This happens late enough to properly fixup u-boot env MAC addresses.
126 #define CONFIG_RESET_PHY_R
129 * Carve out a DDR region which will not be used by u-boot/Linux
131 * It will be used by MC and Debug Server. The MC region must be
132 * 512MB aligned, so the min size to hide is 512MB.
134 #ifdef CONFIG_FSL_MC_ENET
135 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
138 /* Miscellaneous configurable options */
140 /* Physical Memory Map */
141 /* fixme: these need to be checked against the board */
142 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
144 #define CONFIG_HWCONFIG
145 #define HWCONFIG_BUFFER_SIZE 128
147 /* Initial environment variables */
148 #define CONFIG_EXTRA_ENV_SETTINGS \
149 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
150 "loadaddr=0x80100000\0" \
151 "kernel_addr=0x100000\0" \
152 "ramdisk_addr=0x800000\0" \
153 "ramdisk_size=0x2000000\0" \
154 "fdt_high=0xa0000000\0" \
155 "initrd_high=0xffffffffffffffff\0" \
156 "kernel_start=0x581000000\0" \
157 "kernel_load=0xa0000000\0" \
158 "kernel_size=0x2800000\0" \
159 "console=ttyAMA0,38400n8\0" \
160 "mcinitcmd=fsl_mc start mc 0x580a00000" \
163 /* Monitor Command Prompt */
164 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
165 #define CONFIG_SYS_MAXARGS 64 /* max command args */
167 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
168 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
169 #define CONFIG_SPL_MAX_SIZE 0x16000
170 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
171 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
173 #ifdef CONFIG_NAND_BOOT
174 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
175 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
177 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
178 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
179 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
181 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
183 #include <asm/arch/soc.h>
185 #endif /* __LS2_COMMON_H */