1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 2014 Freescale Semiconductor
10 #include <asm/arch/stream_id_lsch3.h>
11 #include <asm/arch/config.h>
13 /* Link Definitions */
15 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
17 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
20 /* We need architecture specific misc initializations */
22 /* Link Definitions */
24 #ifndef CONFIG_SYS_FSL_DDR4
25 #define CONFIG_SYS_DDR_RAW_TIMING
28 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
30 #define CONFIG_VERY_BIG_RAM
31 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
32 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
33 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
34 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
35 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
40 #define CPU_RELEASE_ADDR secondary_boot_addr
42 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
44 /* Generic Timer Definitions */
46 * This is not an accurate number. It is used in start.S. The frequency
47 * will be udpated later when get_bus_freq(0) is available.
49 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
56 #define CONFIG_SYS_NS16550_SERIAL
57 #define CONFIG_SYS_NS16550_REG_SIZE 1
58 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
61 * During booting, IFC is mapped at the region of 0x30000000.
62 * But this region is limited to 256MB. To accommodate NOR, promjet
63 * and FPGA. This region is divided as below:
64 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
65 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
66 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
68 * To accommodate bigger NOR flash and other devices, we will map IFC
69 * chip selects to as below:
70 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
71 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
72 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
73 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
74 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
76 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
77 * CONFIG_SYS_FLASH_BASE has the final address (core view)
78 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
79 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
80 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
83 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
84 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
85 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
87 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
88 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
91 unsigned long long get_qixis_addr(void);
93 #define QIXIS_BASE get_qixis_addr()
94 #define QIXIS_BASE_PHYS 0x20000000
95 #define QIXIS_BASE_PHYS_EARLY 0xC000000
96 #define QIXIS_STAT_PRES1 0xb
97 #define QIXIS_SDID_MASK 0x07
98 #define QIXIS_ESDHC_NO_ADAPTER 0x7
100 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
101 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
104 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
105 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
106 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
107 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
108 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
110 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
111 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
114 * Carve out a DDR region which will not be used by u-boot/Linux
116 * It will be used by MC and Debug Server. The MC region must be
117 * 512MB aligned, so the min size to hide is 512MB.
119 #ifdef CONFIG_FSL_MC_ENET
120 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
123 /* Miscellaneous configurable options */
125 /* Physical Memory Map */
126 /* fixme: these need to be checked against the board */
128 #define CONFIG_HWCONFIG
129 #define HWCONFIG_BUFFER_SIZE 128
131 /* Initial environment variables */
132 #define CONFIG_EXTRA_ENV_SETTINGS \
133 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
134 "loadaddr=0x80100000\0" \
135 "kernel_addr=0x100000\0" \
136 "ramdisk_addr=0x800000\0" \
137 "ramdisk_size=0x2000000\0" \
138 "fdt_high=0xa0000000\0" \
139 "initrd_high=0xffffffffffffffff\0" \
140 "kernel_start=0x581000000\0" \
141 "kernel_load=0xa0000000\0" \
142 "kernel_size=0x2800000\0" \
143 "console=ttyAMA0,38400n8\0" \
144 "mcinitcmd=fsl_mc start mc 0x580a00000" \
147 /* Monitor Command Prompt */
148 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
149 #define CONFIG_SYS_MAXARGS 64 /* max command args */
151 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
152 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
153 #define CONFIG_SPL_MAX_SIZE 0x16000
154 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
155 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
157 #ifdef CONFIG_NAND_BOOT
158 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
159 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
161 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
162 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
163 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
165 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
167 #include <asm/arch/soc.h>
169 #endif /* __LS2_COMMON_H */