1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_CLK_FREQ 100000000
20 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
21 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
23 #define CONFIG_DDR_SPD
25 #define CONFIG_SYS_FSL_DDR_EMU
27 #define CONFIG_DDR_ECC
28 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
29 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
31 #define SPD_EEPROM_ADDRESS 0x51
32 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
33 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
36 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
37 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
38 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
39 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
41 #define CONFIG_SYS_NOR0_CSPR \
42 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
46 #define CONFIG_SYS_NOR0_CSPR_EARLY \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
51 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
52 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
53 FTIM0_NOR_TEADC(0x1) | \
55 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
56 FTIM1_NOR_TRAD_NOR(0x1))
57 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
58 FTIM2_NOR_TCH(0x0) | \
60 #define CONFIG_SYS_NOR_FTIM3 0x04000000
61 #define CONFIG_SYS_IFC_CCR 0x01000000
64 #define CONFIG_SYS_FLASH_QUIET_TEST
65 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
67 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
68 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
69 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
70 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
72 #define CONFIG_SYS_FLASH_EMPTY_INFO
73 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
78 #define CONFIG_NAND_FSL_IFC
81 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
82 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
84 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
85 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
86 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
87 | CSPR_MSEL_NAND /* MSEL = NAND */ \
89 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
91 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
92 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
93 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
94 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
95 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
96 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
97 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
99 #define CONFIG_SYS_NAND_ONFI_DETECTION
101 /* ONFI NAND Flash mode0 Timing Params */
102 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
103 FTIM0_NAND_TWP(0x18) | \
104 FTIM0_NAND_TWCHT(0x07) | \
105 FTIM0_NAND_TWH(0x0a))
106 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
107 FTIM1_NAND_TWBE(0x39) | \
108 FTIM1_NAND_TRR(0x0e) | \
109 FTIM1_NAND_TRP(0x18))
110 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
111 FTIM2_NAND_TREH(0x0a) | \
112 FTIM2_NAND_TWHRE(0x1e))
113 #define CONFIG_SYS_NAND_FTIM3 0x0
115 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
116 #define CONFIG_SYS_MAX_NAND_DEVICE 1
117 #define CONFIG_MTD_NAND_VERIFY_WRITE
119 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
122 #define CONFIG_FSL_QIXIS
125 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
126 #define QIXIS_BRDCFG4_OFFSET 0x54
127 #define QIXIS_LBMAP_SWITCH 2
128 #define QIXIS_QMAP_MASK 0xe0
129 #define QIXIS_QMAP_SHIFT 5
130 #define QIXIS_LBMAP_MASK 0x1f
131 #define QIXIS_LBMAP_SHIFT 5
132 #define QIXIS_LBMAP_DFLTBANK 0x00
133 #define QIXIS_LBMAP_ALTBANK 0x20
134 #define QIXIS_LBMAP_SD 0x00
135 #define QIXIS_LBMAP_EMMC 0x00
136 #define QIXIS_LBMAP_SD_QSPI 0x00
137 #define QIXIS_LBMAP_QSPI 0x00
138 #define QIXIS_RCW_SRC_SD 0x40
139 #define QIXIS_RCW_SRC_EMMC 0x41
140 #define QIXIS_RCW_SRC_QSPI 0x62
141 #define QIXIS_RST_CTL_RESET 0x31
142 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
143 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
144 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
145 #define QIXIS_RST_FORCE_MEM 0x01
147 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
148 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
152 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
157 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
158 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
159 /* QIXIS Timing parameters*/
160 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
161 FTIM0_GPCM_TEADC(0x0e) | \
162 FTIM0_GPCM_TEAHC(0x0e))
163 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
164 FTIM1_GPCM_TRAD(0x3f))
165 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
166 FTIM2_GPCM_TCH(0xf) | \
167 FTIM2_GPCM_TWP(0x3E))
168 #define SYS_FPGA_CS_FTIM3 0x0
170 #if defined(CONFIG_TFABOOT) || \
171 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
172 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
173 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
174 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
175 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
176 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
177 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
178 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
179 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
180 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
181 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
182 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
183 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
184 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
185 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
186 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
187 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
188 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
190 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
191 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
192 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
193 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
194 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
195 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
196 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
197 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
198 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
201 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
203 #define I2C_MUX_CH_VOL_MONITOR 0xA
204 /* Voltage monitor on channel 2*/
205 #define I2C_VOL_MONITOR_ADDR 0x63
206 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
207 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
208 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
209 #define I2C_SVDD_MONITOR_ADDR 0x4F
211 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
214 /* The lowest and highest voltage allowed for LS1088ARDB */
215 #define VDD_MV_MIN 819
216 #define VDD_MV_MAX 1212
218 #define CONFIG_VOL_MONITOR_LTC3882_SET
219 #define CONFIG_VOL_MONITOR_LTC3882_READ
221 #define PWM_CHANNEL0 0x0
224 * I2C bus multiplexer
226 #define I2C_MUX_PCA_ADDR_PRI 0x77
227 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
228 #define I2C_RETIMER_ADDR 0x18
229 #define I2C_MUX_CH_DEFAULT 0x8
230 #define I2C_MUX_CH5 0xD
237 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
241 #define CONFIG_SYS_I2C_EEPROM_NXID
242 #define CONFIG_SYS_EEPROM_BUS_NUM 0
244 #ifdef CONFIG_SPL_BUILD
245 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
247 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
250 #define CONFIG_FSL_MEMAC
253 /* Initial environment variables */
254 #ifdef CONFIG_TFABOOT
255 #define QSPI_MC_INIT_CMD \
256 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
257 "sf read 0x80e00000 0xE00000 0x100000;" \
258 "env exists secureboot && " \
259 "sf read 0x80640000 0x640000 0x40000 && " \
260 "sf read 0x80680000 0x680000 0x40000 && " \
261 "esbc_validate 0x80640000 && " \
262 "esbc_validate 0x80680000 ;" \
263 "fsl_mc start mc 0x80a00000 0x80e00000\0"
264 #define SD_MC_INIT_CMD \
265 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
266 "mmc read 0x80e00000 0x7000 0x800;" \
267 "env exists secureboot && " \
268 "mmc read 0x80640000 0x3200 0x20 && " \
269 "mmc read 0x80680000 0x3400 0x20 && " \
270 "esbc_validate 0x80640000 && " \
271 "esbc_validate 0x80680000 ;" \
272 "fsl_mc start mc 0x80a00000 0x80e00000\0"
274 #if defined(CONFIG_QSPI_BOOT)
275 #define MC_INIT_CMD \
276 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
277 "sf read 0x80e00000 0xE00000 0x100000;" \
278 "env exists secureboot && " \
279 "sf read 0x80640000 0x640000 0x40000 && " \
280 "sf read 0x80680000 0x680000 0x40000 && " \
281 "esbc_validate 0x80640000 && " \
282 "esbc_validate 0x80680000 ;" \
283 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
284 "mcmemsize=0x70000000\0"
285 #elif defined(CONFIG_SD_BOOT)
286 #define MC_INIT_CMD \
287 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
288 "mmc read 0x80e00000 0x7000 0x800;" \
289 "env exists secureboot && " \
290 "mmc read 0x80640000 0x3200 0x20 && " \
291 "mmc read 0x80680000 0x3400 0x20 && " \
292 "esbc_validate 0x80640000 && " \
293 "esbc_validate 0x80680000 ;" \
294 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
295 "mcmemsize=0x70000000\0"
297 #endif /* CONFIG_TFABOOT */
299 #undef CONFIG_EXTRA_ENV_SETTINGS
300 #ifdef CONFIG_TFABOOT
301 #define CONFIG_EXTRA_ENV_SETTINGS \
302 "BOARD=ls1088ardb\0" \
303 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
304 "ramdisk_addr=0x800000\0" \
305 "ramdisk_size=0x2000000\0" \
306 "fdt_high=0xa0000000\0" \
307 "initrd_high=0xffffffffffffffff\0" \
308 "fdt_addr=0x64f00000\0" \
309 "kernel_addr=0x1000000\0" \
310 "kernel_addr_sd=0x8000\0" \
311 "kernelhdr_addr_sd=0x3000\0" \
312 "kernel_start=0x580100000\0" \
313 "kernelheader_start=0x580600000\0" \
314 "scriptaddr=0x80000000\0" \
315 "scripthdraddr=0x80080000\0" \
316 "fdtheader_addr_r=0x80100000\0" \
317 "kernelheader_addr=0x600000\0" \
318 "kernelheader_addr_r=0x80200000\0" \
319 "kernel_addr_r=0x81000000\0" \
320 "kernelheader_size=0x40000\0" \
321 "fdt_addr_r=0x90000000\0" \
322 "load_addr=0xa0000000\0" \
323 "kernel_size=0x2800000\0" \
324 "kernel_size_sd=0x14000\0" \
325 "kernelhdr_size_sd=0x20\0" \
327 "mcmemsize=0x70000000\0" \
329 "boot_scripts=ls1088ardb_boot.scr\0" \
330 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
331 "scan_dev_for_boot_part=" \
332 "part list ${devtype} ${devnum} devplist; " \
333 "env exists devplist || setenv devplist 1; " \
334 "for distro_bootpart in ${devplist}; do " \
335 "if fstype ${devtype} " \
336 "${devnum}:${distro_bootpart} " \
337 "bootfstype; then " \
338 "run scan_dev_for_boot; " \
342 "load ${devtype} ${devnum}:${distro_bootpart} " \
343 "${scriptaddr} ${prefix}${script}; " \
344 "env exists secureboot && load ${devtype} " \
345 "${devnum}:${distro_bootpart} " \
346 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
347 "env exists secureboot " \
348 "&& esbc_validate ${scripthdraddr};" \
349 "source ${scriptaddr}\0" \
350 "installer=load mmc 0:2 $load_addr " \
351 "/flex_installer_arm64.itb; " \
352 "env exists mcinitcmd && run mcinitcmd && " \
353 "mmc read 0x80001000 0x6800 0x800;" \
354 "fsl_mc lazyapply dpl 0x80001000;" \
355 "bootm $load_addr#ls1088ardb\0" \
356 "qspi_bootcmd=echo Trying load from qspi..;" \
357 "sf probe && sf read $load_addr " \
358 "$kernel_addr $kernel_size ; env exists secureboot " \
359 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
360 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
361 "bootm $load_addr#$BOARD\0" \
362 "sd_bootcmd=echo Trying load from sd card..;" \
363 "mmcinfo; mmc read $load_addr " \
364 "$kernel_addr_sd $kernel_size_sd ;" \
365 "env exists secureboot && mmc read $kernelheader_addr_r "\
366 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
367 " && esbc_validate ${kernelheader_addr_r};" \
368 "bootm $load_addr#$BOARD\0"
370 #define CONFIG_EXTRA_ENV_SETTINGS \
371 "BOARD=ls1088ardb\0" \
372 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
373 "ramdisk_addr=0x800000\0" \
374 "ramdisk_size=0x2000000\0" \
375 "fdt_high=0xa0000000\0" \
376 "initrd_high=0xffffffffffffffff\0" \
377 "fdt_addr=0x64f00000\0" \
378 "kernel_addr=0x1000000\0" \
379 "kernel_addr_sd=0x8000\0" \
380 "kernelhdr_addr_sd=0x3000\0" \
381 "kernel_start=0x580100000\0" \
382 "kernelheader_start=0x580800000\0" \
383 "scriptaddr=0x80000000\0" \
384 "scripthdraddr=0x80080000\0" \
385 "fdtheader_addr_r=0x80100000\0" \
386 "kernelheader_addr=0x600000\0" \
387 "kernelheader_addr_r=0x80200000\0" \
388 "kernel_addr_r=0x81000000\0" \
389 "kernelheader_size=0x40000\0" \
390 "fdt_addr_r=0x90000000\0" \
391 "load_addr=0xa0000000\0" \
392 "kernel_size=0x2800000\0" \
393 "kernel_size_sd=0x14000\0" \
394 "kernelhdr_size_sd=0x20\0" \
397 "boot_scripts=ls1088ardb_boot.scr\0" \
398 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
399 "scan_dev_for_boot_part=" \
400 "part list ${devtype} ${devnum} devplist; " \
401 "env exists devplist || setenv devplist 1; " \
402 "for distro_bootpart in ${devplist}; do " \
403 "if fstype ${devtype} " \
404 "${devnum}:${distro_bootpart} " \
405 "bootfstype; then " \
406 "run scan_dev_for_boot; " \
410 "load ${devtype} ${devnum}:${distro_bootpart} " \
411 "${scriptaddr} ${prefix}${script}; " \
412 "env exists secureboot && load ${devtype} " \
413 "${devnum}:${distro_bootpart} " \
414 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
415 "&& esbc_validate ${scripthdraddr};" \
416 "source ${scriptaddr}\0" \
417 "installer=load mmc 0:2 $load_addr " \
418 "/flex_installer_arm64.itb; " \
419 "env exists mcinitcmd && run mcinitcmd && " \
420 "mmc read 0x80001000 0x6800 0x800;" \
421 "fsl_mc lazyapply dpl 0x80001000;" \
422 "bootm $load_addr#ls1088ardb\0" \
423 "qspi_bootcmd=echo Trying load from qspi..;" \
424 "sf probe && sf read $load_addr " \
425 "$kernel_addr $kernel_size ; env exists secureboot " \
426 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
427 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
428 "bootm $load_addr#$BOARD\0" \
429 "sd_bootcmd=echo Trying load from sd card..;" \
430 "mmcinfo; mmc read $load_addr " \
431 "$kernel_addr_sd $kernel_size_sd ;" \
432 "env exists secureboot && mmc read $kernelheader_addr_r "\
433 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
434 " && esbc_validate ${kernelheader_addr_r};" \
435 "bootm $load_addr#$BOARD\0"
436 #endif /* CONFIG_TFABOOT */
438 #undef CONFIG_BOOTCOMMAND
439 #ifdef CONFIG_TFABOOT
440 #define QSPI_NOR_BOOTCOMMAND \
441 "sf read 0x80001000 0xd00000 0x100000;" \
442 "env exists mcinitcmd && env exists secureboot " \
443 " && sf read 0x806C0000 0x6C0000 0x100000 " \
444 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
445 "&& fsl_mc lazyapply dpl 0x80001000;" \
446 "run distro_bootcmd;run qspi_bootcmd;" \
447 "env exists secureboot && esbc_halt;"
448 #define SD_BOOTCOMMAND \
449 "env exists mcinitcmd && mmcinfo; " \
450 "mmc read 0x80001000 0x6800 0x800; " \
451 "env exists mcinitcmd && env exists secureboot " \
452 " && mmc read 0x806C0000 0x3600 0x20 " \
453 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
454 "&& fsl_mc lazyapply dpl 0x80001000;" \
455 "run distro_bootcmd;run sd_bootcmd;" \
456 "env exists secureboot && esbc_halt;"
458 #if defined(CONFIG_QSPI_BOOT)
459 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
460 #define CONFIG_BOOTCOMMAND \
461 "sf read 0x80001000 0xd00000 0x100000;" \
462 "env exists mcinitcmd && env exists secureboot " \
463 " && sf read 0x806C0000 0x6C0000 0x100000 " \
464 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
465 "&& fsl_mc lazyapply dpl 0x80001000;" \
466 "run distro_bootcmd;run qspi_bootcmd;" \
467 "env exists secureboot && esbc_halt;"
469 /* Try to boot an on-SD kernel first, then do normal distro boot */
470 #elif defined(CONFIG_SD_BOOT)
471 #define CONFIG_BOOTCOMMAND \
472 "env exists mcinitcmd && mmcinfo; " \
473 "mmc read 0x80001000 0x6800 0x800; " \
474 "env exists mcinitcmd && env exists secureboot " \
475 " && mmc read 0x806C0000 0x3600 0x20 " \
476 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
477 "&& fsl_mc lazyapply dpl 0x80001000;" \
478 "run distro_bootcmd;run sd_bootcmd;" \
479 "env exists secureboot && esbc_halt;"
481 #endif /* CONFIG_TFABOOT */
483 /* MAC/PHY configuration */
484 #ifdef CONFIG_FSL_MC_ENET
485 #define AQ_PHY_ADDR1 0x00
486 #define AQR105_IRQ_MASK 0x00000004
488 #define QSGMII1_PORT1_PHY_ADDR 0x0c
489 #define QSGMII1_PORT2_PHY_ADDR 0x0d
490 #define QSGMII1_PORT3_PHY_ADDR 0x0e
491 #define QSGMII1_PORT4_PHY_ADDR 0x0f
492 #define QSGMII2_PORT1_PHY_ADDR 0x1c
493 #define QSGMII2_PORT2_PHY_ADDR 0x1d
494 #define QSGMII2_PORT3_PHY_ADDR 0x1e
495 #define QSGMII2_PORT4_PHY_ADDR 0x1f
497 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
498 #define CONFIG_PHY_GIGE
504 #define BOOT_TARGET_DEVICES(func) \
507 func(SCSI, scsi, 0) \
509 #include <config_distro_bootcmd.h>
512 #include <asm/fsl_secure_boot.h>
514 #endif /* __LS1088A_RDB_H */