1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #define CONFIG_SYS_MMC_ENV_DEV 0
13 #if defined(CONFIG_TFABOOT) || \
14 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
15 #ifndef CONFIG_SPL_BUILD
16 #define CONFIG_QIXIS_I2C_ACCESS
21 #define CONFIG_SYS_CLK_FREQ 100000000
22 #define CONFIG_DDR_CLK_FREQ 100000000
23 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
24 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
26 #define CONFIG_DDR_SPD
28 #define CONFIG_SYS_FSL_DDR_EMU
29 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
30 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
32 #define CONFIG_DDR_ECC
33 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
36 #define SPD_EEPROM_ADDRESS 0x51
37 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
38 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
41 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
42 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
43 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
44 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
46 #define CONFIG_SYS_NOR0_CSPR \
47 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
51 #define CONFIG_SYS_NOR0_CSPR_EARLY \
52 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
56 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
57 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
58 FTIM0_NOR_TEADC(0x1) | \
60 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
61 FTIM1_NOR_TRAD_NOR(0x1))
62 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
63 FTIM2_NOR_TCH(0x0) | \
65 #define CONFIG_SYS_NOR_FTIM3 0x04000000
66 #define CONFIG_SYS_IFC_CCR 0x01000000
69 #define CONFIG_SYS_FLASH_QUIET_TEST
70 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
72 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
73 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
74 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
75 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
77 #define CONFIG_SYS_FLASH_EMPTY_INFO
78 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
83 #define CONFIG_NAND_FSL_IFC
86 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
87 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
89 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
90 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
91 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
92 | CSPR_MSEL_NAND /* MSEL = NAND */ \
94 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
96 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
97 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
98 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
99 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
100 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
101 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
102 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
104 #define CONFIG_SYS_NAND_ONFI_DETECTION
106 /* ONFI NAND Flash mode0 Timing Params */
107 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
108 FTIM0_NAND_TWP(0x18) | \
109 FTIM0_NAND_TWCHT(0x07) | \
110 FTIM0_NAND_TWH(0x0a))
111 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
112 FTIM1_NAND_TWBE(0x39) | \
113 FTIM1_NAND_TRR(0x0e) | \
114 FTIM1_NAND_TRP(0x18))
115 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
116 FTIM2_NAND_TREH(0x0a) | \
117 FTIM2_NAND_TWHRE(0x1e))
118 #define CONFIG_SYS_NAND_FTIM3 0x0
120 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
121 #define CONFIG_SYS_MAX_NAND_DEVICE 1
122 #define CONFIG_MTD_NAND_VERIFY_WRITE
124 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
127 #define CONFIG_FSL_QIXIS
130 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
131 #define QIXIS_BRDCFG4_OFFSET 0x54
132 #define QIXIS_LBMAP_SWITCH 2
133 #define QIXIS_QMAP_MASK 0xe0
134 #define QIXIS_QMAP_SHIFT 5
135 #define QIXIS_LBMAP_MASK 0x1f
136 #define QIXIS_LBMAP_SHIFT 5
137 #define QIXIS_LBMAP_DFLTBANK 0x00
138 #define QIXIS_LBMAP_ALTBANK 0x20
139 #define QIXIS_LBMAP_SD 0x00
140 #define QIXIS_LBMAP_EMMC 0x00
141 #define QIXIS_LBMAP_SD_QSPI 0x00
142 #define QIXIS_LBMAP_QSPI 0x00
143 #define QIXIS_RCW_SRC_SD 0x40
144 #define QIXIS_RCW_SRC_EMMC 0x41
145 #define QIXIS_RCW_SRC_QSPI 0x62
146 #define QIXIS_RST_CTL_RESET 0x31
147 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
148 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
149 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
150 #define QIXIS_RST_FORCE_MEM 0x01
152 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
153 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
157 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
162 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
163 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
164 /* QIXIS Timing parameters*/
165 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
166 FTIM0_GPCM_TEADC(0x0e) | \
167 FTIM0_GPCM_TEAHC(0x0e))
168 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
169 FTIM1_GPCM_TRAD(0x3f))
170 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
171 FTIM2_GPCM_TCH(0xf) | \
172 FTIM2_GPCM_TWP(0x3E))
173 #define SYS_FPGA_CS_FTIM3 0x0
175 #if defined(CONFIG_TFABOOT) || \
176 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
177 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
178 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
179 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
180 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
181 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
182 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
183 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
184 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
185 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
186 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
187 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
188 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
189 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
190 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
191 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
192 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
193 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
195 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
196 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
197 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
198 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
199 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
200 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
201 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
202 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
203 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
206 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
208 #define I2C_MUX_CH_VOL_MONITOR 0xA
209 /* Voltage monitor on channel 2*/
210 #define I2C_VOL_MONITOR_ADDR 0x63
211 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
212 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
213 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
214 #define I2C_SVDD_MONITOR_ADDR 0x4F
216 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
219 /* The lowest and highest voltage allowed for LS1088ARDB */
220 #define VDD_MV_MIN 819
221 #define VDD_MV_MAX 1212
223 #define CONFIG_VOL_MONITOR_LTC3882_SET
224 #define CONFIG_VOL_MONITOR_LTC3882_READ
226 /* PM Bus commands code for LTC3882*/
227 #define PMBUS_CMD_PAGE 0x0
228 #define PMBUS_CMD_READ_VOUT 0x8B
229 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
230 #define PMBUS_CMD_VOUT_COMMAND 0x21
232 #define PWM_CHANNEL0 0x0
235 * I2C bus multiplexer
237 #define I2C_MUX_PCA_ADDR_PRI 0x77
238 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
239 #define I2C_RETIMER_ADDR 0x18
240 #define I2C_MUX_CH_DEFAULT 0x8
241 #define I2C_MUX_CH5 0xD
248 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
252 #define CONFIG_ID_EEPROM
253 #define CONFIG_SYS_I2C_EEPROM_NXID
254 #define CONFIG_SYS_EEPROM_BUS_NUM 0
255 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
256 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
257 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
260 #ifdef CONFIG_SPL_BUILD
261 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
266 #define CONFIG_FSL_MEMAC
269 /* Initial environment variables */
270 #ifdef CONFIG_TFABOOT
271 #define QSPI_MC_INIT_CMD \
272 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
273 "sf read 0x80100000 0xE00000 0x100000;" \
274 "env exists secureboot && " \
275 "sf read 0x80640000 0x640000 0x40000 && " \
276 "sf read 0x80680000 0x680000 0x40000 && " \
277 "esbc_validate 0x80640000 && " \
278 "esbc_validate 0x80680000 ;" \
279 "fsl_mc start mc 0x80000000 0x80100000\0"
280 #define SD_MC_INIT_CMD \
281 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
282 "mmc read 0x80100000 0x7000 0x800;" \
283 "env exists secureboot && " \
284 "mmc read 0x80640000 0x3200 0x20 && " \
285 "mmc read 0x80680000 0x3400 0x20 && " \
286 "esbc_validate 0x80640000 && " \
287 "esbc_validate 0x80680000 ;" \
288 "fsl_mc start mc 0x80000000 0x80100000\0"
290 #if defined(CONFIG_QSPI_BOOT)
291 #define MC_INIT_CMD \
292 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
293 "sf read 0x80100000 0xE00000 0x100000;" \
294 "env exists secureboot && " \
295 "sf read 0x80640000 0x640000 0x40000 && " \
296 "sf read 0x80680000 0x680000 0x40000 && " \
297 "esbc_validate 0x80640000 && " \
298 "esbc_validate 0x80680000 ;" \
299 "fsl_mc start mc 0x80000000 0x80100000\0" \
300 "mcmemsize=0x70000000\0"
301 #elif defined(CONFIG_SD_BOOT)
302 #define MC_INIT_CMD \
303 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
304 "mmc read 0x80100000 0x7000 0x800;" \
305 "env exists secureboot && " \
306 "mmc read 0x80640000 0x3200 0x20 && " \
307 "mmc read 0x80680000 0x3400 0x20 && " \
308 "esbc_validate 0x80640000 && " \
309 "esbc_validate 0x80680000 ;" \
310 "fsl_mc start mc 0x80000000 0x80100000\0" \
311 "mcmemsize=0x70000000\0"
313 #endif /* CONFIG_TFABOOT */
315 #undef CONFIG_EXTRA_ENV_SETTINGS
316 #ifdef CONFIG_TFABOOT
317 #define CONFIG_EXTRA_ENV_SETTINGS \
318 "BOARD=ls1088ardb\0" \
319 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
320 "ramdisk_addr=0x800000\0" \
321 "ramdisk_size=0x2000000\0" \
322 "fdt_high=0xa0000000\0" \
323 "initrd_high=0xffffffffffffffff\0" \
324 "fdt_addr=0x64f00000\0" \
325 "kernel_addr=0x1000000\0" \
326 "kernel_addr_sd=0x8000\0" \
327 "kernelhdr_addr_sd=0x3000\0" \
328 "kernel_start=0x580100000\0" \
329 "kernelheader_start=0x580600000\0" \
330 "scriptaddr=0x80000000\0" \
331 "scripthdraddr=0x80080000\0" \
332 "fdtheader_addr_r=0x80100000\0" \
333 "kernelheader_addr=0x600000\0" \
334 "kernelheader_addr_r=0x80200000\0" \
335 "kernel_addr_r=0x81000000\0" \
336 "kernelheader_size=0x40000\0" \
337 "fdt_addr_r=0x90000000\0" \
338 "load_addr=0xa0000000\0" \
339 "kernel_size=0x2800000\0" \
340 "kernel_size_sd=0x14000\0" \
341 "kernelhdr_size_sd=0x20\0" \
343 "mcmemsize=0x70000000\0" \
345 "boot_scripts=ls1088ardb_boot.scr\0" \
346 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
347 "scan_dev_for_boot_part=" \
348 "part list ${devtype} ${devnum} devplist; " \
349 "env exists devplist || setenv devplist 1; " \
350 "for distro_bootpart in ${devplist}; do " \
351 "if fstype ${devtype} " \
352 "${devnum}:${distro_bootpart} " \
353 "bootfstype; then " \
354 "run scan_dev_for_boot; " \
358 "load ${devtype} ${devnum}:${distro_bootpart} " \
359 "${scriptaddr} ${prefix}${script}; " \
360 "env exists secureboot && load ${devtype} " \
361 "${devnum}:${distro_bootpart} " \
362 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
363 "env exists secureboot " \
364 "&& esbc_validate ${scripthdraddr};" \
365 "source ${scriptaddr}\0" \
366 "installer=load mmc 0:2 $load_addr " \
367 "/flex_installer_arm64.itb; " \
368 "env exists mcinitcmd && run mcinitcmd && " \
369 "mmc read 0x80001000 0x6800 0x800;" \
370 "fsl_mc lazyapply dpl 0x80001000;" \
371 "bootm $load_addr#ls1088ardb\0" \
372 "qspi_bootcmd=echo Trying load from qspi..;" \
373 "sf probe && sf read $load_addr " \
374 "$kernel_addr $kernel_size ; env exists secureboot " \
375 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
376 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
377 "bootm $load_addr#$BOARD\0" \
378 "sd_bootcmd=echo Trying load from sd card..;" \
379 "mmcinfo; mmc read $load_addr " \
380 "$kernel_addr_sd $kernel_size_sd ;" \
381 "env exists secureboot && mmc read $kernelheader_addr_r "\
382 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
383 " && esbc_validate ${kernelheader_addr_r};" \
384 "bootm $load_addr#$BOARD\0"
386 #define CONFIG_EXTRA_ENV_SETTINGS \
387 "BOARD=ls1088ardb\0" \
388 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
389 "ramdisk_addr=0x800000\0" \
390 "ramdisk_size=0x2000000\0" \
391 "fdt_high=0xa0000000\0" \
392 "initrd_high=0xffffffffffffffff\0" \
393 "fdt_addr=0x64f00000\0" \
394 "kernel_addr=0x1000000\0" \
395 "kernel_addr_sd=0x8000\0" \
396 "kernelhdr_addr_sd=0x3000\0" \
397 "kernel_start=0x580100000\0" \
398 "kernelheader_start=0x580800000\0" \
399 "scriptaddr=0x80000000\0" \
400 "scripthdraddr=0x80080000\0" \
401 "fdtheader_addr_r=0x80100000\0" \
402 "kernelheader_addr=0x600000\0" \
403 "kernelheader_addr_r=0x80200000\0" \
404 "kernel_addr_r=0x81000000\0" \
405 "kernelheader_size=0x40000\0" \
406 "fdt_addr_r=0x90000000\0" \
407 "load_addr=0xa0000000\0" \
408 "kernel_size=0x2800000\0" \
409 "kernel_size_sd=0x14000\0" \
410 "kernelhdr_size_sd=0x20\0" \
413 "boot_scripts=ls1088ardb_boot.scr\0" \
414 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
415 "scan_dev_for_boot_part=" \
416 "part list ${devtype} ${devnum} devplist; " \
417 "env exists devplist || setenv devplist 1; " \
418 "for distro_bootpart in ${devplist}; do " \
419 "if fstype ${devtype} " \
420 "${devnum}:${distro_bootpart} " \
421 "bootfstype; then " \
422 "run scan_dev_for_boot; " \
426 "load ${devtype} ${devnum}:${distro_bootpart} " \
427 "${scriptaddr} ${prefix}${script}; " \
428 "env exists secureboot && load ${devtype} " \
429 "${devnum}:${distro_bootpart} " \
430 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
431 "&& esbc_validate ${scripthdraddr};" \
432 "source ${scriptaddr}\0" \
433 "installer=load mmc 0:2 $load_addr " \
434 "/flex_installer_arm64.itb; " \
435 "env exists mcinitcmd && run mcinitcmd && " \
436 "mmc read 0x80001000 0x6800 0x800;" \
437 "fsl_mc lazyapply dpl 0x80001000;" \
438 "bootm $load_addr#ls1088ardb\0" \
439 "qspi_bootcmd=echo Trying load from qspi..;" \
440 "sf probe && sf read $load_addr " \
441 "$kernel_addr $kernel_size ; env exists secureboot " \
442 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
443 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
444 "bootm $load_addr#$BOARD\0" \
445 "sd_bootcmd=echo Trying load from sd card..;" \
446 "mmcinfo; mmc read $load_addr " \
447 "$kernel_addr_sd $kernel_size_sd ;" \
448 "env exists secureboot && mmc read $kernelheader_addr_r "\
449 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
450 " && esbc_validate ${kernelheader_addr_r};" \
451 "bootm $load_addr#$BOARD\0"
452 #endif /* CONFIG_TFABOOT */
454 #undef CONFIG_BOOTCOMMAND
455 #ifdef CONFIG_TFABOOT
456 #define QSPI_NOR_BOOTCOMMAND \
457 "sf read 0x80001000 0xd00000 0x100000;" \
458 "env exists mcinitcmd && env exists secureboot " \
459 " && sf read 0x806C0000 0x6C0000 0x100000 " \
460 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
461 "&& fsl_mc lazyapply dpl 0x80001000;" \
462 "run distro_bootcmd;run qspi_bootcmd;" \
463 "env exists secureboot && esbc_halt;"
464 #define SD_BOOTCOMMAND \
465 "env exists mcinitcmd && mmcinfo; " \
466 "mmc read 0x80001000 0x6800 0x800; " \
467 "env exists mcinitcmd && env exists secureboot " \
468 " && mmc read 0x806C0000 0x3600 0x20 " \
469 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
470 "&& fsl_mc lazyapply dpl 0x80001000;" \
471 "run distro_bootcmd;run sd_bootcmd;" \
472 "env exists secureboot && esbc_halt;"
474 #if defined(CONFIG_QSPI_BOOT)
475 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
476 #define CONFIG_BOOTCOMMAND \
477 "sf read 0x80001000 0xd00000 0x100000;" \
478 "env exists mcinitcmd && env exists secureboot " \
479 " && sf read 0x806C0000 0x6C0000 0x100000 " \
480 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
481 "&& fsl_mc lazyapply dpl 0x80001000;" \
482 "run distro_bootcmd;run qspi_bootcmd;" \
483 "env exists secureboot && esbc_halt;"
485 /* Try to boot an on-SD kernel first, then do normal distro boot */
486 #elif defined(CONFIG_SD_BOOT)
487 #define CONFIG_BOOTCOMMAND \
488 "env exists mcinitcmd && mmcinfo; " \
489 "mmc read 0x80001000 0x6800 0x800; " \
490 "env exists mcinitcmd && env exists secureboot " \
491 " && mmc read 0x806C0000 0x3600 0x20 " \
492 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
493 "&& fsl_mc lazyapply dpl 0x80001000;" \
494 "run distro_bootcmd;run sd_bootcmd;" \
495 "env exists secureboot && esbc_halt;"
497 #endif /* CONFIG_TFABOOT */
499 /* MAC/PHY configuration */
500 #ifdef CONFIG_FSL_MC_ENET
501 #define AQ_PHY_ADDR1 0x00
502 #define AQR105_IRQ_MASK 0x00000004
504 #define QSGMII1_PORT1_PHY_ADDR 0x0c
505 #define QSGMII1_PORT2_PHY_ADDR 0x0d
506 #define QSGMII1_PORT3_PHY_ADDR 0x0e
507 #define QSGMII1_PORT4_PHY_ADDR 0x0f
508 #define QSGMII2_PORT1_PHY_ADDR 0x1c
509 #define QSGMII2_PORT2_PHY_ADDR 0x1d
510 #define QSGMII2_PORT3_PHY_ADDR 0x1e
511 #define QSGMII2_PORT4_PHY_ADDR 0x1f
513 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
514 #define CONFIG_PHY_GIGE
520 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
525 #define BOOT_TARGET_DEVICES(func) \
527 func(SCSI, scsi, 0) \
529 #include <config_distro_bootcmd.h>
532 #include <asm/fsl_secure_boot.h>
534 #endif /* __LS1088A_RDB_H */