1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_CLK_FREQ 100000000
20 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
21 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
24 #define CONFIG_SYS_FSL_DDR_EMU
26 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
30 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
33 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
34 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
35 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
36 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
38 #define CONFIG_SYS_NOR0_CSPR \
39 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
43 #define CONFIG_SYS_NOR0_CSPR_EARLY \
44 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
48 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
49 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
50 FTIM0_NOR_TEADC(0x1) | \
52 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
53 FTIM1_NOR_TRAD_NOR(0x1))
54 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
55 FTIM2_NOR_TCH(0x0) | \
57 #define CONFIG_SYS_NOR_FTIM3 0x04000000
58 #define CONFIG_SYS_IFC_CCR 0x01000000
61 #define CONFIG_SYS_FLASH_QUIET_TEST
62 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
64 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
65 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
66 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
67 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
69 #define CONFIG_SYS_FLASH_EMPTY_INFO
70 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
75 #define CONFIG_NAND_FSL_IFC
78 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
79 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
81 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
82 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
83 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
84 | CSPR_MSEL_NAND /* MSEL = NAND */ \
86 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
88 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
89 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
90 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
91 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
92 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
93 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
94 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
96 #define CONFIG_SYS_NAND_ONFI_DETECTION
98 /* ONFI NAND Flash mode0 Timing Params */
99 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
100 FTIM0_NAND_TWP(0x18) | \
101 FTIM0_NAND_TWCHT(0x07) | \
102 FTIM0_NAND_TWH(0x0a))
103 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
104 FTIM1_NAND_TWBE(0x39) | \
105 FTIM1_NAND_TRR(0x0e) | \
106 FTIM1_NAND_TRP(0x18))
107 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
108 FTIM2_NAND_TREH(0x0a) | \
109 FTIM2_NAND_TWHRE(0x1e))
110 #define CONFIG_SYS_NAND_FTIM3 0x0
112 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
113 #define CONFIG_SYS_MAX_NAND_DEVICE 1
114 #define CONFIG_MTD_NAND_VERIFY_WRITE
116 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
119 #define CONFIG_FSL_QIXIS
122 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
123 #define QIXIS_BRDCFG4_OFFSET 0x54
124 #define QIXIS_LBMAP_SWITCH 2
125 #define QIXIS_QMAP_MASK 0xe0
126 #define QIXIS_QMAP_SHIFT 5
127 #define QIXIS_LBMAP_MASK 0x1f
128 #define QIXIS_LBMAP_SHIFT 5
129 #define QIXIS_LBMAP_DFLTBANK 0x00
130 #define QIXIS_LBMAP_ALTBANK 0x20
131 #define QIXIS_LBMAP_SD 0x00
132 #define QIXIS_LBMAP_EMMC 0x00
133 #define QIXIS_LBMAP_SD_QSPI 0x00
134 #define QIXIS_LBMAP_QSPI 0x00
135 #define QIXIS_RCW_SRC_SD 0x40
136 #define QIXIS_RCW_SRC_EMMC 0x41
137 #define QIXIS_RCW_SRC_QSPI 0x62
138 #define QIXIS_RST_CTL_RESET 0x31
139 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
140 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
141 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
142 #define QIXIS_RST_FORCE_MEM 0x01
144 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
145 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
149 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
154 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
155 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
156 /* QIXIS Timing parameters*/
157 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
158 FTIM0_GPCM_TEADC(0x0e) | \
159 FTIM0_GPCM_TEAHC(0x0e))
160 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
161 FTIM1_GPCM_TRAD(0x3f))
162 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
163 FTIM2_GPCM_TCH(0xf) | \
164 FTIM2_GPCM_TWP(0x3E))
165 #define SYS_FPGA_CS_FTIM3 0x0
167 #if defined(CONFIG_TFABOOT) || \
168 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
169 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
170 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
171 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
172 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
173 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
174 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
175 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
176 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
177 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
178 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
179 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
180 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
181 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
182 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
183 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
184 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
185 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
187 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
188 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
189 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
190 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
191 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
192 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
193 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
194 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
195 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
198 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
200 #define I2C_MUX_CH_VOL_MONITOR 0xA
201 /* Voltage monitor on channel 2*/
202 #define I2C_VOL_MONITOR_ADDR 0x63
203 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
204 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
205 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
206 #define I2C_SVDD_MONITOR_ADDR 0x4F
208 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
211 /* The lowest and highest voltage allowed for LS1088ARDB */
212 #define VDD_MV_MIN 819
213 #define VDD_MV_MAX 1212
215 #define CONFIG_VOL_MONITOR_LTC3882_SET
216 #define CONFIG_VOL_MONITOR_LTC3882_READ
218 #define PWM_CHANNEL0 0x0
221 * I2C bus multiplexer
223 #define I2C_MUX_PCA_ADDR_PRI 0x77
224 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
225 #define I2C_RETIMER_ADDR 0x18
226 #define I2C_MUX_CH_DEFAULT 0x8
227 #define I2C_MUX_CH5 0xD
234 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
238 #define CONFIG_SYS_I2C_EEPROM_NXID
239 #define CONFIG_SYS_EEPROM_BUS_NUM 0
241 #ifdef CONFIG_SPL_BUILD
242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
244 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
247 #define CONFIG_FSL_MEMAC
250 /* Initial environment variables */
251 #ifdef CONFIG_TFABOOT
252 #define QSPI_MC_INIT_CMD \
253 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
254 "sf read 0x80e00000 0xE00000 0x100000;" \
255 "env exists secureboot && " \
256 "sf read 0x80640000 0x640000 0x40000 && " \
257 "sf read 0x80680000 0x680000 0x40000 && " \
258 "esbc_validate 0x80640000 && " \
259 "esbc_validate 0x80680000 ;" \
260 "fsl_mc start mc 0x80a00000 0x80e00000\0"
261 #define SD_MC_INIT_CMD \
262 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
263 "mmc read 0x80e00000 0x7000 0x800;" \
264 "env exists secureboot && " \
265 "mmc read 0x80640000 0x3200 0x20 && " \
266 "mmc read 0x80680000 0x3400 0x20 && " \
267 "esbc_validate 0x80640000 && " \
268 "esbc_validate 0x80680000 ;" \
269 "fsl_mc start mc 0x80a00000 0x80e00000\0"
271 #if defined(CONFIG_QSPI_BOOT)
272 #define MC_INIT_CMD \
273 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
274 "sf read 0x80e00000 0xE00000 0x100000;" \
275 "env exists secureboot && " \
276 "sf read 0x80640000 0x640000 0x40000 && " \
277 "sf read 0x80680000 0x680000 0x40000 && " \
278 "esbc_validate 0x80640000 && " \
279 "esbc_validate 0x80680000 ;" \
280 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
281 "mcmemsize=0x70000000\0"
282 #elif defined(CONFIG_SD_BOOT)
283 #define MC_INIT_CMD \
284 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
285 "mmc read 0x80e00000 0x7000 0x800;" \
286 "env exists secureboot && " \
287 "mmc read 0x80640000 0x3200 0x20 && " \
288 "mmc read 0x80680000 0x3400 0x20 && " \
289 "esbc_validate 0x80640000 && " \
290 "esbc_validate 0x80680000 ;" \
291 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
292 "mcmemsize=0x70000000\0"
294 #endif /* CONFIG_TFABOOT */
296 #undef CONFIG_EXTRA_ENV_SETTINGS
297 #ifdef CONFIG_TFABOOT
298 #define CONFIG_EXTRA_ENV_SETTINGS \
299 "BOARD=ls1088ardb\0" \
300 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
301 "ramdisk_addr=0x800000\0" \
302 "ramdisk_size=0x2000000\0" \
303 "fdt_high=0xa0000000\0" \
304 "initrd_high=0xffffffffffffffff\0" \
305 "fdt_addr=0x64f00000\0" \
306 "kernel_addr=0x1000000\0" \
307 "kernel_addr_sd=0x8000\0" \
308 "kernelhdr_addr_sd=0x3000\0" \
309 "kernel_start=0x580100000\0" \
310 "kernelheader_start=0x580600000\0" \
311 "scriptaddr=0x80000000\0" \
312 "scripthdraddr=0x80080000\0" \
313 "fdtheader_addr_r=0x80100000\0" \
314 "kernelheader_addr=0x600000\0" \
315 "kernelheader_addr_r=0x80200000\0" \
316 "kernel_addr_r=0x81000000\0" \
317 "kernelheader_size=0x40000\0" \
318 "fdt_addr_r=0x90000000\0" \
319 "load_addr=0xa0000000\0" \
320 "kernel_size=0x2800000\0" \
321 "kernel_size_sd=0x14000\0" \
322 "kernelhdr_size_sd=0x20\0" \
324 "mcmemsize=0x70000000\0" \
326 "boot_scripts=ls1088ardb_boot.scr\0" \
327 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
328 "scan_dev_for_boot_part=" \
329 "part list ${devtype} ${devnum} devplist; " \
330 "env exists devplist || setenv devplist 1; " \
331 "for distro_bootpart in ${devplist}; do " \
332 "if fstype ${devtype} " \
333 "${devnum}:${distro_bootpart} " \
334 "bootfstype; then " \
335 "run scan_dev_for_boot; " \
339 "load ${devtype} ${devnum}:${distro_bootpart} " \
340 "${scriptaddr} ${prefix}${script}; " \
341 "env exists secureboot && load ${devtype} " \
342 "${devnum}:${distro_bootpart} " \
343 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
344 "env exists secureboot " \
345 "&& esbc_validate ${scripthdraddr};" \
346 "source ${scriptaddr}\0" \
347 "installer=load mmc 0:2 $load_addr " \
348 "/flex_installer_arm64.itb; " \
349 "env exists mcinitcmd && run mcinitcmd && " \
350 "mmc read 0x80001000 0x6800 0x800;" \
351 "fsl_mc lazyapply dpl 0x80001000;" \
352 "bootm $load_addr#ls1088ardb\0" \
353 "qspi_bootcmd=echo Trying load from qspi..;" \
354 "sf probe && sf read $load_addr " \
355 "$kernel_addr $kernel_size ; env exists secureboot " \
356 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
357 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
358 "bootm $load_addr#$BOARD\0" \
359 "sd_bootcmd=echo Trying load from sd card..;" \
360 "mmcinfo; mmc read $load_addr " \
361 "$kernel_addr_sd $kernel_size_sd ;" \
362 "env exists secureboot && mmc read $kernelheader_addr_r "\
363 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
364 " && esbc_validate ${kernelheader_addr_r};" \
365 "bootm $load_addr#$BOARD\0"
367 #define CONFIG_EXTRA_ENV_SETTINGS \
368 "BOARD=ls1088ardb\0" \
369 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
370 "ramdisk_addr=0x800000\0" \
371 "ramdisk_size=0x2000000\0" \
372 "fdt_high=0xa0000000\0" \
373 "initrd_high=0xffffffffffffffff\0" \
374 "fdt_addr=0x64f00000\0" \
375 "kernel_addr=0x1000000\0" \
376 "kernel_addr_sd=0x8000\0" \
377 "kernelhdr_addr_sd=0x3000\0" \
378 "kernel_start=0x580100000\0" \
379 "kernelheader_start=0x580800000\0" \
380 "scriptaddr=0x80000000\0" \
381 "scripthdraddr=0x80080000\0" \
382 "fdtheader_addr_r=0x80100000\0" \
383 "kernelheader_addr=0x600000\0" \
384 "kernelheader_addr_r=0x80200000\0" \
385 "kernel_addr_r=0x81000000\0" \
386 "kernelheader_size=0x40000\0" \
387 "fdt_addr_r=0x90000000\0" \
388 "load_addr=0xa0000000\0" \
389 "kernel_size=0x2800000\0" \
390 "kernel_size_sd=0x14000\0" \
391 "kernelhdr_size_sd=0x20\0" \
394 "boot_scripts=ls1088ardb_boot.scr\0" \
395 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
396 "scan_dev_for_boot_part=" \
397 "part list ${devtype} ${devnum} devplist; " \
398 "env exists devplist || setenv devplist 1; " \
399 "for distro_bootpart in ${devplist}; do " \
400 "if fstype ${devtype} " \
401 "${devnum}:${distro_bootpart} " \
402 "bootfstype; then " \
403 "run scan_dev_for_boot; " \
407 "load ${devtype} ${devnum}:${distro_bootpart} " \
408 "${scriptaddr} ${prefix}${script}; " \
409 "env exists secureboot && load ${devtype} " \
410 "${devnum}:${distro_bootpart} " \
411 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
412 "&& esbc_validate ${scripthdraddr};" \
413 "source ${scriptaddr}\0" \
414 "installer=load mmc 0:2 $load_addr " \
415 "/flex_installer_arm64.itb; " \
416 "env exists mcinitcmd && run mcinitcmd && " \
417 "mmc read 0x80001000 0x6800 0x800;" \
418 "fsl_mc lazyapply dpl 0x80001000;" \
419 "bootm $load_addr#ls1088ardb\0" \
420 "qspi_bootcmd=echo Trying load from qspi..;" \
421 "sf probe && sf read $load_addr " \
422 "$kernel_addr $kernel_size ; env exists secureboot " \
423 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
424 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
425 "bootm $load_addr#$BOARD\0" \
426 "sd_bootcmd=echo Trying load from sd card..;" \
427 "mmcinfo; mmc read $load_addr " \
428 "$kernel_addr_sd $kernel_size_sd ;" \
429 "env exists secureboot && mmc read $kernelheader_addr_r "\
430 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
431 " && esbc_validate ${kernelheader_addr_r};" \
432 "bootm $load_addr#$BOARD\0"
433 #endif /* CONFIG_TFABOOT */
435 #undef CONFIG_BOOTCOMMAND
436 #ifdef CONFIG_TFABOOT
437 #define QSPI_NOR_BOOTCOMMAND \
438 "sf read 0x80001000 0xd00000 0x100000;" \
439 "env exists mcinitcmd && env exists secureboot " \
440 " && sf read 0x806C0000 0x6C0000 0x100000 " \
441 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
442 "&& fsl_mc lazyapply dpl 0x80001000;" \
443 "run distro_bootcmd;run qspi_bootcmd;" \
444 "env exists secureboot && esbc_halt;"
445 #define SD_BOOTCOMMAND \
446 "env exists mcinitcmd && mmcinfo; " \
447 "mmc read 0x80001000 0x6800 0x800; " \
448 "env exists mcinitcmd && env exists secureboot " \
449 " && mmc read 0x806C0000 0x3600 0x20 " \
450 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
451 "&& fsl_mc lazyapply dpl 0x80001000;" \
452 "run distro_bootcmd;run sd_bootcmd;" \
453 "env exists secureboot && esbc_halt;"
455 #if defined(CONFIG_QSPI_BOOT)
456 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
457 #define CONFIG_BOOTCOMMAND \
458 "sf read 0x80001000 0xd00000 0x100000;" \
459 "env exists mcinitcmd && env exists secureboot " \
460 " && sf read 0x806C0000 0x6C0000 0x100000 " \
461 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
462 "&& fsl_mc lazyapply dpl 0x80001000;" \
463 "run distro_bootcmd;run qspi_bootcmd;" \
464 "env exists secureboot && esbc_halt;"
466 /* Try to boot an on-SD kernel first, then do normal distro boot */
467 #elif defined(CONFIG_SD_BOOT)
468 #define CONFIG_BOOTCOMMAND \
469 "env exists mcinitcmd && mmcinfo; " \
470 "mmc read 0x80001000 0x6800 0x800; " \
471 "env exists mcinitcmd && env exists secureboot " \
472 " && mmc read 0x806C0000 0x3600 0x20 " \
473 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
474 "&& fsl_mc lazyapply dpl 0x80001000;" \
475 "run distro_bootcmd;run sd_bootcmd;" \
476 "env exists secureboot && esbc_halt;"
478 #endif /* CONFIG_TFABOOT */
480 /* MAC/PHY configuration */
481 #ifdef CONFIG_FSL_MC_ENET
482 #define AQ_PHY_ADDR1 0x00
483 #define AQR105_IRQ_MASK 0x00000004
485 #define QSGMII1_PORT1_PHY_ADDR 0x0c
486 #define QSGMII1_PORT2_PHY_ADDR 0x0d
487 #define QSGMII1_PORT3_PHY_ADDR 0x0e
488 #define QSGMII1_PORT4_PHY_ADDR 0x0f
489 #define QSGMII2_PORT1_PHY_ADDR 0x1c
490 #define QSGMII2_PORT2_PHY_ADDR 0x1d
491 #define QSGMII2_PORT3_PHY_ADDR 0x1e
492 #define QSGMII2_PORT4_PHY_ADDR 0x1f
494 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
495 #define CONFIG_PHY_GIGE
501 #define BOOT_TARGET_DEVICES(func) \
504 func(SCSI, scsi, 0) \
506 #include <config_distro_bootcmd.h>
509 #include <asm/fsl_secure_boot.h>
511 #endif /* __LS1088A_RDB_H */