1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_CLK_FREQ 100000000
20 #define CONFIG_DDR_CLK_FREQ 100000000
21 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
22 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
24 #define CONFIG_DDR_SPD
26 #define CONFIG_SYS_FSL_DDR_EMU
27 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
28 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
30 #define CONFIG_DDR_ECC
31 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
32 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS 0x51
35 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
36 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
39 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
40 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
41 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
42 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
44 #define CONFIG_SYS_NOR0_CSPR \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
49 #define CONFIG_SYS_NOR0_CSPR_EARLY \
50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
54 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
55 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
56 FTIM0_NOR_TEADC(0x1) | \
58 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
59 FTIM1_NOR_TRAD_NOR(0x1))
60 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
61 FTIM2_NOR_TCH(0x0) | \
63 #define CONFIG_SYS_NOR_FTIM3 0x04000000
64 #define CONFIG_SYS_IFC_CCR 0x01000000
67 #define CONFIG_SYS_FLASH_QUIET_TEST
68 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
70 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
71 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
72 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
73 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
75 #define CONFIG_SYS_FLASH_EMPTY_INFO
76 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
81 #define CONFIG_NAND_FSL_IFC
84 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
85 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
87 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
88 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
89 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
90 | CSPR_MSEL_NAND /* MSEL = NAND */ \
92 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
94 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
95 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
96 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
97 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
98 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
99 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
100 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
102 #define CONFIG_SYS_NAND_ONFI_DETECTION
104 /* ONFI NAND Flash mode0 Timing Params */
105 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
106 FTIM0_NAND_TWP(0x18) | \
107 FTIM0_NAND_TWCHT(0x07) | \
108 FTIM0_NAND_TWH(0x0a))
109 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
110 FTIM1_NAND_TWBE(0x39) | \
111 FTIM1_NAND_TRR(0x0e) | \
112 FTIM1_NAND_TRP(0x18))
113 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
114 FTIM2_NAND_TREH(0x0a) | \
115 FTIM2_NAND_TWHRE(0x1e))
116 #define CONFIG_SYS_NAND_FTIM3 0x0
118 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
119 #define CONFIG_SYS_MAX_NAND_DEVICE 1
120 #define CONFIG_MTD_NAND_VERIFY_WRITE
122 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
125 #define CONFIG_FSL_QIXIS
128 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
129 #define QIXIS_BRDCFG4_OFFSET 0x54
130 #define QIXIS_LBMAP_SWITCH 2
131 #define QIXIS_QMAP_MASK 0xe0
132 #define QIXIS_QMAP_SHIFT 5
133 #define QIXIS_LBMAP_MASK 0x1f
134 #define QIXIS_LBMAP_SHIFT 5
135 #define QIXIS_LBMAP_DFLTBANK 0x00
136 #define QIXIS_LBMAP_ALTBANK 0x20
137 #define QIXIS_LBMAP_SD 0x00
138 #define QIXIS_LBMAP_EMMC 0x00
139 #define QIXIS_LBMAP_SD_QSPI 0x00
140 #define QIXIS_LBMAP_QSPI 0x00
141 #define QIXIS_RCW_SRC_SD 0x40
142 #define QIXIS_RCW_SRC_EMMC 0x41
143 #define QIXIS_RCW_SRC_QSPI 0x62
144 #define QIXIS_RST_CTL_RESET 0x31
145 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
146 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
147 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
148 #define QIXIS_RST_FORCE_MEM 0x01
150 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
151 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
155 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
160 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
161 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
162 /* QIXIS Timing parameters*/
163 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
164 FTIM0_GPCM_TEADC(0x0e) | \
165 FTIM0_GPCM_TEAHC(0x0e))
166 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
167 FTIM1_GPCM_TRAD(0x3f))
168 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
169 FTIM2_GPCM_TCH(0xf) | \
170 FTIM2_GPCM_TWP(0x3E))
171 #define SYS_FPGA_CS_FTIM3 0x0
173 #if defined(CONFIG_TFABOOT) || \
174 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
175 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
176 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
177 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
178 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
179 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
180 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
181 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
182 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
183 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
184 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
185 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
186 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
187 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
188 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
189 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
190 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
191 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
193 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
194 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
195 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
196 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
197 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
198 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
199 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
200 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
201 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
206 #define I2C_MUX_CH_VOL_MONITOR 0xA
207 /* Voltage monitor on channel 2*/
208 #define I2C_VOL_MONITOR_ADDR 0x63
209 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
210 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
211 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
212 #define I2C_SVDD_MONITOR_ADDR 0x4F
214 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
217 /* The lowest and highest voltage allowed for LS1088ARDB */
218 #define VDD_MV_MIN 819
219 #define VDD_MV_MAX 1212
221 #define CONFIG_VOL_MONITOR_LTC3882_SET
222 #define CONFIG_VOL_MONITOR_LTC3882_READ
224 #define PWM_CHANNEL0 0x0
227 * I2C bus multiplexer
229 #define I2C_MUX_PCA_ADDR_PRI 0x77
230 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
231 #define I2C_RETIMER_ADDR 0x18
232 #define I2C_MUX_CH_DEFAULT 0x8
233 #define I2C_MUX_CH5 0xD
240 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
244 #define CONFIG_SYS_I2C_EEPROM_NXID
245 #define CONFIG_SYS_EEPROM_BUS_NUM 0
246 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
247 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
248 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
249 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
251 #ifdef CONFIG_SPL_BUILD
252 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
257 #define CONFIG_FSL_MEMAC
260 /* Initial environment variables */
261 #ifdef CONFIG_TFABOOT
262 #define QSPI_MC_INIT_CMD \
263 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
264 "sf read 0x80e00000 0xE00000 0x100000;" \
265 "env exists secureboot && " \
266 "sf read 0x80640000 0x640000 0x40000 && " \
267 "sf read 0x80680000 0x680000 0x40000 && " \
268 "esbc_validate 0x80640000 && " \
269 "esbc_validate 0x80680000 ;" \
270 "fsl_mc start mc 0x80a00000 0x80e00000\0"
271 #define SD_MC_INIT_CMD \
272 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
273 "mmc read 0x80e00000 0x7000 0x800;" \
274 "env exists secureboot && " \
275 "mmc read 0x80640000 0x3200 0x20 && " \
276 "mmc read 0x80680000 0x3400 0x20 && " \
277 "esbc_validate 0x80640000 && " \
278 "esbc_validate 0x80680000 ;" \
279 "fsl_mc start mc 0x80a00000 0x80e00000\0"
281 #if defined(CONFIG_QSPI_BOOT)
282 #define MC_INIT_CMD \
283 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
284 "sf read 0x80e00000 0xE00000 0x100000;" \
285 "env exists secureboot && " \
286 "sf read 0x80640000 0x640000 0x40000 && " \
287 "sf read 0x80680000 0x680000 0x40000 && " \
288 "esbc_validate 0x80640000 && " \
289 "esbc_validate 0x80680000 ;" \
290 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
291 "mcmemsize=0x70000000\0"
292 #elif defined(CONFIG_SD_BOOT)
293 #define MC_INIT_CMD \
294 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
295 "mmc read 0x80e00000 0x7000 0x800;" \
296 "env exists secureboot && " \
297 "mmc read 0x80640000 0x3200 0x20 && " \
298 "mmc read 0x80680000 0x3400 0x20 && " \
299 "esbc_validate 0x80640000 && " \
300 "esbc_validate 0x80680000 ;" \
301 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
302 "mcmemsize=0x70000000\0"
304 #endif /* CONFIG_TFABOOT */
306 #undef CONFIG_EXTRA_ENV_SETTINGS
307 #ifdef CONFIG_TFABOOT
308 #define CONFIG_EXTRA_ENV_SETTINGS \
309 "BOARD=ls1088ardb\0" \
310 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
311 "ramdisk_addr=0x800000\0" \
312 "ramdisk_size=0x2000000\0" \
313 "fdt_high=0xa0000000\0" \
314 "initrd_high=0xffffffffffffffff\0" \
315 "fdt_addr=0x64f00000\0" \
316 "kernel_addr=0x1000000\0" \
317 "kernel_addr_sd=0x8000\0" \
318 "kernelhdr_addr_sd=0x3000\0" \
319 "kernel_start=0x580100000\0" \
320 "kernelheader_start=0x580600000\0" \
321 "scriptaddr=0x80000000\0" \
322 "scripthdraddr=0x80080000\0" \
323 "fdtheader_addr_r=0x80100000\0" \
324 "kernelheader_addr=0x600000\0" \
325 "kernelheader_addr_r=0x80200000\0" \
326 "kernel_addr_r=0x81000000\0" \
327 "kernelheader_size=0x40000\0" \
328 "fdt_addr_r=0x90000000\0" \
329 "load_addr=0xa0000000\0" \
330 "kernel_size=0x2800000\0" \
331 "kernel_size_sd=0x14000\0" \
332 "kernelhdr_size_sd=0x20\0" \
334 "mcmemsize=0x70000000\0" \
336 "boot_scripts=ls1088ardb_boot.scr\0" \
337 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
338 "scan_dev_for_boot_part=" \
339 "part list ${devtype} ${devnum} devplist; " \
340 "env exists devplist || setenv devplist 1; " \
341 "for distro_bootpart in ${devplist}; do " \
342 "if fstype ${devtype} " \
343 "${devnum}:${distro_bootpart} " \
344 "bootfstype; then " \
345 "run scan_dev_for_boot; " \
349 "load ${devtype} ${devnum}:${distro_bootpart} " \
350 "${scriptaddr} ${prefix}${script}; " \
351 "env exists secureboot && load ${devtype} " \
352 "${devnum}:${distro_bootpart} " \
353 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
354 "env exists secureboot " \
355 "&& esbc_validate ${scripthdraddr};" \
356 "source ${scriptaddr}\0" \
357 "installer=load mmc 0:2 $load_addr " \
358 "/flex_installer_arm64.itb; " \
359 "env exists mcinitcmd && run mcinitcmd && " \
360 "mmc read 0x80001000 0x6800 0x800;" \
361 "fsl_mc lazyapply dpl 0x80001000;" \
362 "bootm $load_addr#ls1088ardb\0" \
363 "qspi_bootcmd=echo Trying load from qspi..;" \
364 "sf probe && sf read $load_addr " \
365 "$kernel_addr $kernel_size ; env exists secureboot " \
366 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
367 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
368 "bootm $load_addr#$BOARD\0" \
369 "sd_bootcmd=echo Trying load from sd card..;" \
370 "mmcinfo; mmc read $load_addr " \
371 "$kernel_addr_sd $kernel_size_sd ;" \
372 "env exists secureboot && mmc read $kernelheader_addr_r "\
373 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
374 " && esbc_validate ${kernelheader_addr_r};" \
375 "bootm $load_addr#$BOARD\0"
377 #define CONFIG_EXTRA_ENV_SETTINGS \
378 "BOARD=ls1088ardb\0" \
379 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
380 "ramdisk_addr=0x800000\0" \
381 "ramdisk_size=0x2000000\0" \
382 "fdt_high=0xa0000000\0" \
383 "initrd_high=0xffffffffffffffff\0" \
384 "fdt_addr=0x64f00000\0" \
385 "kernel_addr=0x1000000\0" \
386 "kernel_addr_sd=0x8000\0" \
387 "kernelhdr_addr_sd=0x3000\0" \
388 "kernel_start=0x580100000\0" \
389 "kernelheader_start=0x580800000\0" \
390 "scriptaddr=0x80000000\0" \
391 "scripthdraddr=0x80080000\0" \
392 "fdtheader_addr_r=0x80100000\0" \
393 "kernelheader_addr=0x600000\0" \
394 "kernelheader_addr_r=0x80200000\0" \
395 "kernel_addr_r=0x81000000\0" \
396 "kernelheader_size=0x40000\0" \
397 "fdt_addr_r=0x90000000\0" \
398 "load_addr=0xa0000000\0" \
399 "kernel_size=0x2800000\0" \
400 "kernel_size_sd=0x14000\0" \
401 "kernelhdr_size_sd=0x20\0" \
404 "boot_scripts=ls1088ardb_boot.scr\0" \
405 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
406 "scan_dev_for_boot_part=" \
407 "part list ${devtype} ${devnum} devplist; " \
408 "env exists devplist || setenv devplist 1; " \
409 "for distro_bootpart in ${devplist}; do " \
410 "if fstype ${devtype} " \
411 "${devnum}:${distro_bootpart} " \
412 "bootfstype; then " \
413 "run scan_dev_for_boot; " \
417 "load ${devtype} ${devnum}:${distro_bootpart} " \
418 "${scriptaddr} ${prefix}${script}; " \
419 "env exists secureboot && load ${devtype} " \
420 "${devnum}:${distro_bootpart} " \
421 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
422 "&& esbc_validate ${scripthdraddr};" \
423 "source ${scriptaddr}\0" \
424 "installer=load mmc 0:2 $load_addr " \
425 "/flex_installer_arm64.itb; " \
426 "env exists mcinitcmd && run mcinitcmd && " \
427 "mmc read 0x80001000 0x6800 0x800;" \
428 "fsl_mc lazyapply dpl 0x80001000;" \
429 "bootm $load_addr#ls1088ardb\0" \
430 "qspi_bootcmd=echo Trying load from qspi..;" \
431 "sf probe && sf read $load_addr " \
432 "$kernel_addr $kernel_size ; env exists secureboot " \
433 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
434 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
435 "bootm $load_addr#$BOARD\0" \
436 "sd_bootcmd=echo Trying load from sd card..;" \
437 "mmcinfo; mmc read $load_addr " \
438 "$kernel_addr_sd $kernel_size_sd ;" \
439 "env exists secureboot && mmc read $kernelheader_addr_r "\
440 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
441 " && esbc_validate ${kernelheader_addr_r};" \
442 "bootm $load_addr#$BOARD\0"
443 #endif /* CONFIG_TFABOOT */
445 #undef CONFIG_BOOTCOMMAND
446 #ifdef CONFIG_TFABOOT
447 #define QSPI_NOR_BOOTCOMMAND \
448 "sf read 0x80001000 0xd00000 0x100000;" \
449 "env exists mcinitcmd && env exists secureboot " \
450 " && sf read 0x806C0000 0x6C0000 0x100000 " \
451 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
452 "&& fsl_mc lazyapply dpl 0x80001000;" \
453 "run distro_bootcmd;run qspi_bootcmd;" \
454 "env exists secureboot && esbc_halt;"
455 #define SD_BOOTCOMMAND \
456 "env exists mcinitcmd && mmcinfo; " \
457 "mmc read 0x80001000 0x6800 0x800; " \
458 "env exists mcinitcmd && env exists secureboot " \
459 " && mmc read 0x806C0000 0x3600 0x20 " \
460 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
461 "&& fsl_mc lazyapply dpl 0x80001000;" \
462 "run distro_bootcmd;run sd_bootcmd;" \
463 "env exists secureboot && esbc_halt;"
465 #if defined(CONFIG_QSPI_BOOT)
466 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
467 #define CONFIG_BOOTCOMMAND \
468 "sf read 0x80001000 0xd00000 0x100000;" \
469 "env exists mcinitcmd && env exists secureboot " \
470 " && sf read 0x806C0000 0x6C0000 0x100000 " \
471 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
472 "&& fsl_mc lazyapply dpl 0x80001000;" \
473 "run distro_bootcmd;run qspi_bootcmd;" \
474 "env exists secureboot && esbc_halt;"
476 /* Try to boot an on-SD kernel first, then do normal distro boot */
477 #elif defined(CONFIG_SD_BOOT)
478 #define CONFIG_BOOTCOMMAND \
479 "env exists mcinitcmd && mmcinfo; " \
480 "mmc read 0x80001000 0x6800 0x800; " \
481 "env exists mcinitcmd && env exists secureboot " \
482 " && mmc read 0x806C0000 0x3600 0x20 " \
483 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
484 "&& fsl_mc lazyapply dpl 0x80001000;" \
485 "run distro_bootcmd;run sd_bootcmd;" \
486 "env exists secureboot && esbc_halt;"
488 #endif /* CONFIG_TFABOOT */
490 /* MAC/PHY configuration */
491 #ifdef CONFIG_FSL_MC_ENET
492 #define AQ_PHY_ADDR1 0x00
493 #define AQR105_IRQ_MASK 0x00000004
495 #define QSGMII1_PORT1_PHY_ADDR 0x0c
496 #define QSGMII1_PORT2_PHY_ADDR 0x0d
497 #define QSGMII1_PORT3_PHY_ADDR 0x0e
498 #define QSGMII1_PORT4_PHY_ADDR 0x0f
499 #define QSGMII2_PORT1_PHY_ADDR 0x1c
500 #define QSGMII2_PORT2_PHY_ADDR 0x1d
501 #define QSGMII2_PORT3_PHY_ADDR 0x1e
502 #define QSGMII2_PORT4_PHY_ADDR 0x1f
504 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
505 #define CONFIG_PHY_GIGE
511 #define BOOT_TARGET_DEVICES(func) \
514 func(SCSI, scsi, 0) \
516 #include <config_distro_bootcmd.h>
519 #include <asm/fsl_secure_boot.h>
521 #endif /* __LS1088A_RDB_H */