include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #define SYS_NO_FLASH
  14 #endif
  15
  16 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  17 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  18
  19 #ifdef CONFIG_EMU
  20 #define CONFIG_SYS_FSL_DDR_EMU
  21 #else
  22 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  23 #endif
  24 #define SPD_EEPROM_ADDRESS      0x51
  25 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  26
  27
  28 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  29 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  30 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  31 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  32
  33 #define CONFIG_SYS_NOR0_CSPR                                    \
  34         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  35         CSPR_PORT_SIZE_16                                       | \
  36         CSPR_MSEL_NOR                                           | \
  37         CSPR_V)
  38 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  39         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  40         CSPR_PORT_SIZE_16                                       | \
  41         CSPR_MSEL_NOR                                           | \
  42         CSPR_V)
  43 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  44 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  45                                 FTIM0_NOR_TEADC(0x1) | \
  46                                 FTIM0_NOR_TEAHC(0x1))
  47 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  48                                 FTIM1_NOR_TRAD_NOR(0x1))
  49 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  50                                 FTIM2_NOR_TCH(0x0) | \
  51                                 FTIM2_NOR_TWP(0x1))
  52 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  53 #define CONFIG_SYS_IFC_CCR      0x01000000
  54
  55 #ifndef SYS_NO_FLASH
  56 #define CONFIG_SYS_FLASH_QUIET_TEST
  57 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  58
  59 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  60 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  61 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  62
  63 #define CONFIG_SYS_FLASH_EMPTY_INFO
  64 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  65 #endif
  66 #endif
  67
  68 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  69 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  70
  71 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  72 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  73                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  74                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  75                                 | CSPR_V)
  76 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  77
  78 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  79                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  80                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  81                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  82                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  83                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  84                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  85
  86 /* ONFI NAND Flash mode0 Timing Params */
  87 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  88                                         FTIM0_NAND_TWP(0x18)   | \
  89                                         FTIM0_NAND_TWCHT(0x07) | \
  90                                         FTIM0_NAND_TWH(0x0a))
  91 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  92                                         FTIM1_NAND_TWBE(0x39)  | \
  93                                         FTIM1_NAND_TRR(0x0e)   | \
  94                                         FTIM1_NAND_TRP(0x18))
  95 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
  96                                         FTIM2_NAND_TREH(0x0a) | \
  97                                         FTIM2_NAND_TWHRE(0x1e))
  98 #define CONFIG_SYS_NAND_FTIM3           0x0
  99
 100 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 101 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 102 #define CONFIG_MTD_NAND_VERIFY_WRITE
 103
 104 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 105 #define QIXIS_BRDCFG4_OFFSET            0x54
 106 #define QIXIS_LBMAP_SWITCH              2
 107 #define QIXIS_QMAP_MASK                 0xe0
 108 #define QIXIS_QMAP_SHIFT                5
 109 #define QIXIS_LBMAP_MASK                0x1f
 110 #define QIXIS_LBMAP_SHIFT               5
 111 #define QIXIS_LBMAP_DFLTBANK            0x00
 112 #define QIXIS_LBMAP_ALTBANK             0x20
 113 #define QIXIS_LBMAP_SD                  0x00
 114 #define QIXIS_LBMAP_EMMC                0x00
 115 #define QIXIS_LBMAP_SD_QSPI             0x00
 116 #define QIXIS_LBMAP_QSPI                0x00
 117 #define QIXIS_RCW_SRC_SD                0x40
 118 #define QIXIS_RCW_SRC_EMMC              0x41
 119 #define QIXIS_RCW_SRC_QSPI              0x62
 120 #define QIXIS_RST_CTL_RESET             0x31
 121 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 122 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 123 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 124 #define QIXIS_RST_FORCE_MEM             0x01
 125
 126 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 127 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 128                                         | CSPR_PORT_SIZE_8 \
 129                                         | CSPR_MSEL_GPCM \
 130                                         | CSPR_V)
 131 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 132                                         | CSPR_PORT_SIZE_8 \
 133                                         | CSPR_MSEL_GPCM \
 134                                         | CSPR_V)
 135
 136 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 137 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 138 /* QIXIS Timing parameters*/
 139 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 140                                         FTIM0_GPCM_TEADC(0x0e) | \
 141                                         FTIM0_GPCM_TEAHC(0x0e))
 142 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 143                                         FTIM1_GPCM_TRAD(0x3f))
 144 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 145                                         FTIM2_GPCM_TCH(0xf) | \
 146                                         FTIM2_GPCM_TWP(0x3E))
 147 #define SYS_FPGA_CS_FTIM3       0x0
 148
 149 #if defined(CONFIG_TFABOOT) || \
 150         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 151 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 152 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 153 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 154 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 155 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 156 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 157 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 158 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 159 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 160 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 161 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 162 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 163 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 164 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 165 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 166 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 167 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 168 #else
 169 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 170 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 171 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 172 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 173 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 174 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 175 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 176 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 177 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 178 #endif
 179
 180 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 181
 182 #define I2C_MUX_CH_VOL_MONITOR         0xA
 183 /* Voltage monitor on channel 2*/
 184 #define I2C_VOL_MONITOR_ADDR           0x63
 185 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 186 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 187 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 188 #define I2C_SVDD_MONITOR_ADDR           0x4F
 189
 190 /* The lowest and highest voltage allowed for LS1088ARDB */
 191 #define VDD_MV_MIN                      819
 192 #define VDD_MV_MAX                      1212
 193
 194 #define PWM_CHANNEL0                    0x0
 195
 196 /*
 197  * I2C bus multiplexer
 198  */
 199 #define I2C_MUX_PCA_ADDR_PRI            0x77
 200 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 201 #define I2C_RETIMER_ADDR                0x18
 202 #define I2C_MUX_CH_DEFAULT              0x8
 203 #define I2C_MUX_CH5                     0xD
 204
 205 #ifndef SPL_NO_RTC
 206 /*
 207 * RTC configuration
 208 */
 209 #define RTC
 210 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 211 #endif
 212
 213 /* EEPROM */
 214 #define CONFIG_SYS_I2C_EEPROM_NXID
 215 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 216
 217 #define CONFIG_FSL_MEMAC
 218
 219 #ifndef SPL_NO_ENV
 220 /* Initial environment variables */
 221 #ifdef CONFIG_TFABOOT
 222 #define QSPI_MC_INIT_CMD                                \
 223         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 224         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 225         "env exists secureboot && "                     \
 226         "sf read 0x80640000 0x640000 0x40000 && "       \
 227         "sf read 0x80680000 0x680000 0x40000 && "       \
 228         "esbc_validate 0x80640000 && "                  \
 229         "esbc_validate 0x80680000 ;"                    \
 230         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 231 #define SD_MC_INIT_CMD                          \
 232         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 233         "mmc read 0x80e00000 0x7000 0x800;"                             \
 234         "env exists secureboot && "                     \
 235         "mmc read 0x80640000 0x3200 0x20 && "           \
 236         "mmc read 0x80680000 0x3400 0x20 && "           \
 237         "esbc_validate 0x80640000 && "                  \
 238         "esbc_validate 0x80680000 ;"                    \
 239         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 240 #else
 241 #if defined(CONFIG_QSPI_BOOT)
 242 #define MC_INIT_CMD                             \
 243         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 244         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 245         "env exists secureboot && "                     \
 246         "sf read 0x80640000 0x640000 0x40000 && "       \
 247         "sf read 0x80680000 0x680000 0x40000 && "       \
 248         "esbc_validate 0x80640000 && "                  \
 249         "esbc_validate 0x80680000 ;"                    \
 250         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 251         "mcmemsize=0x70000000\0"
 252 #elif defined(CONFIG_SD_BOOT)
 253 #define MC_INIT_CMD                             \
 254         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 255         "mmc read 0x80e00000 0x7000 0x800;"                             \
 256         "env exists secureboot && "                     \
 257         "mmc read 0x80640000 0x3200 0x20 && "           \
 258         "mmc read 0x80680000 0x3400 0x20 && "           \
 259         "esbc_validate 0x80640000 && "                  \
 260         "esbc_validate 0x80680000 ;"                    \
 261         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 262         "mcmemsize=0x70000000\0"
 263 #endif
 264 #endif /* CONFIG_TFABOOT */
 265
 266 #undef CONFIG_EXTRA_ENV_SETTINGS
 267 #ifdef CONFIG_TFABOOT
 268 #define CONFIG_EXTRA_ENV_SETTINGS               \
 269         "BOARD=ls1088ardb\0"                    \
 270         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 271         "ramdisk_addr=0x800000\0"               \
 272         "ramdisk_size=0x2000000\0"              \
 273         "fdt_high=0xa0000000\0"                 \
 274         "initrd_high=0xffffffffffffffff\0"      \
 275         "fdt_addr=0x64f00000\0"                 \
 276         "kernel_addr=0x1000000\0"               \
 277         "kernel_addr_sd=0x8000\0"               \
 278         "kernelhdr_addr_sd=0x3000\0"            \
 279         "kernel_start=0x580100000\0"            \
 280         "kernelheader_start=0x580600000\0"      \
 281         "scriptaddr=0x80000000\0"               \
 282         "scripthdraddr=0x80080000\0"            \
 283         "fdtheader_addr_r=0x80100000\0"         \
 284         "kernelheader_addr=0x600000\0"          \
 285         "kernelheader_addr_r=0x80200000\0"      \
 286         "kernel_addr_r=0x81000000\0"            \
 287         "kernelheader_size=0x40000\0"           \
 288         "fdt_addr_r=0x90000000\0"               \
 289         "load_addr=0xa0000000\0"                \
 290         "kernel_size=0x2800000\0"               \
 291         "kernel_size_sd=0x14000\0"              \
 292         "kernelhdr_size_sd=0x20\0"              \
 293         QSPI_MC_INIT_CMD                        \
 294         "mcmemsize=0x70000000\0"                \
 295         BOOTENV                                 \
 296         "boot_scripts=ls1088ardb_boot.scr\0"    \
 297         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 298         "scan_dev_for_boot_part="               \
 299                 "part list ${devtype} ${devnum} devplist; "     \
 300                 "env exists devplist || setenv devplist 1; "    \
 301                 "for distro_bootpart in ${devplist}; do "       \
 302                         "if fstype ${devtype} "                 \
 303                                 "${devnum}:${distro_bootpart} " \
 304                                 "bootfstype; then "             \
 305                                 "run scan_dev_for_boot; "       \
 306                         "fi; "                                  \
 307                 "done\0"                                        \
 308         "boot_a_script="                                        \
 309                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 310                 "${scriptaddr} ${prefix}${script}; "            \
 311         "env exists secureboot && load ${devtype} "             \
 312                 "${devnum}:${distro_bootpart} "                 \
 313                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 314                 "env exists secureboot "                        \
 315                 "&& esbc_validate ${scripthdraddr};"            \
 316                 "source ${scriptaddr}\0"                        \
 317         "installer=load mmc 0:2 $load_addr "                    \
 318                 "/flex_installer_arm64.itb; "                   \
 319                 "env exists mcinitcmd && run mcinitcmd && "     \
 320                 "mmc read 0x80001000 0x6800 0x800;"             \
 321                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 322                 "bootm $load_addr#ls1088ardb\0"                 \
 323         "qspi_bootcmd=echo Trying load from qspi..;"            \
 324                 "sf probe && sf read $load_addr "               \
 325                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 326                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 327                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 328                 "bootm $load_addr#$BOARD\0"                     \
 329                 "sd_bootcmd=echo Trying load from sd card..;"           \
 330                 "mmcinfo; mmc read $load_addr "                 \
 331                 "$kernel_addr_sd $kernel_size_sd ;"             \
 332                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 333                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 334                 " && esbc_validate ${kernelheader_addr_r};"     \
 335                 "bootm $load_addr#$BOARD\0"
 336 #else
 337 #define CONFIG_EXTRA_ENV_SETTINGS               \
 338         "BOARD=ls1088ardb\0"                    \
 339         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 340         "ramdisk_addr=0x800000\0"               \
 341         "ramdisk_size=0x2000000\0"              \
 342         "fdt_high=0xa0000000\0"                 \
 343         "initrd_high=0xffffffffffffffff\0"      \
 344         "fdt_addr=0x64f00000\0"                 \
 345         "kernel_addr=0x1000000\0"               \
 346         "kernel_addr_sd=0x8000\0"               \
 347         "kernelhdr_addr_sd=0x3000\0"            \
 348         "kernel_start=0x580100000\0"            \
 349         "kernelheader_start=0x580800000\0"      \
 350         "scriptaddr=0x80000000\0"               \
 351         "scripthdraddr=0x80080000\0"            \
 352         "fdtheader_addr_r=0x80100000\0"         \
 353         "kernelheader_addr=0x600000\0"          \
 354         "kernelheader_addr_r=0x80200000\0"      \
 355         "kernel_addr_r=0x81000000\0"            \
 356         "kernelheader_size=0x40000\0"           \
 357         "fdt_addr_r=0x90000000\0"               \
 358         "load_addr=0xa0000000\0"                \
 359         "kernel_size=0x2800000\0"               \
 360         "kernel_size_sd=0x14000\0"              \
 361         "kernelhdr_size_sd=0x20\0"              \
 362         MC_INIT_CMD                             \
 363         BOOTENV                                 \
 364         "boot_scripts=ls1088ardb_boot.scr\0"    \
 365         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 366         "scan_dev_for_boot_part="               \
 367                 "part list ${devtype} ${devnum} devplist; "     \
 368                 "env exists devplist || setenv devplist 1; "    \
 369                 "for distro_bootpart in ${devplist}; do "       \
 370                         "if fstype ${devtype} "                 \
 371                                 "${devnum}:${distro_bootpart} " \
 372                                 "bootfstype; then "             \
 373                                 "run scan_dev_for_boot; "       \
 374                         "fi; "                                  \
 375                 "done\0"                                        \
 376         "boot_a_script="                                        \
 377                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 378                 "${scriptaddr} ${prefix}${script}; "            \
 379         "env exists secureboot && load ${devtype} "             \
 380                 "${devnum}:${distro_bootpart} "                 \
 381                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 382                 "&& esbc_validate ${scripthdraddr};"            \
 383                 "source ${scriptaddr}\0"                        \
 384         "installer=load mmc 0:2 $load_addr "                    \
 385                 "/flex_installer_arm64.itb; "                   \
 386                 "env exists mcinitcmd && run mcinitcmd && "     \
 387                 "mmc read 0x80001000 0x6800 0x800;"             \
 388                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 389                 "bootm $load_addr#ls1088ardb\0"                 \
 390         "qspi_bootcmd=echo Trying load from qspi..;"            \
 391                 "sf probe && sf read $load_addr "               \
 392                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 393                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 394                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 395                 "bootm $load_addr#$BOARD\0"                     \
 396                 "sd_bootcmd=echo Trying load from sd card..;"           \
 397                 "mmcinfo; mmc read $load_addr "                 \
 398                 "$kernel_addr_sd $kernel_size_sd ;"             \
 399                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 400                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 401                 " && esbc_validate ${kernelheader_addr_r};"     \
 402                 "bootm $load_addr#$BOARD\0"
 403 #endif /* CONFIG_TFABOOT */
 404
 405 #ifdef CONFIG_TFABOOT
 406 #define QSPI_NOR_BOOTCOMMAND                                    \
 407         "sf read 0x80001000 0xd00000 0x100000;"         \
 408                 "env exists mcinitcmd && env exists secureboot "        \
 409                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 410                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 411                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 412                 "run distro_bootcmd;run qspi_bootcmd;"          \
 413                 "env exists secureboot && esbc_halt;"
 414 #define SD_BOOTCOMMAND                                          \
 415                 "env exists mcinitcmd && mmcinfo; "             \
 416                 "mmc read 0x80001000 0x6800 0x800; "            \
 417                 "env exists mcinitcmd && env exists secureboot "        \
 418                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 419                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 420                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 421                 "run distro_bootcmd;run sd_bootcmd;"            \
 422                 "env exists secureboot && esbc_halt;"
 423 #else
 424 #if defined(CONFIG_QSPI_BOOT)
 425 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 426
 427 /* Try to boot an on-SD kernel first, then do normal distro boot */
 428 #endif
 429 #endif /* CONFIG_TFABOOT */
 430
 431 /* MAC/PHY configuration */
 432 #ifdef CONFIG_FSL_MC_ENET
 433 #define AQ_PHY_ADDR1                    0x00
 434 #define AQR105_IRQ_MASK                 0x00000004
 435
 436 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 437 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 438 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 439 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 440 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 441 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 442 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 443 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 444 #endif
 445 #endif
 446
 447 #ifndef SPL_NO_ENV
 448
 449 #define BOOT_TARGET_DEVICES(func) \
 450         func(MMC, mmc, 0) \
 451         func(USB, usb, 0) \
 452         func(SCSI, scsi, 0) \
 453         func(DHCP, dhcp, na)
 454 #include <config_distro_bootcmd.h>
 455 #endif
 456
 457 #include <asm/fsl_secure_boot.h>
 458
 459 #endif /* __LS1088A_RDB_H */