include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #ifdef CONFIG_TFABOOT
  12 #define CONFIG_SYS_MMC_ENV_DEV          0
  13 #else
  14 #if defined(CONFIG_QSPI_BOOT)
  15 #elif defined(CONFIG_SD_BOOT)
  16 #define CONFIG_SYS_MMC_ENV_DEV          0
  17 #else
  18 #define CONFIG_ENV_IS_IN_FLASH
  19 #endif
  20 #endif /* CONFIG_TFABOOT */
  21
  22 #if defined(CONFIG_TFABOOT) || \
  23         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  24 #ifndef CONFIG_SPL_BUILD
  25 #define CONFIG_QIXIS_I2C_ACCESS
  26 #endif
  27 #define SYS_NO_FLASH
  28 #undef CONFIG_CMD_IMLS
  29 #endif
  30
  31 #define CONFIG_SYS_CLK_FREQ             100000000
  32 #define CONFIG_DDR_CLK_FREQ             100000000
  33 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  34 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  35
  36 #define CONFIG_DDR_SPD
  37 #ifdef CONFIG_EMU
  38 #define CONFIG_SYS_FSL_DDR_EMU
  39 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  40 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  41 #else
  42 #define CONFIG_DDR_ECC
  43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  44 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  45 #endif
  46 #define SPD_EEPROM_ADDRESS      0x51
  47 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  48 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  49
  50
  51 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  52 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  53 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  54 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  55
  56 #define CONFIG_SYS_NOR0_CSPR                                    \
  57         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  58         CSPR_PORT_SIZE_16                                       | \
  59         CSPR_MSEL_NOR                                           | \
  60         CSPR_V)
  61 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  62         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  63         CSPR_PORT_SIZE_16                                       | \
  64         CSPR_MSEL_NOR                                           | \
  65         CSPR_V)
  66 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  67 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  68                                 FTIM0_NOR_TEADC(0x1) | \
  69                                 FTIM0_NOR_TEAHC(0x1))
  70 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  71                                 FTIM1_NOR_TRAD_NOR(0x1))
  72 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  73                                 FTIM2_NOR_TCH(0x0) | \
  74                                 FTIM2_NOR_TWP(0x1))
  75 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  76 #define CONFIG_SYS_IFC_CCR      0x01000000
  77
  78 #ifndef SYS_NO_FLASH
  79 #define CONFIG_SYS_FLASH_QUIET_TEST
  80 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  81
  82 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  83 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  84 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  85 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  86
  87 #define CONFIG_SYS_FLASH_EMPTY_INFO
  88 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  89 #endif
  90 #endif
  91
  92 #ifndef SPL_NO_IFC
  93 #define CONFIG_NAND_FSL_IFC
  94 #endif
  95
  96 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  97 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  98
  99 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 100 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 101                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 102                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 103                                 | CSPR_V)
 104 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 105
 106 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 107                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 108                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 109                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 110                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 111                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 112                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 113
 114 #define CONFIG_SYS_NAND_ONFI_DETECTION
 115
 116 /* ONFI NAND Flash mode0 Timing Params */
 117 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 118                                         FTIM0_NAND_TWP(0x18)   | \
 119                                         FTIM0_NAND_TWCHT(0x07) | \
 120                                         FTIM0_NAND_TWH(0x0a))
 121 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 122                                         FTIM1_NAND_TWBE(0x39)  | \
 123                                         FTIM1_NAND_TRR(0x0e)   | \
 124                                         FTIM1_NAND_TRP(0x18))
 125 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 126                                         FTIM2_NAND_TREH(0x0a) | \
 127                                         FTIM2_NAND_TWHRE(0x1e))
 128 #define CONFIG_SYS_NAND_FTIM3           0x0
 129
 130 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 131 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 132 #define CONFIG_MTD_NAND_VERIFY_WRITE
 133 #define CONFIG_CMD_NAND
 134
 135 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 136
 137 #ifndef SPL_NO_QIXIS
 138 #define CONFIG_FSL_QIXIS
 139 #endif
 140
 141 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 142 #define QIXIS_BRDCFG4_OFFSET            0x54
 143 #define QIXIS_LBMAP_SWITCH              2
 144 #define QIXIS_QMAP_MASK                 0xe0
 145 #define QIXIS_QMAP_SHIFT                5
 146 #define QIXIS_LBMAP_MASK                0x1f
 147 #define QIXIS_LBMAP_SHIFT               5
 148 #define QIXIS_LBMAP_DFLTBANK            0x00
 149 #define QIXIS_LBMAP_ALTBANK             0x20
 150 #define QIXIS_LBMAP_SD                  0x00
 151 #define QIXIS_LBMAP_EMMC                0x00
 152 #define QIXIS_LBMAP_SD_QSPI             0x00
 153 #define QIXIS_LBMAP_QSPI                0x00
 154 #define QIXIS_RCW_SRC_SD                0x40
 155 #define QIXIS_RCW_SRC_EMMC              0x41
 156 #define QIXIS_RCW_SRC_QSPI              0x62
 157 #define QIXIS_RST_CTL_RESET             0x31
 158 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 159 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 160 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 161 #define QIXIS_RST_FORCE_MEM             0x01
 162
 163 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 164 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 165                                         | CSPR_PORT_SIZE_8 \
 166                                         | CSPR_MSEL_GPCM \
 167                                         | CSPR_V)
 168 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 169                                         | CSPR_PORT_SIZE_8 \
 170                                         | CSPR_MSEL_GPCM \
 171                                         | CSPR_V)
 172
 173 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 174 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 175 /* QIXIS Timing parameters*/
 176 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 177                                         FTIM0_GPCM_TEADC(0x0e) | \
 178                                         FTIM0_GPCM_TEAHC(0x0e))
 179 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 180                                         FTIM1_GPCM_TRAD(0x3f))
 181 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 182                                         FTIM2_GPCM_TCH(0xf) | \
 183                                         FTIM2_GPCM_TWP(0x3E))
 184 #define SYS_FPGA_CS_FTIM3       0x0
 185
 186 #if defined(CONFIG_TFABOOT) || \
 187         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 188 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 189 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 190 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 191 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 192 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 193 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 194 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 195 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 196 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 197 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 198 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 199 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 200 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 201 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 202 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 203 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 204 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 205 #else
 206 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 208 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 209 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 210 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 211 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 212 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 213 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 214 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 215 #endif
 216
 217 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 218
 219 #define I2C_MUX_CH_VOL_MONITOR          0xA
 220 /* Voltage monitor on channel 2*/
 221 #define I2C_VOL_MONITOR_ADDR           0x63
 222 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 223 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 224 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 225 #define I2C_SVDD_MONITOR_ADDR           0x4F
 226
 227 #define CONFIG_VID_FLS_ENV              "ls1088ardb_vdd_mv"
 228 #define CONFIG_VID
 229
 230 /* The lowest and highest voltage allowed for LS1088ARDB */
 231 #define VDD_MV_MIN                      819
 232 #define VDD_MV_MAX                      1212
 233
 234 #define CONFIG_VOL_MONITOR_LTC3882_SET
 235 #define CONFIG_VOL_MONITOR_LTC3882_READ
 236
 237 /* PM Bus commands code for LTC3882*/
 238 #define PMBUS_CMD_PAGE                  0x0
 239 #define PMBUS_CMD_READ_VOUT             0x8B
 240 #define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
 241 #define PMBUS_CMD_VOUT_COMMAND          0x21
 242
 243 #define PWM_CHANNEL0                    0x0
 244
 245 /*
 246  * I2C bus multiplexer
 247  */
 248 #define I2C_MUX_PCA_ADDR_PRI            0x77
 249 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 250 #define I2C_RETIMER_ADDR                0x18
 251 #define I2C_MUX_CH_DEFAULT              0x8
 252 #define I2C_MUX_CH5                     0xD
 253
 254 #ifndef SPL_NO_RTC
 255 /*
 256 * RTC configuration
 257 */
 258 #define RTC
 259 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 260 #endif
 261
 262 /* EEPROM */
 263 #define CONFIG_ID_EEPROM
 264 #define CONFIG_SYS_I2C_EEPROM_NXID
 265 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 266 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 267 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 268 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 270
 271 #ifndef SPL_NO_QSPI
 272 /* QSPI device */
 273 #if defined(CONFIG_TFABOOT) || \
 274         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 275 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 276 #define FSL_QSPI_FLASH_NUM              2
 277 #endif
 278 #endif
 279
 280 #define CONFIG_CMD_MEMINFO
 281
 282 #ifdef CONFIG_SPL_BUILD
 283 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 284 #else
 285 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 286 #endif
 287
 288 #define CONFIG_FSL_MEMAC
 289
 290 #ifndef SPL_NO_ENV
 291 /* Initial environment variables */
 292 #ifdef CONFIG_TFABOOT
 293 #define QSPI_MC_INIT_CMD                                \
 294         "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"    \
 295         "sf read 0x80100000 0xE00000 0x100000;"                         \
 296         "env exists secureboot && "                     \
 297         "sf read 0x80640000 0x640000 0x40000 && "       \
 298         "sf read 0x80680000 0x680000 0x40000 && "       \
 299         "esbc_validate 0x80640000 && "                  \
 300         "esbc_validate 0x80680000 ;"                    \
 301         "fsl_mc start mc 0x80000000 0x80100000\0"
 302 #define SD_MC_INIT_CMD                          \
 303         "mmcinfo;mmc read 0x80000000 0x5000 0x800;"             \
 304         "mmc read 0x80100000 0x7000 0x800;"                             \
 305         "env exists secureboot && "                     \
 306         "mmc read 0x80640000 0x3200 0x20 && "           \
 307         "mmc read 0x80680000 0x3400 0x20 && "           \
 308         "esbc_validate 0x80640000 && "                  \
 309         "esbc_validate 0x80680000 ;"                    \
 310         "fsl_mc start mc 0x80000000 0x80100000\0"
 311 #else
 312 #if defined(CONFIG_QSPI_BOOT)
 313 #define MC_INIT_CMD                             \
 314         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 315         "sf read 0x80100000 0xE00000 0x100000;"                         \
 316         "env exists secureboot && "                     \
 317         "sf read 0x80640000 0x640000 0x40000 && "       \
 318         "sf read 0x80680000 0x680000 0x40000 && "       \
 319         "esbc_validate 0x80640000 && "                  \
 320         "esbc_validate 0x80680000 ;"                    \
 321         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 322         "mcmemsize=0x70000000\0"
 323 #elif defined(CONFIG_SD_BOOT)
 324 #define MC_INIT_CMD                             \
 325         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"           \
 326         "mmc read 0x80100000 0x7000 0x800;"                             \
 327         "env exists secureboot && "                     \
 328         "mmc read 0x80640000 0x3200 0x20 && "           \
 329         "mmc read 0x80680000 0x3400 0x20 && "           \
 330         "esbc_validate 0x80640000 && "                  \
 331         "esbc_validate 0x80680000 ;"                    \
 332         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 333         "mcmemsize=0x70000000\0"
 334 #endif
 335 #endif /* CONFIG_TFABOOT */
 336
 337 #undef CONFIG_EXTRA_ENV_SETTINGS
 338 #ifdef CONFIG_TFABOOT
 339 #define CONFIG_EXTRA_ENV_SETTINGS               \
 340         "BOARD=ls1088ardb\0"                    \
 341         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 342         "ramdisk_addr=0x800000\0"               \
 343         "ramdisk_size=0x2000000\0"              \
 344         "fdt_high=0xa0000000\0"                 \
 345         "initrd_high=0xffffffffffffffff\0"      \
 346         "fdt_addr=0x64f00000\0"                 \
 347         "kernel_addr=0x1000000\0"               \
 348         "kernel_addr_sd=0x8000\0"               \
 349         "kernelhdr_addr_sd=0x3000\0"            \
 350         "kernel_start=0x580100000\0"            \
 351         "kernelheader_start=0x580600000\0"      \
 352         "scriptaddr=0x80000000\0"               \
 353         "scripthdraddr=0x80080000\0"            \
 354         "fdtheader_addr_r=0x80100000\0"         \
 355         "kernelheader_addr=0x600000\0"          \
 356         "kernelheader_addr_r=0x80200000\0"      \
 357         "kernel_addr_r=0x81000000\0"            \
 358         "kernelheader_size=0x40000\0"           \
 359         "fdt_addr_r=0x90000000\0"               \
 360         "load_addr=0xa0000000\0"                \
 361         "kernel_size=0x2800000\0"               \
 362         "kernel_size_sd=0x14000\0"              \
 363         "kernelhdr_size_sd=0x20\0"              \
 364         QSPI_MC_INIT_CMD                        \
 365         "mcmemsize=0x70000000\0"                \
 366         BOOTENV                                 \
 367         "boot_scripts=ls1088ardb_boot.scr\0"    \
 368         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 369         "scan_dev_for_boot_part="               \
 370                 "part list ${devtype} ${devnum} devplist; "     \
 371                 "env exists devplist || setenv devplist 1; "    \
 372                 "for distro_bootpart in ${devplist}; do "       \
 373                         "if fstype ${devtype} "                 \
 374                                 "${devnum}:${distro_bootpart} " \
 375                                 "bootfstype; then "             \
 376                                 "run scan_dev_for_boot; "       \
 377                         "fi; "                                  \
 378                 "done\0"                                        \
 379         "boot_a_script="                                        \
 380                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 381                 "${scriptaddr} ${prefix}${script}; "            \
 382         "env exists secureboot && load ${devtype} "             \
 383                 "${devnum}:${distro_bootpart} "                 \
 384                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 385                 "env exists secureboot "                        \
 386                 "&& esbc_validate ${scripthdraddr};"            \
 387                 "source ${scriptaddr}\0"                        \
 388         "installer=load mmc 0:2 $load_addr "                    \
 389                 "/flex_installer_arm64.itb; "                   \
 390                 "env exists mcinitcmd && run mcinitcmd && "     \
 391                 "mmc read 0x80001000 0x6800 0x800;"             \
 392                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 393                 "bootm $load_addr#ls1088ardb\0"                 \
 394         "qspi_bootcmd=echo Trying load from qspi..;"            \
 395                 "sf probe && sf read $load_addr "               \
 396                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 397                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 398                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 399                 "bootm $load_addr#$BOARD\0"                     \
 400                 "sd_bootcmd=echo Trying load from sd card..;"           \
 401                 "mmcinfo; mmc read $load_addr "                 \
 402                 "$kernel_addr_sd $kernel_size_sd ;"             \
 403                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 404                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 405                 " && esbc_validate ${kernelheader_addr_r};"     \
 406                 "bootm $load_addr#$BOARD\0"
 407 #else
 408 #define CONFIG_EXTRA_ENV_SETTINGS               \
 409         "BOARD=ls1088ardb\0"                    \
 410         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 411         "ramdisk_addr=0x800000\0"               \
 412         "ramdisk_size=0x2000000\0"              \
 413         "fdt_high=0xa0000000\0"                 \
 414         "initrd_high=0xffffffffffffffff\0"      \
 415         "fdt_addr=0x64f00000\0"                 \
 416         "kernel_addr=0x1000000\0"               \
 417         "kernel_addr_sd=0x8000\0"               \
 418         "kernelhdr_addr_sd=0x3000\0"            \
 419         "kernel_start=0x580100000\0"            \
 420         "kernelheader_start=0x580800000\0"      \
 421         "scriptaddr=0x80000000\0"               \
 422         "scripthdraddr=0x80080000\0"            \
 423         "fdtheader_addr_r=0x80100000\0"         \
 424         "kernelheader_addr=0x600000\0"          \
 425         "kernelheader_addr_r=0x80200000\0"      \
 426         "kernel_addr_r=0x81000000\0"            \
 427         "kernelheader_size=0x40000\0"           \
 428         "fdt_addr_r=0x90000000\0"               \
 429         "load_addr=0xa0000000\0"                \
 430         "kernel_size=0x2800000\0"               \
 431         "kernel_size_sd=0x14000\0"              \
 432         "kernelhdr_size_sd=0x20\0"              \
 433         MC_INIT_CMD                             \
 434         BOOTENV                                 \
 435         "boot_scripts=ls1088ardb_boot.scr\0"    \
 436         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 437         "scan_dev_for_boot_part="               \
 438                 "part list ${devtype} ${devnum} devplist; "     \
 439                 "env exists devplist || setenv devplist 1; "    \
 440                 "for distro_bootpart in ${devplist}; do "       \
 441                         "if fstype ${devtype} "                 \
 442                                 "${devnum}:${distro_bootpart} " \
 443                                 "bootfstype; then "             \
 444                                 "run scan_dev_for_boot; "       \
 445                         "fi; "                                  \
 446                 "done\0"                                        \
 447         "boot_a_script="                                        \
 448                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 449                 "${scriptaddr} ${prefix}${script}; "            \
 450         "env exists secureboot && load ${devtype} "             \
 451                 "${devnum}:${distro_bootpart} "                 \
 452                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 453                 "&& esbc_validate ${scripthdraddr};"            \
 454                 "source ${scriptaddr}\0"                        \
 455         "installer=load mmc 0:2 $load_addr "                    \
 456                 "/flex_installer_arm64.itb; "                   \
 457                 "env exists mcinitcmd && run mcinitcmd && "     \
 458                 "mmc read 0x80001000 0x6800 0x800;"             \
 459                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 460                 "bootm $load_addr#ls1088ardb\0"                 \
 461         "qspi_bootcmd=echo Trying load from qspi..;"            \
 462                 "sf probe && sf read $load_addr "               \
 463                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 464                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 465                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 466                 "bootm $load_addr#$BOARD\0"                     \
 467                 "sd_bootcmd=echo Trying load from sd card..;"           \
 468                 "mmcinfo; mmc read $load_addr "                 \
 469                 "$kernel_addr_sd $kernel_size_sd ;"             \
 470                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 471                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 472                 " && esbc_validate ${kernelheader_addr_r};"     \
 473                 "bootm $load_addr#$BOARD\0"
 474 #endif /* CONFIG_TFABOOT */
 475
 476 #undef CONFIG_BOOTCOMMAND
 477 #ifdef CONFIG_TFABOOT
 478 #define QSPI_NOR_BOOTCOMMAND                                    \
 479         "sf read 0x80001000 0xd00000 0x100000;"         \
 480                 "env exists mcinitcmd && env exists secureboot "        \
 481                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 482                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 483                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 484                 "run distro_bootcmd;run qspi_bootcmd;"          \
 485                 "env exists secureboot && esbc_halt;"
 486 #define SD_BOOTCOMMAND                                          \
 487                 "env exists mcinitcmd && mmcinfo; "             \
 488                 "mmc read 0x80001000 0x6800 0x800; "            \
 489                 "env exists mcinitcmd && env exists secureboot "        \
 490                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 491                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 492                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 493                 "run distro_bootcmd;run sd_bootcmd;"            \
 494                 "env exists secureboot && esbc_halt;"
 495 #else
 496 #if defined(CONFIG_QSPI_BOOT)
 497 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 498 #define CONFIG_BOOTCOMMAND                                      \
 499                 "sf read 0x80001000 0xd00000 0x100000;"         \
 500                 "env exists mcinitcmd && env exists secureboot "        \
 501                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 502                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 503                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 504                 "run distro_bootcmd;run qspi_bootcmd;"          \
 505                 "env exists secureboot && esbc_halt;"
 506
 507 /* Try to boot an on-SD kernel first, then do normal distro boot */
 508 #elif defined(CONFIG_SD_BOOT)
 509 #define CONFIG_BOOTCOMMAND                                      \
 510                 "env exists mcinitcmd && mmcinfo; "             \
 511                 "mmc read 0x80001000 0x6800 0x800; "            \
 512                 "env exists mcinitcmd && env exists secureboot "        \
 513                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 514                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 515                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 516                 "run distro_bootcmd;run sd_bootcmd;"            \
 517                 "env exists secureboot && esbc_halt;"
 518 #endif
 519 #endif /* CONFIG_TFABOOT */
 520
 521 /* MAC/PHY configuration */
 522 #ifdef CONFIG_FSL_MC_ENET
 523 #define AQ_PHY_ADDR1                    0x00
 524 #define AQR105_IRQ_MASK                 0x00000004
 525
 526 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 527 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 528 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 529 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 530 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 531 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 532 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 533 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 534
 535 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 536 #define CONFIG_PHY_GIGE
 537 #endif
 538 #endif
 539
 540 /*  MMC  */
 541 #ifdef CONFIG_MMC
 542 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 543 #endif
 544
 545 #ifndef SPL_NO_ENV
 546
 547 #define BOOT_TARGET_DEVICES(func) \
 548         func(MMC, mmc, 0) \
 549         func(SCSI, scsi, 0) \
 550         func(DHCP, dhcp, na)
 551 #include <config_distro_bootcmd.h>
 552 #endif
 553
 554 #include <asm/fsl_secure_boot.h>
 555
 556 #endif /* __LS1088A_RDB_H */