1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_CLK_FREQ 100000000
20 #define CONFIG_DDR_CLK_FREQ 100000000
21 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
22 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
24 #define CONFIG_DDR_SPD
26 #define CONFIG_SYS_FSL_DDR_EMU
28 #define CONFIG_DDR_ECC
29 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
30 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #define SPD_EEPROM_ADDRESS 0x51
33 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
34 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
37 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
38 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
39 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
40 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
42 #define CONFIG_SYS_NOR0_CSPR \
43 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
47 #define CONFIG_SYS_NOR0_CSPR_EARLY \
48 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
52 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
53 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
54 FTIM0_NOR_TEADC(0x1) | \
56 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
57 FTIM1_NOR_TRAD_NOR(0x1))
58 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
59 FTIM2_NOR_TCH(0x0) | \
61 #define CONFIG_SYS_NOR_FTIM3 0x04000000
62 #define CONFIG_SYS_IFC_CCR 0x01000000
65 #define CONFIG_SYS_FLASH_QUIET_TEST
66 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
68 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
69 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
70 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
71 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
73 #define CONFIG_SYS_FLASH_EMPTY_INFO
74 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
79 #define CONFIG_NAND_FSL_IFC
82 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
83 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
85 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
86 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
87 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
88 | CSPR_MSEL_NAND /* MSEL = NAND */ \
90 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
92 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
93 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
94 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
95 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
96 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
97 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
98 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
100 #define CONFIG_SYS_NAND_ONFI_DETECTION
102 /* ONFI NAND Flash mode0 Timing Params */
103 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
104 FTIM0_NAND_TWP(0x18) | \
105 FTIM0_NAND_TWCHT(0x07) | \
106 FTIM0_NAND_TWH(0x0a))
107 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
108 FTIM1_NAND_TWBE(0x39) | \
109 FTIM1_NAND_TRR(0x0e) | \
110 FTIM1_NAND_TRP(0x18))
111 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
112 FTIM2_NAND_TREH(0x0a) | \
113 FTIM2_NAND_TWHRE(0x1e))
114 #define CONFIG_SYS_NAND_FTIM3 0x0
116 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
117 #define CONFIG_SYS_MAX_NAND_DEVICE 1
118 #define CONFIG_MTD_NAND_VERIFY_WRITE
120 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
123 #define CONFIG_FSL_QIXIS
126 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
127 #define QIXIS_BRDCFG4_OFFSET 0x54
128 #define QIXIS_LBMAP_SWITCH 2
129 #define QIXIS_QMAP_MASK 0xe0
130 #define QIXIS_QMAP_SHIFT 5
131 #define QIXIS_LBMAP_MASK 0x1f
132 #define QIXIS_LBMAP_SHIFT 5
133 #define QIXIS_LBMAP_DFLTBANK 0x00
134 #define QIXIS_LBMAP_ALTBANK 0x20
135 #define QIXIS_LBMAP_SD 0x00
136 #define QIXIS_LBMAP_EMMC 0x00
137 #define QIXIS_LBMAP_SD_QSPI 0x00
138 #define QIXIS_LBMAP_QSPI 0x00
139 #define QIXIS_RCW_SRC_SD 0x40
140 #define QIXIS_RCW_SRC_EMMC 0x41
141 #define QIXIS_RCW_SRC_QSPI 0x62
142 #define QIXIS_RST_CTL_RESET 0x31
143 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
144 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
145 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
146 #define QIXIS_RST_FORCE_MEM 0x01
148 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
149 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
153 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
158 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
159 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
160 /* QIXIS Timing parameters*/
161 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
162 FTIM0_GPCM_TEADC(0x0e) | \
163 FTIM0_GPCM_TEAHC(0x0e))
164 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
165 FTIM1_GPCM_TRAD(0x3f))
166 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
167 FTIM2_GPCM_TCH(0xf) | \
168 FTIM2_GPCM_TWP(0x3E))
169 #define SYS_FPGA_CS_FTIM3 0x0
171 #if defined(CONFIG_TFABOOT) || \
172 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
173 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
174 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
175 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
176 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
177 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
178 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
179 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
180 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
181 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
182 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
183 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
184 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
185 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
186 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
187 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
188 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
189 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
191 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
192 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
193 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
194 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
195 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
196 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
197 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
198 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
199 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
202 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
204 #define I2C_MUX_CH_VOL_MONITOR 0xA
205 /* Voltage monitor on channel 2*/
206 #define I2C_VOL_MONITOR_ADDR 0x63
207 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
208 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
209 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
210 #define I2C_SVDD_MONITOR_ADDR 0x4F
212 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
215 /* The lowest and highest voltage allowed for LS1088ARDB */
216 #define VDD_MV_MIN 819
217 #define VDD_MV_MAX 1212
219 #define CONFIG_VOL_MONITOR_LTC3882_SET
220 #define CONFIG_VOL_MONITOR_LTC3882_READ
222 #define PWM_CHANNEL0 0x0
225 * I2C bus multiplexer
227 #define I2C_MUX_PCA_ADDR_PRI 0x77
228 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
229 #define I2C_RETIMER_ADDR 0x18
230 #define I2C_MUX_CH_DEFAULT 0x8
231 #define I2C_MUX_CH5 0xD
238 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
242 #define CONFIG_SYS_I2C_EEPROM_NXID
243 #define CONFIG_SYS_EEPROM_BUS_NUM 0
245 #ifdef CONFIG_SPL_BUILD
246 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
251 #define CONFIG_FSL_MEMAC
254 /* Initial environment variables */
255 #ifdef CONFIG_TFABOOT
256 #define QSPI_MC_INIT_CMD \
257 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
258 "sf read 0x80e00000 0xE00000 0x100000;" \
259 "env exists secureboot && " \
260 "sf read 0x80640000 0x640000 0x40000 && " \
261 "sf read 0x80680000 0x680000 0x40000 && " \
262 "esbc_validate 0x80640000 && " \
263 "esbc_validate 0x80680000 ;" \
264 "fsl_mc start mc 0x80a00000 0x80e00000\0"
265 #define SD_MC_INIT_CMD \
266 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
267 "mmc read 0x80e00000 0x7000 0x800;" \
268 "env exists secureboot && " \
269 "mmc read 0x80640000 0x3200 0x20 && " \
270 "mmc read 0x80680000 0x3400 0x20 && " \
271 "esbc_validate 0x80640000 && " \
272 "esbc_validate 0x80680000 ;" \
273 "fsl_mc start mc 0x80a00000 0x80e00000\0"
275 #if defined(CONFIG_QSPI_BOOT)
276 #define MC_INIT_CMD \
277 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
278 "sf read 0x80e00000 0xE00000 0x100000;" \
279 "env exists secureboot && " \
280 "sf read 0x80640000 0x640000 0x40000 && " \
281 "sf read 0x80680000 0x680000 0x40000 && " \
282 "esbc_validate 0x80640000 && " \
283 "esbc_validate 0x80680000 ;" \
284 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
285 "mcmemsize=0x70000000\0"
286 #elif defined(CONFIG_SD_BOOT)
287 #define MC_INIT_CMD \
288 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
289 "mmc read 0x80e00000 0x7000 0x800;" \
290 "env exists secureboot && " \
291 "mmc read 0x80640000 0x3200 0x20 && " \
292 "mmc read 0x80680000 0x3400 0x20 && " \
293 "esbc_validate 0x80640000 && " \
294 "esbc_validate 0x80680000 ;" \
295 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
296 "mcmemsize=0x70000000\0"
298 #endif /* CONFIG_TFABOOT */
300 #undef CONFIG_EXTRA_ENV_SETTINGS
301 #ifdef CONFIG_TFABOOT
302 #define CONFIG_EXTRA_ENV_SETTINGS \
303 "BOARD=ls1088ardb\0" \
304 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
305 "ramdisk_addr=0x800000\0" \
306 "ramdisk_size=0x2000000\0" \
307 "fdt_high=0xa0000000\0" \
308 "initrd_high=0xffffffffffffffff\0" \
309 "fdt_addr=0x64f00000\0" \
310 "kernel_addr=0x1000000\0" \
311 "kernel_addr_sd=0x8000\0" \
312 "kernelhdr_addr_sd=0x3000\0" \
313 "kernel_start=0x580100000\0" \
314 "kernelheader_start=0x580600000\0" \
315 "scriptaddr=0x80000000\0" \
316 "scripthdraddr=0x80080000\0" \
317 "fdtheader_addr_r=0x80100000\0" \
318 "kernelheader_addr=0x600000\0" \
319 "kernelheader_addr_r=0x80200000\0" \
320 "kernel_addr_r=0x81000000\0" \
321 "kernelheader_size=0x40000\0" \
322 "fdt_addr_r=0x90000000\0" \
323 "load_addr=0xa0000000\0" \
324 "kernel_size=0x2800000\0" \
325 "kernel_size_sd=0x14000\0" \
326 "kernelhdr_size_sd=0x20\0" \
328 "mcmemsize=0x70000000\0" \
330 "boot_scripts=ls1088ardb_boot.scr\0" \
331 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
332 "scan_dev_for_boot_part=" \
333 "part list ${devtype} ${devnum} devplist; " \
334 "env exists devplist || setenv devplist 1; " \
335 "for distro_bootpart in ${devplist}; do " \
336 "if fstype ${devtype} " \
337 "${devnum}:${distro_bootpart} " \
338 "bootfstype; then " \
339 "run scan_dev_for_boot; " \
343 "load ${devtype} ${devnum}:${distro_bootpart} " \
344 "${scriptaddr} ${prefix}${script}; " \
345 "env exists secureboot && load ${devtype} " \
346 "${devnum}:${distro_bootpart} " \
347 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
348 "env exists secureboot " \
349 "&& esbc_validate ${scripthdraddr};" \
350 "source ${scriptaddr}\0" \
351 "installer=load mmc 0:2 $load_addr " \
352 "/flex_installer_arm64.itb; " \
353 "env exists mcinitcmd && run mcinitcmd && " \
354 "mmc read 0x80001000 0x6800 0x800;" \
355 "fsl_mc lazyapply dpl 0x80001000;" \
356 "bootm $load_addr#ls1088ardb\0" \
357 "qspi_bootcmd=echo Trying load from qspi..;" \
358 "sf probe && sf read $load_addr " \
359 "$kernel_addr $kernel_size ; env exists secureboot " \
360 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
361 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
362 "bootm $load_addr#$BOARD\0" \
363 "sd_bootcmd=echo Trying load from sd card..;" \
364 "mmcinfo; mmc read $load_addr " \
365 "$kernel_addr_sd $kernel_size_sd ;" \
366 "env exists secureboot && mmc read $kernelheader_addr_r "\
367 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
368 " && esbc_validate ${kernelheader_addr_r};" \
369 "bootm $load_addr#$BOARD\0"
371 #define CONFIG_EXTRA_ENV_SETTINGS \
372 "BOARD=ls1088ardb\0" \
373 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
374 "ramdisk_addr=0x800000\0" \
375 "ramdisk_size=0x2000000\0" \
376 "fdt_high=0xa0000000\0" \
377 "initrd_high=0xffffffffffffffff\0" \
378 "fdt_addr=0x64f00000\0" \
379 "kernel_addr=0x1000000\0" \
380 "kernel_addr_sd=0x8000\0" \
381 "kernelhdr_addr_sd=0x3000\0" \
382 "kernel_start=0x580100000\0" \
383 "kernelheader_start=0x580800000\0" \
384 "scriptaddr=0x80000000\0" \
385 "scripthdraddr=0x80080000\0" \
386 "fdtheader_addr_r=0x80100000\0" \
387 "kernelheader_addr=0x600000\0" \
388 "kernelheader_addr_r=0x80200000\0" \
389 "kernel_addr_r=0x81000000\0" \
390 "kernelheader_size=0x40000\0" \
391 "fdt_addr_r=0x90000000\0" \
392 "load_addr=0xa0000000\0" \
393 "kernel_size=0x2800000\0" \
394 "kernel_size_sd=0x14000\0" \
395 "kernelhdr_size_sd=0x20\0" \
398 "boot_scripts=ls1088ardb_boot.scr\0" \
399 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
400 "scan_dev_for_boot_part=" \
401 "part list ${devtype} ${devnum} devplist; " \
402 "env exists devplist || setenv devplist 1; " \
403 "for distro_bootpart in ${devplist}; do " \
404 "if fstype ${devtype} " \
405 "${devnum}:${distro_bootpart} " \
406 "bootfstype; then " \
407 "run scan_dev_for_boot; " \
411 "load ${devtype} ${devnum}:${distro_bootpart} " \
412 "${scriptaddr} ${prefix}${script}; " \
413 "env exists secureboot && load ${devtype} " \
414 "${devnum}:${distro_bootpart} " \
415 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
416 "&& esbc_validate ${scripthdraddr};" \
417 "source ${scriptaddr}\0" \
418 "installer=load mmc 0:2 $load_addr " \
419 "/flex_installer_arm64.itb; " \
420 "env exists mcinitcmd && run mcinitcmd && " \
421 "mmc read 0x80001000 0x6800 0x800;" \
422 "fsl_mc lazyapply dpl 0x80001000;" \
423 "bootm $load_addr#ls1088ardb\0" \
424 "qspi_bootcmd=echo Trying load from qspi..;" \
425 "sf probe && sf read $load_addr " \
426 "$kernel_addr $kernel_size ; env exists secureboot " \
427 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
428 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
429 "bootm $load_addr#$BOARD\0" \
430 "sd_bootcmd=echo Trying load from sd card..;" \
431 "mmcinfo; mmc read $load_addr " \
432 "$kernel_addr_sd $kernel_size_sd ;" \
433 "env exists secureboot && mmc read $kernelheader_addr_r "\
434 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
435 " && esbc_validate ${kernelheader_addr_r};" \
436 "bootm $load_addr#$BOARD\0"
437 #endif /* CONFIG_TFABOOT */
439 #undef CONFIG_BOOTCOMMAND
440 #ifdef CONFIG_TFABOOT
441 #define QSPI_NOR_BOOTCOMMAND \
442 "sf read 0x80001000 0xd00000 0x100000;" \
443 "env exists mcinitcmd && env exists secureboot " \
444 " && sf read 0x806C0000 0x6C0000 0x100000 " \
445 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
446 "&& fsl_mc lazyapply dpl 0x80001000;" \
447 "run distro_bootcmd;run qspi_bootcmd;" \
448 "env exists secureboot && esbc_halt;"
449 #define SD_BOOTCOMMAND \
450 "env exists mcinitcmd && mmcinfo; " \
451 "mmc read 0x80001000 0x6800 0x800; " \
452 "env exists mcinitcmd && env exists secureboot " \
453 " && mmc read 0x806C0000 0x3600 0x20 " \
454 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
455 "&& fsl_mc lazyapply dpl 0x80001000;" \
456 "run distro_bootcmd;run sd_bootcmd;" \
457 "env exists secureboot && esbc_halt;"
459 #if defined(CONFIG_QSPI_BOOT)
460 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
461 #define CONFIG_BOOTCOMMAND \
462 "sf read 0x80001000 0xd00000 0x100000;" \
463 "env exists mcinitcmd && env exists secureboot " \
464 " && sf read 0x806C0000 0x6C0000 0x100000 " \
465 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
466 "&& fsl_mc lazyapply dpl 0x80001000;" \
467 "run distro_bootcmd;run qspi_bootcmd;" \
468 "env exists secureboot && esbc_halt;"
470 /* Try to boot an on-SD kernel first, then do normal distro boot */
471 #elif defined(CONFIG_SD_BOOT)
472 #define CONFIG_BOOTCOMMAND \
473 "env exists mcinitcmd && mmcinfo; " \
474 "mmc read 0x80001000 0x6800 0x800; " \
475 "env exists mcinitcmd && env exists secureboot " \
476 " && mmc read 0x806C0000 0x3600 0x20 " \
477 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
478 "&& fsl_mc lazyapply dpl 0x80001000;" \
479 "run distro_bootcmd;run sd_bootcmd;" \
480 "env exists secureboot && esbc_halt;"
482 #endif /* CONFIG_TFABOOT */
484 /* MAC/PHY configuration */
485 #ifdef CONFIG_FSL_MC_ENET
486 #define AQ_PHY_ADDR1 0x00
487 #define AQR105_IRQ_MASK 0x00000004
489 #define QSGMII1_PORT1_PHY_ADDR 0x0c
490 #define QSGMII1_PORT2_PHY_ADDR 0x0d
491 #define QSGMII1_PORT3_PHY_ADDR 0x0e
492 #define QSGMII1_PORT4_PHY_ADDR 0x0f
493 #define QSGMII2_PORT1_PHY_ADDR 0x1c
494 #define QSGMII2_PORT2_PHY_ADDR 0x1d
495 #define QSGMII2_PORT3_PHY_ADDR 0x1e
496 #define QSGMII2_PORT4_PHY_ADDR 0x1f
498 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
499 #define CONFIG_PHY_GIGE
505 #define BOOT_TARGET_DEVICES(func) \
508 func(SCSI, scsi, 0) \
510 #include <config_distro_bootcmd.h>
513 #include <asm/fsl_secure_boot.h>
515 #endif /* __LS1088A_RDB_H */