1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_CLK_FREQ 100000000
20 #define CONFIG_DDR_CLK_FREQ 100000000
21 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
22 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
24 #define CONFIG_DDR_SPD
26 #define CONFIG_SYS_FSL_DDR_EMU
27 #define CONFIG_SYS_MXC_I2C1_SPEED 40000000
28 #define CONFIG_SYS_MXC_I2C2_SPEED 40000000
30 #define CONFIG_DDR_ECC
31 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
32 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS 0x51
35 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
36 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
39 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
40 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
41 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
42 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
44 #define CONFIG_SYS_NOR0_CSPR \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
49 #define CONFIG_SYS_NOR0_CSPR_EARLY \
50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
54 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
55 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
56 FTIM0_NOR_TEADC(0x1) | \
58 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
59 FTIM1_NOR_TRAD_NOR(0x1))
60 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
61 FTIM2_NOR_TCH(0x0) | \
63 #define CONFIG_SYS_NOR_FTIM3 0x04000000
64 #define CONFIG_SYS_IFC_CCR 0x01000000
67 #define CONFIG_SYS_FLASH_QUIET_TEST
68 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
70 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
71 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
72 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
73 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
75 #define CONFIG_SYS_FLASH_EMPTY_INFO
76 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
81 #define CONFIG_NAND_FSL_IFC
84 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
85 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
87 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
88 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
89 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
90 | CSPR_MSEL_NAND /* MSEL = NAND */ \
92 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
94 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
95 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
96 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
97 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
98 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
99 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
100 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
102 #define CONFIG_SYS_NAND_ONFI_DETECTION
104 /* ONFI NAND Flash mode0 Timing Params */
105 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
106 FTIM0_NAND_TWP(0x18) | \
107 FTIM0_NAND_TWCHT(0x07) | \
108 FTIM0_NAND_TWH(0x0a))
109 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
110 FTIM1_NAND_TWBE(0x39) | \
111 FTIM1_NAND_TRR(0x0e) | \
112 FTIM1_NAND_TRP(0x18))
113 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
114 FTIM2_NAND_TREH(0x0a) | \
115 FTIM2_NAND_TWHRE(0x1e))
116 #define CONFIG_SYS_NAND_FTIM3 0x0
118 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
119 #define CONFIG_SYS_MAX_NAND_DEVICE 1
120 #define CONFIG_MTD_NAND_VERIFY_WRITE
122 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
125 #define CONFIG_FSL_QIXIS
128 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
129 #define QIXIS_BRDCFG4_OFFSET 0x54
130 #define QIXIS_LBMAP_SWITCH 2
131 #define QIXIS_QMAP_MASK 0xe0
132 #define QIXIS_QMAP_SHIFT 5
133 #define QIXIS_LBMAP_MASK 0x1f
134 #define QIXIS_LBMAP_SHIFT 5
135 #define QIXIS_LBMAP_DFLTBANK 0x00
136 #define QIXIS_LBMAP_ALTBANK 0x20
137 #define QIXIS_LBMAP_SD 0x00
138 #define QIXIS_LBMAP_EMMC 0x00
139 #define QIXIS_LBMAP_SD_QSPI 0x00
140 #define QIXIS_LBMAP_QSPI 0x00
141 #define QIXIS_RCW_SRC_SD 0x40
142 #define QIXIS_RCW_SRC_EMMC 0x41
143 #define QIXIS_RCW_SRC_QSPI 0x62
144 #define QIXIS_RST_CTL_RESET 0x31
145 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
146 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
147 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
148 #define QIXIS_RST_FORCE_MEM 0x01
150 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
151 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
155 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
160 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
161 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
162 /* QIXIS Timing parameters*/
163 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
164 FTIM0_GPCM_TEADC(0x0e) | \
165 FTIM0_GPCM_TEAHC(0x0e))
166 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
167 FTIM1_GPCM_TRAD(0x3f))
168 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
169 FTIM2_GPCM_TCH(0xf) | \
170 FTIM2_GPCM_TWP(0x3E))
171 #define SYS_FPGA_CS_FTIM3 0x0
173 #if defined(CONFIG_TFABOOT) || \
174 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
175 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
176 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
177 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
178 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
179 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
180 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
181 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
182 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
183 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
184 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
185 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
186 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
187 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
188 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
189 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
190 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
191 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
193 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
194 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
195 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
196 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
197 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
198 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
199 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
200 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
201 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
206 #define I2C_MUX_CH_VOL_MONITOR 0xA
207 /* Voltage monitor on channel 2*/
208 #define I2C_VOL_MONITOR_ADDR 0x63
209 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
210 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
211 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
212 #define I2C_SVDD_MONITOR_ADDR 0x4F
214 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
217 /* The lowest and highest voltage allowed for LS1088ARDB */
218 #define VDD_MV_MIN 819
219 #define VDD_MV_MAX 1212
221 #define CONFIG_VOL_MONITOR_LTC3882_SET
222 #define CONFIG_VOL_MONITOR_LTC3882_READ
224 #define PWM_CHANNEL0 0x0
227 * I2C bus multiplexer
229 #define I2C_MUX_PCA_ADDR_PRI 0x77
230 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
231 #define I2C_RETIMER_ADDR 0x18
232 #define I2C_MUX_CH_DEFAULT 0x8
233 #define I2C_MUX_CH5 0xD
240 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
244 #define CONFIG_SYS_I2C_EEPROM_NXID
245 #define CONFIG_SYS_EEPROM_BUS_NUM 0
247 #ifdef CONFIG_SPL_BUILD
248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
250 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
253 #define CONFIG_FSL_MEMAC
256 /* Initial environment variables */
257 #ifdef CONFIG_TFABOOT
258 #define QSPI_MC_INIT_CMD \
259 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
260 "sf read 0x80e00000 0xE00000 0x100000;" \
261 "env exists secureboot && " \
262 "sf read 0x80640000 0x640000 0x40000 && " \
263 "sf read 0x80680000 0x680000 0x40000 && " \
264 "esbc_validate 0x80640000 && " \
265 "esbc_validate 0x80680000 ;" \
266 "fsl_mc start mc 0x80a00000 0x80e00000\0"
267 #define SD_MC_INIT_CMD \
268 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
269 "mmc read 0x80e00000 0x7000 0x800;" \
270 "env exists secureboot && " \
271 "mmc read 0x80640000 0x3200 0x20 && " \
272 "mmc read 0x80680000 0x3400 0x20 && " \
273 "esbc_validate 0x80640000 && " \
274 "esbc_validate 0x80680000 ;" \
275 "fsl_mc start mc 0x80a00000 0x80e00000\0"
277 #if defined(CONFIG_QSPI_BOOT)
278 #define MC_INIT_CMD \
279 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
280 "sf read 0x80e00000 0xE00000 0x100000;" \
281 "env exists secureboot && " \
282 "sf read 0x80640000 0x640000 0x40000 && " \
283 "sf read 0x80680000 0x680000 0x40000 && " \
284 "esbc_validate 0x80640000 && " \
285 "esbc_validate 0x80680000 ;" \
286 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
287 "mcmemsize=0x70000000\0"
288 #elif defined(CONFIG_SD_BOOT)
289 #define MC_INIT_CMD \
290 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
291 "mmc read 0x80e00000 0x7000 0x800;" \
292 "env exists secureboot && " \
293 "mmc read 0x80640000 0x3200 0x20 && " \
294 "mmc read 0x80680000 0x3400 0x20 && " \
295 "esbc_validate 0x80640000 && " \
296 "esbc_validate 0x80680000 ;" \
297 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
298 "mcmemsize=0x70000000\0"
300 #endif /* CONFIG_TFABOOT */
302 #undef CONFIG_EXTRA_ENV_SETTINGS
303 #ifdef CONFIG_TFABOOT
304 #define CONFIG_EXTRA_ENV_SETTINGS \
305 "BOARD=ls1088ardb\0" \
306 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
307 "ramdisk_addr=0x800000\0" \
308 "ramdisk_size=0x2000000\0" \
309 "fdt_high=0xa0000000\0" \
310 "initrd_high=0xffffffffffffffff\0" \
311 "fdt_addr=0x64f00000\0" \
312 "kernel_addr=0x1000000\0" \
313 "kernel_addr_sd=0x8000\0" \
314 "kernelhdr_addr_sd=0x3000\0" \
315 "kernel_start=0x580100000\0" \
316 "kernelheader_start=0x580600000\0" \
317 "scriptaddr=0x80000000\0" \
318 "scripthdraddr=0x80080000\0" \
319 "fdtheader_addr_r=0x80100000\0" \
320 "kernelheader_addr=0x600000\0" \
321 "kernelheader_addr_r=0x80200000\0" \
322 "kernel_addr_r=0x81000000\0" \
323 "kernelheader_size=0x40000\0" \
324 "fdt_addr_r=0x90000000\0" \
325 "load_addr=0xa0000000\0" \
326 "kernel_size=0x2800000\0" \
327 "kernel_size_sd=0x14000\0" \
328 "kernelhdr_size_sd=0x20\0" \
330 "mcmemsize=0x70000000\0" \
332 "boot_scripts=ls1088ardb_boot.scr\0" \
333 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
334 "scan_dev_for_boot_part=" \
335 "part list ${devtype} ${devnum} devplist; " \
336 "env exists devplist || setenv devplist 1; " \
337 "for distro_bootpart in ${devplist}; do " \
338 "if fstype ${devtype} " \
339 "${devnum}:${distro_bootpart} " \
340 "bootfstype; then " \
341 "run scan_dev_for_boot; " \
345 "load ${devtype} ${devnum}:${distro_bootpart} " \
346 "${scriptaddr} ${prefix}${script}; " \
347 "env exists secureboot && load ${devtype} " \
348 "${devnum}:${distro_bootpart} " \
349 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
350 "env exists secureboot " \
351 "&& esbc_validate ${scripthdraddr};" \
352 "source ${scriptaddr}\0" \
353 "installer=load mmc 0:2 $load_addr " \
354 "/flex_installer_arm64.itb; " \
355 "env exists mcinitcmd && run mcinitcmd && " \
356 "mmc read 0x80001000 0x6800 0x800;" \
357 "fsl_mc lazyapply dpl 0x80001000;" \
358 "bootm $load_addr#ls1088ardb\0" \
359 "qspi_bootcmd=echo Trying load from qspi..;" \
360 "sf probe && sf read $load_addr " \
361 "$kernel_addr $kernel_size ; env exists secureboot " \
362 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
363 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
364 "bootm $load_addr#$BOARD\0" \
365 "sd_bootcmd=echo Trying load from sd card..;" \
366 "mmcinfo; mmc read $load_addr " \
367 "$kernel_addr_sd $kernel_size_sd ;" \
368 "env exists secureboot && mmc read $kernelheader_addr_r "\
369 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
370 " && esbc_validate ${kernelheader_addr_r};" \
371 "bootm $load_addr#$BOARD\0"
373 #define CONFIG_EXTRA_ENV_SETTINGS \
374 "BOARD=ls1088ardb\0" \
375 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
376 "ramdisk_addr=0x800000\0" \
377 "ramdisk_size=0x2000000\0" \
378 "fdt_high=0xa0000000\0" \
379 "initrd_high=0xffffffffffffffff\0" \
380 "fdt_addr=0x64f00000\0" \
381 "kernel_addr=0x1000000\0" \
382 "kernel_addr_sd=0x8000\0" \
383 "kernelhdr_addr_sd=0x3000\0" \
384 "kernel_start=0x580100000\0" \
385 "kernelheader_start=0x580800000\0" \
386 "scriptaddr=0x80000000\0" \
387 "scripthdraddr=0x80080000\0" \
388 "fdtheader_addr_r=0x80100000\0" \
389 "kernelheader_addr=0x600000\0" \
390 "kernelheader_addr_r=0x80200000\0" \
391 "kernel_addr_r=0x81000000\0" \
392 "kernelheader_size=0x40000\0" \
393 "fdt_addr_r=0x90000000\0" \
394 "load_addr=0xa0000000\0" \
395 "kernel_size=0x2800000\0" \
396 "kernel_size_sd=0x14000\0" \
397 "kernelhdr_size_sd=0x20\0" \
400 "boot_scripts=ls1088ardb_boot.scr\0" \
401 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
402 "scan_dev_for_boot_part=" \
403 "part list ${devtype} ${devnum} devplist; " \
404 "env exists devplist || setenv devplist 1; " \
405 "for distro_bootpart in ${devplist}; do " \
406 "if fstype ${devtype} " \
407 "${devnum}:${distro_bootpart} " \
408 "bootfstype; then " \
409 "run scan_dev_for_boot; " \
413 "load ${devtype} ${devnum}:${distro_bootpart} " \
414 "${scriptaddr} ${prefix}${script}; " \
415 "env exists secureboot && load ${devtype} " \
416 "${devnum}:${distro_bootpart} " \
417 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
418 "&& esbc_validate ${scripthdraddr};" \
419 "source ${scriptaddr}\0" \
420 "installer=load mmc 0:2 $load_addr " \
421 "/flex_installer_arm64.itb; " \
422 "env exists mcinitcmd && run mcinitcmd && " \
423 "mmc read 0x80001000 0x6800 0x800;" \
424 "fsl_mc lazyapply dpl 0x80001000;" \
425 "bootm $load_addr#ls1088ardb\0" \
426 "qspi_bootcmd=echo Trying load from qspi..;" \
427 "sf probe && sf read $load_addr " \
428 "$kernel_addr $kernel_size ; env exists secureboot " \
429 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
430 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
431 "bootm $load_addr#$BOARD\0" \
432 "sd_bootcmd=echo Trying load from sd card..;" \
433 "mmcinfo; mmc read $load_addr " \
434 "$kernel_addr_sd $kernel_size_sd ;" \
435 "env exists secureboot && mmc read $kernelheader_addr_r "\
436 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
437 " && esbc_validate ${kernelheader_addr_r};" \
438 "bootm $load_addr#$BOARD\0"
439 #endif /* CONFIG_TFABOOT */
441 #undef CONFIG_BOOTCOMMAND
442 #ifdef CONFIG_TFABOOT
443 #define QSPI_NOR_BOOTCOMMAND \
444 "sf read 0x80001000 0xd00000 0x100000;" \
445 "env exists mcinitcmd && env exists secureboot " \
446 " && sf read 0x806C0000 0x6C0000 0x100000 " \
447 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
448 "&& fsl_mc lazyapply dpl 0x80001000;" \
449 "run distro_bootcmd;run qspi_bootcmd;" \
450 "env exists secureboot && esbc_halt;"
451 #define SD_BOOTCOMMAND \
452 "env exists mcinitcmd && mmcinfo; " \
453 "mmc read 0x80001000 0x6800 0x800; " \
454 "env exists mcinitcmd && env exists secureboot " \
455 " && mmc read 0x806C0000 0x3600 0x20 " \
456 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
457 "&& fsl_mc lazyapply dpl 0x80001000;" \
458 "run distro_bootcmd;run sd_bootcmd;" \
459 "env exists secureboot && esbc_halt;"
461 #if defined(CONFIG_QSPI_BOOT)
462 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
463 #define CONFIG_BOOTCOMMAND \
464 "sf read 0x80001000 0xd00000 0x100000;" \
465 "env exists mcinitcmd && env exists secureboot " \
466 " && sf read 0x806C0000 0x6C0000 0x100000 " \
467 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
468 "&& fsl_mc lazyapply dpl 0x80001000;" \
469 "run distro_bootcmd;run qspi_bootcmd;" \
470 "env exists secureboot && esbc_halt;"
472 /* Try to boot an on-SD kernel first, then do normal distro boot */
473 #elif defined(CONFIG_SD_BOOT)
474 #define CONFIG_BOOTCOMMAND \
475 "env exists mcinitcmd && mmcinfo; " \
476 "mmc read 0x80001000 0x6800 0x800; " \
477 "env exists mcinitcmd && env exists secureboot " \
478 " && mmc read 0x806C0000 0x3600 0x20 " \
479 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
480 "&& fsl_mc lazyapply dpl 0x80001000;" \
481 "run distro_bootcmd;run sd_bootcmd;" \
482 "env exists secureboot && esbc_halt;"
484 #endif /* CONFIG_TFABOOT */
486 /* MAC/PHY configuration */
487 #ifdef CONFIG_FSL_MC_ENET
488 #define AQ_PHY_ADDR1 0x00
489 #define AQR105_IRQ_MASK 0x00000004
491 #define QSGMII1_PORT1_PHY_ADDR 0x0c
492 #define QSGMII1_PORT2_PHY_ADDR 0x0d
493 #define QSGMII1_PORT3_PHY_ADDR 0x0e
494 #define QSGMII1_PORT4_PHY_ADDR 0x0f
495 #define QSGMII2_PORT1_PHY_ADDR 0x1c
496 #define QSGMII2_PORT2_PHY_ADDR 0x1d
497 #define QSGMII2_PORT3_PHY_ADDR 0x1e
498 #define QSGMII2_PORT4_PHY_ADDR 0x1f
500 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
501 #define CONFIG_PHY_GIGE
507 #define BOOT_TARGET_DEVICES(func) \
510 func(SCSI, scsi, 0) \
512 #include <config_distro_bootcmd.h>
515 #include <asm/fsl_secure_boot.h>
517 #endif /* __LS1088A_RDB_H */