1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
20 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
23 #define CONFIG_SYS_FSL_DDR_EMU
25 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
27 #define SPD_EEPROM_ADDRESS 0x51
28 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
29 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
32 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
33 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
34 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
35 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
37 #define CONFIG_SYS_NOR0_CSPR \
38 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
42 #define CONFIG_SYS_NOR0_CSPR_EARLY \
43 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
47 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
48 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
49 FTIM0_NOR_TEADC(0x1) | \
51 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
52 FTIM1_NOR_TRAD_NOR(0x1))
53 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
54 FTIM2_NOR_TCH(0x0) | \
56 #define CONFIG_SYS_NOR_FTIM3 0x04000000
57 #define CONFIG_SYS_IFC_CCR 0x01000000
60 #define CONFIG_SYS_FLASH_QUIET_TEST
61 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
63 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
64 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
65 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
66 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
68 #define CONFIG_SYS_FLASH_EMPTY_INFO
69 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
73 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
74 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
76 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
77 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
78 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
79 | CSPR_MSEL_NAND /* MSEL = NAND */ \
81 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
83 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
84 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
85 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
86 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
87 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
88 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
89 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
91 /* ONFI NAND Flash mode0 Timing Params */
92 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
93 FTIM0_NAND_TWP(0x18) | \
94 FTIM0_NAND_TWCHT(0x07) | \
96 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
97 FTIM1_NAND_TWBE(0x39) | \
98 FTIM1_NAND_TRR(0x0e) | \
100 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
101 FTIM2_NAND_TREH(0x0a) | \
102 FTIM2_NAND_TWHRE(0x1e))
103 #define CONFIG_SYS_NAND_FTIM3 0x0
105 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
106 #define CONFIG_SYS_MAX_NAND_DEVICE 1
107 #define CONFIG_MTD_NAND_VERIFY_WRITE
110 #define CONFIG_FSL_QIXIS
113 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
114 #define QIXIS_BRDCFG4_OFFSET 0x54
115 #define QIXIS_LBMAP_SWITCH 2
116 #define QIXIS_QMAP_MASK 0xe0
117 #define QIXIS_QMAP_SHIFT 5
118 #define QIXIS_LBMAP_MASK 0x1f
119 #define QIXIS_LBMAP_SHIFT 5
120 #define QIXIS_LBMAP_DFLTBANK 0x00
121 #define QIXIS_LBMAP_ALTBANK 0x20
122 #define QIXIS_LBMAP_SD 0x00
123 #define QIXIS_LBMAP_EMMC 0x00
124 #define QIXIS_LBMAP_SD_QSPI 0x00
125 #define QIXIS_LBMAP_QSPI 0x00
126 #define QIXIS_RCW_SRC_SD 0x40
127 #define QIXIS_RCW_SRC_EMMC 0x41
128 #define QIXIS_RCW_SRC_QSPI 0x62
129 #define QIXIS_RST_CTL_RESET 0x31
130 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
131 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
132 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
133 #define QIXIS_RST_FORCE_MEM 0x01
135 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
136 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
140 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
145 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
146 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
147 /* QIXIS Timing parameters*/
148 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
149 FTIM0_GPCM_TEADC(0x0e) | \
150 FTIM0_GPCM_TEAHC(0x0e))
151 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
152 FTIM1_GPCM_TRAD(0x3f))
153 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
154 FTIM2_GPCM_TCH(0xf) | \
155 FTIM2_GPCM_TWP(0x3E))
156 #define SYS_FPGA_CS_FTIM3 0x0
158 #if defined(CONFIG_TFABOOT) || \
159 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
160 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
161 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
162 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
163 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
164 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
165 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
166 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
167 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
168 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
169 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
170 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
171 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
172 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
173 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
174 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
175 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
176 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
178 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
179 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
180 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
181 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
182 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
183 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
184 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
185 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
186 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
189 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
191 #define I2C_MUX_CH_VOL_MONITOR 0xA
192 /* Voltage monitor on channel 2*/
193 #define I2C_VOL_MONITOR_ADDR 0x63
194 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
195 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
196 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
197 #define I2C_SVDD_MONITOR_ADDR 0x4F
199 /* The lowest and highest voltage allowed for LS1088ARDB */
200 #define VDD_MV_MIN 819
201 #define VDD_MV_MAX 1212
203 #define PWM_CHANNEL0 0x0
206 * I2C bus multiplexer
208 #define I2C_MUX_PCA_ADDR_PRI 0x77
209 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
210 #define I2C_RETIMER_ADDR 0x18
211 #define I2C_MUX_CH_DEFAULT 0x8
212 #define I2C_MUX_CH5 0xD
219 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
223 #define CONFIG_SYS_I2C_EEPROM_NXID
224 #define CONFIG_SYS_EEPROM_BUS_NUM 0
226 #ifdef CONFIG_SPL_BUILD
227 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
232 #define CONFIG_FSL_MEMAC
235 /* Initial environment variables */
236 #ifdef CONFIG_TFABOOT
237 #define QSPI_MC_INIT_CMD \
238 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
239 "sf read 0x80e00000 0xE00000 0x100000;" \
240 "env exists secureboot && " \
241 "sf read 0x80640000 0x640000 0x40000 && " \
242 "sf read 0x80680000 0x680000 0x40000 && " \
243 "esbc_validate 0x80640000 && " \
244 "esbc_validate 0x80680000 ;" \
245 "fsl_mc start mc 0x80a00000 0x80e00000\0"
246 #define SD_MC_INIT_CMD \
247 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
248 "mmc read 0x80e00000 0x7000 0x800;" \
249 "env exists secureboot && " \
250 "mmc read 0x80640000 0x3200 0x20 && " \
251 "mmc read 0x80680000 0x3400 0x20 && " \
252 "esbc_validate 0x80640000 && " \
253 "esbc_validate 0x80680000 ;" \
254 "fsl_mc start mc 0x80a00000 0x80e00000\0"
256 #if defined(CONFIG_QSPI_BOOT)
257 #define MC_INIT_CMD \
258 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
259 "sf read 0x80e00000 0xE00000 0x100000;" \
260 "env exists secureboot && " \
261 "sf read 0x80640000 0x640000 0x40000 && " \
262 "sf read 0x80680000 0x680000 0x40000 && " \
263 "esbc_validate 0x80640000 && " \
264 "esbc_validate 0x80680000 ;" \
265 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
266 "mcmemsize=0x70000000\0"
267 #elif defined(CONFIG_SD_BOOT)
268 #define MC_INIT_CMD \
269 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
270 "mmc read 0x80e00000 0x7000 0x800;" \
271 "env exists secureboot && " \
272 "mmc read 0x80640000 0x3200 0x20 && " \
273 "mmc read 0x80680000 0x3400 0x20 && " \
274 "esbc_validate 0x80640000 && " \
275 "esbc_validate 0x80680000 ;" \
276 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
277 "mcmemsize=0x70000000\0"
279 #endif /* CONFIG_TFABOOT */
281 #undef CONFIG_EXTRA_ENV_SETTINGS
282 #ifdef CONFIG_TFABOOT
283 #define CONFIG_EXTRA_ENV_SETTINGS \
284 "BOARD=ls1088ardb\0" \
285 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
286 "ramdisk_addr=0x800000\0" \
287 "ramdisk_size=0x2000000\0" \
288 "fdt_high=0xa0000000\0" \
289 "initrd_high=0xffffffffffffffff\0" \
290 "fdt_addr=0x64f00000\0" \
291 "kernel_addr=0x1000000\0" \
292 "kernel_addr_sd=0x8000\0" \
293 "kernelhdr_addr_sd=0x3000\0" \
294 "kernel_start=0x580100000\0" \
295 "kernelheader_start=0x580600000\0" \
296 "scriptaddr=0x80000000\0" \
297 "scripthdraddr=0x80080000\0" \
298 "fdtheader_addr_r=0x80100000\0" \
299 "kernelheader_addr=0x600000\0" \
300 "kernelheader_addr_r=0x80200000\0" \
301 "kernel_addr_r=0x81000000\0" \
302 "kernelheader_size=0x40000\0" \
303 "fdt_addr_r=0x90000000\0" \
304 "load_addr=0xa0000000\0" \
305 "kernel_size=0x2800000\0" \
306 "kernel_size_sd=0x14000\0" \
307 "kernelhdr_size_sd=0x20\0" \
309 "mcmemsize=0x70000000\0" \
311 "boot_scripts=ls1088ardb_boot.scr\0" \
312 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
313 "scan_dev_for_boot_part=" \
314 "part list ${devtype} ${devnum} devplist; " \
315 "env exists devplist || setenv devplist 1; " \
316 "for distro_bootpart in ${devplist}; do " \
317 "if fstype ${devtype} " \
318 "${devnum}:${distro_bootpart} " \
319 "bootfstype; then " \
320 "run scan_dev_for_boot; " \
324 "load ${devtype} ${devnum}:${distro_bootpart} " \
325 "${scriptaddr} ${prefix}${script}; " \
326 "env exists secureboot && load ${devtype} " \
327 "${devnum}:${distro_bootpart} " \
328 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
329 "env exists secureboot " \
330 "&& esbc_validate ${scripthdraddr};" \
331 "source ${scriptaddr}\0" \
332 "installer=load mmc 0:2 $load_addr " \
333 "/flex_installer_arm64.itb; " \
334 "env exists mcinitcmd && run mcinitcmd && " \
335 "mmc read 0x80001000 0x6800 0x800;" \
336 "fsl_mc lazyapply dpl 0x80001000;" \
337 "bootm $load_addr#ls1088ardb\0" \
338 "qspi_bootcmd=echo Trying load from qspi..;" \
339 "sf probe && sf read $load_addr " \
340 "$kernel_addr $kernel_size ; env exists secureboot " \
341 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
342 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
343 "bootm $load_addr#$BOARD\0" \
344 "sd_bootcmd=echo Trying load from sd card..;" \
345 "mmcinfo; mmc read $load_addr " \
346 "$kernel_addr_sd $kernel_size_sd ;" \
347 "env exists secureboot && mmc read $kernelheader_addr_r "\
348 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
349 " && esbc_validate ${kernelheader_addr_r};" \
350 "bootm $load_addr#$BOARD\0"
352 #define CONFIG_EXTRA_ENV_SETTINGS \
353 "BOARD=ls1088ardb\0" \
354 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
355 "ramdisk_addr=0x800000\0" \
356 "ramdisk_size=0x2000000\0" \
357 "fdt_high=0xa0000000\0" \
358 "initrd_high=0xffffffffffffffff\0" \
359 "fdt_addr=0x64f00000\0" \
360 "kernel_addr=0x1000000\0" \
361 "kernel_addr_sd=0x8000\0" \
362 "kernelhdr_addr_sd=0x3000\0" \
363 "kernel_start=0x580100000\0" \
364 "kernelheader_start=0x580800000\0" \
365 "scriptaddr=0x80000000\0" \
366 "scripthdraddr=0x80080000\0" \
367 "fdtheader_addr_r=0x80100000\0" \
368 "kernelheader_addr=0x600000\0" \
369 "kernelheader_addr_r=0x80200000\0" \
370 "kernel_addr_r=0x81000000\0" \
371 "kernelheader_size=0x40000\0" \
372 "fdt_addr_r=0x90000000\0" \
373 "load_addr=0xa0000000\0" \
374 "kernel_size=0x2800000\0" \
375 "kernel_size_sd=0x14000\0" \
376 "kernelhdr_size_sd=0x20\0" \
379 "boot_scripts=ls1088ardb_boot.scr\0" \
380 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
381 "scan_dev_for_boot_part=" \
382 "part list ${devtype} ${devnum} devplist; " \
383 "env exists devplist || setenv devplist 1; " \
384 "for distro_bootpart in ${devplist}; do " \
385 "if fstype ${devtype} " \
386 "${devnum}:${distro_bootpart} " \
387 "bootfstype; then " \
388 "run scan_dev_for_boot; " \
392 "load ${devtype} ${devnum}:${distro_bootpart} " \
393 "${scriptaddr} ${prefix}${script}; " \
394 "env exists secureboot && load ${devtype} " \
395 "${devnum}:${distro_bootpart} " \
396 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
397 "&& esbc_validate ${scripthdraddr};" \
398 "source ${scriptaddr}\0" \
399 "installer=load mmc 0:2 $load_addr " \
400 "/flex_installer_arm64.itb; " \
401 "env exists mcinitcmd && run mcinitcmd && " \
402 "mmc read 0x80001000 0x6800 0x800;" \
403 "fsl_mc lazyapply dpl 0x80001000;" \
404 "bootm $load_addr#ls1088ardb\0" \
405 "qspi_bootcmd=echo Trying load from qspi..;" \
406 "sf probe && sf read $load_addr " \
407 "$kernel_addr $kernel_size ; env exists secureboot " \
408 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
409 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
410 "bootm $load_addr#$BOARD\0" \
411 "sd_bootcmd=echo Trying load from sd card..;" \
412 "mmcinfo; mmc read $load_addr " \
413 "$kernel_addr_sd $kernel_size_sd ;" \
414 "env exists secureboot && mmc read $kernelheader_addr_r "\
415 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
416 " && esbc_validate ${kernelheader_addr_r};" \
417 "bootm $load_addr#$BOARD\0"
418 #endif /* CONFIG_TFABOOT */
420 #ifdef CONFIG_TFABOOT
421 #define QSPI_NOR_BOOTCOMMAND \
422 "sf read 0x80001000 0xd00000 0x100000;" \
423 "env exists mcinitcmd && env exists secureboot " \
424 " && sf read 0x806C0000 0x6C0000 0x100000 " \
425 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
426 "&& fsl_mc lazyapply dpl 0x80001000;" \
427 "run distro_bootcmd;run qspi_bootcmd;" \
428 "env exists secureboot && esbc_halt;"
429 #define SD_BOOTCOMMAND \
430 "env exists mcinitcmd && mmcinfo; " \
431 "mmc read 0x80001000 0x6800 0x800; " \
432 "env exists mcinitcmd && env exists secureboot " \
433 " && mmc read 0x806C0000 0x3600 0x20 " \
434 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
435 "&& fsl_mc lazyapply dpl 0x80001000;" \
436 "run distro_bootcmd;run sd_bootcmd;" \
437 "env exists secureboot && esbc_halt;"
439 #if defined(CONFIG_QSPI_BOOT)
440 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
442 /* Try to boot an on-SD kernel first, then do normal distro boot */
444 #endif /* CONFIG_TFABOOT */
446 /* MAC/PHY configuration */
447 #ifdef CONFIG_FSL_MC_ENET
448 #define AQ_PHY_ADDR1 0x00
449 #define AQR105_IRQ_MASK 0x00000004
451 #define QSGMII1_PORT1_PHY_ADDR 0x0c
452 #define QSGMII1_PORT2_PHY_ADDR 0x0d
453 #define QSGMII1_PORT3_PHY_ADDR 0x0e
454 #define QSGMII1_PORT4_PHY_ADDR 0x0f
455 #define QSGMII2_PORT1_PHY_ADDR 0x1c
456 #define QSGMII2_PORT2_PHY_ADDR 0x1d
457 #define QSGMII2_PORT3_PHY_ADDR 0x1e
458 #define QSGMII2_PORT4_PHY_ADDR 0x1f
460 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
466 #define BOOT_TARGET_DEVICES(func) \
469 func(SCSI, scsi, 0) \
471 #include <config_distro_bootcmd.h>
474 #include <asm/fsl_secure_boot.h>
476 #endif /* __LS1088A_RDB_H */