include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #ifndef CONFIG_SPL_BUILD
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #define SYS_NO_FLASH
  17 #endif
  18
  19 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  20 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  21
  22 #ifdef CONFIG_EMU
  23 #define CONFIG_SYS_FSL_DDR_EMU
  24 #else
  25 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  26 #endif
  27 #define SPD_EEPROM_ADDRESS      0x51
  28 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  29 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  30
  31
  32 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  33 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  34 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  35 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  36
  37 #define CONFIG_SYS_NOR0_CSPR                                    \
  38         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  39         CSPR_PORT_SIZE_16                                       | \
  40         CSPR_MSEL_NOR                                           | \
  41         CSPR_V)
  42 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  43         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  44         CSPR_PORT_SIZE_16                                       | \
  45         CSPR_MSEL_NOR                                           | \
  46         CSPR_V)
  47 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  48 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  49                                 FTIM0_NOR_TEADC(0x1) | \
  50                                 FTIM0_NOR_TEAHC(0x1))
  51 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  52                                 FTIM1_NOR_TRAD_NOR(0x1))
  53 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  54                                 FTIM2_NOR_TCH(0x0) | \
  55                                 FTIM2_NOR_TWP(0x1))
  56 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  57 #define CONFIG_SYS_IFC_CCR      0x01000000
  58
  59 #ifndef SYS_NO_FLASH
  60 #define CONFIG_SYS_FLASH_QUIET_TEST
  61 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  62
  63 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  64 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  65 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  66
  67 #define CONFIG_SYS_FLASH_EMPTY_INFO
  68 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  69 #endif
  70 #endif
  71
  72 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  73 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  74
  75 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  76 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  77                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  78                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  79                                 | CSPR_V)
  80 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  81
  82 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  83                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  84                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  85                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  86                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  87                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  88                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  89
  90 /* ONFI NAND Flash mode0 Timing Params */
  91 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  92                                         FTIM0_NAND_TWP(0x18)   | \
  93                                         FTIM0_NAND_TWCHT(0x07) | \
  94                                         FTIM0_NAND_TWH(0x0a))
  95 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  96                                         FTIM1_NAND_TWBE(0x39)  | \
  97                                         FTIM1_NAND_TRR(0x0e)   | \
  98                                         FTIM1_NAND_TRP(0x18))
  99 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 100                                         FTIM2_NAND_TREH(0x0a) | \
 101                                         FTIM2_NAND_TWHRE(0x1e))
 102 #define CONFIG_SYS_NAND_FTIM3           0x0
 103
 104 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 105 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 106 #define CONFIG_MTD_NAND_VERIFY_WRITE
 107
 108 #ifndef SPL_NO_QIXIS
 109 #define CONFIG_FSL_QIXIS
 110 #endif
 111
 112 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 113 #define QIXIS_BRDCFG4_OFFSET            0x54
 114 #define QIXIS_LBMAP_SWITCH              2
 115 #define QIXIS_QMAP_MASK                 0xe0
 116 #define QIXIS_QMAP_SHIFT                5
 117 #define QIXIS_LBMAP_MASK                0x1f
 118 #define QIXIS_LBMAP_SHIFT               5
 119 #define QIXIS_LBMAP_DFLTBANK            0x00
 120 #define QIXIS_LBMAP_ALTBANK             0x20
 121 #define QIXIS_LBMAP_SD                  0x00
 122 #define QIXIS_LBMAP_EMMC                0x00
 123 #define QIXIS_LBMAP_SD_QSPI             0x00
 124 #define QIXIS_LBMAP_QSPI                0x00
 125 #define QIXIS_RCW_SRC_SD                0x40
 126 #define QIXIS_RCW_SRC_EMMC              0x41
 127 #define QIXIS_RCW_SRC_QSPI              0x62
 128 #define QIXIS_RST_CTL_RESET             0x31
 129 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 130 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 131 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 132 #define QIXIS_RST_FORCE_MEM             0x01
 133
 134 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 135 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 136                                         | CSPR_PORT_SIZE_8 \
 137                                         | CSPR_MSEL_GPCM \
 138                                         | CSPR_V)
 139 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 140                                         | CSPR_PORT_SIZE_8 \
 141                                         | CSPR_MSEL_GPCM \
 142                                         | CSPR_V)
 143
 144 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 145 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 146 /* QIXIS Timing parameters*/
 147 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 148                                         FTIM0_GPCM_TEADC(0x0e) | \
 149                                         FTIM0_GPCM_TEAHC(0x0e))
 150 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 151                                         FTIM1_GPCM_TRAD(0x3f))
 152 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 153                                         FTIM2_GPCM_TCH(0xf) | \
 154                                         FTIM2_GPCM_TWP(0x3E))
 155 #define SYS_FPGA_CS_FTIM3       0x0
 156
 157 #if defined(CONFIG_TFABOOT) || \
 158         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 159 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 160 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 161 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 162 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 163 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 164 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 165 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 166 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 167 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 168 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 169 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 170 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 171 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 172 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 173 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 174 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 175 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 176 #else
 177 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 178 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 179 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 180 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 181 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 182 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 183 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 184 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 185 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 186 #endif
 187
 188 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 189
 190 #define I2C_MUX_CH_VOL_MONITOR         0xA
 191 /* Voltage monitor on channel 2*/
 192 #define I2C_VOL_MONITOR_ADDR           0x63
 193 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 194 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 195 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 196 #define I2C_SVDD_MONITOR_ADDR           0x4F
 197
 198 /* The lowest and highest voltage allowed for LS1088ARDB */
 199 #define VDD_MV_MIN                      819
 200 #define VDD_MV_MAX                      1212
 201
 202 #define PWM_CHANNEL0                    0x0
 203
 204 /*
 205  * I2C bus multiplexer
 206  */
 207 #define I2C_MUX_PCA_ADDR_PRI            0x77
 208 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 209 #define I2C_RETIMER_ADDR                0x18
 210 #define I2C_MUX_CH_DEFAULT              0x8
 211 #define I2C_MUX_CH5                     0xD
 212
 213 #ifndef SPL_NO_RTC
 214 /*
 215 * RTC configuration
 216 */
 217 #define RTC
 218 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 219 #endif
 220
 221 /* EEPROM */
 222 #define CONFIG_SYS_I2C_EEPROM_NXID
 223 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 224
 225 #define CONFIG_FSL_MEMAC
 226
 227 #ifndef SPL_NO_ENV
 228 /* Initial environment variables */
 229 #ifdef CONFIG_TFABOOT
 230 #define QSPI_MC_INIT_CMD                                \
 231         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 232         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 233         "env exists secureboot && "                     \
 234         "sf read 0x80640000 0x640000 0x40000 && "       \
 235         "sf read 0x80680000 0x680000 0x40000 && "       \
 236         "esbc_validate 0x80640000 && "                  \
 237         "esbc_validate 0x80680000 ;"                    \
 238         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 239 #define SD_MC_INIT_CMD                          \
 240         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 241         "mmc read 0x80e00000 0x7000 0x800;"                             \
 242         "env exists secureboot && "                     \
 243         "mmc read 0x80640000 0x3200 0x20 && "           \
 244         "mmc read 0x80680000 0x3400 0x20 && "           \
 245         "esbc_validate 0x80640000 && "                  \
 246         "esbc_validate 0x80680000 ;"                    \
 247         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 248 #else
 249 #if defined(CONFIG_QSPI_BOOT)
 250 #define MC_INIT_CMD                             \
 251         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 252         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 253         "env exists secureboot && "                     \
 254         "sf read 0x80640000 0x640000 0x40000 && "       \
 255         "sf read 0x80680000 0x680000 0x40000 && "       \
 256         "esbc_validate 0x80640000 && "                  \
 257         "esbc_validate 0x80680000 ;"                    \
 258         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 259         "mcmemsize=0x70000000\0"
 260 #elif defined(CONFIG_SD_BOOT)
 261 #define MC_INIT_CMD                             \
 262         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 263         "mmc read 0x80e00000 0x7000 0x800;"                             \
 264         "env exists secureboot && "                     \
 265         "mmc read 0x80640000 0x3200 0x20 && "           \
 266         "mmc read 0x80680000 0x3400 0x20 && "           \
 267         "esbc_validate 0x80640000 && "                  \
 268         "esbc_validate 0x80680000 ;"                    \
 269         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 270         "mcmemsize=0x70000000\0"
 271 #endif
 272 #endif /* CONFIG_TFABOOT */
 273
 274 #undef CONFIG_EXTRA_ENV_SETTINGS
 275 #ifdef CONFIG_TFABOOT
 276 #define CONFIG_EXTRA_ENV_SETTINGS               \
 277         "BOARD=ls1088ardb\0"                    \
 278         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 279         "ramdisk_addr=0x800000\0"               \
 280         "ramdisk_size=0x2000000\0"              \
 281         "fdt_high=0xa0000000\0"                 \
 282         "initrd_high=0xffffffffffffffff\0"      \
 283         "fdt_addr=0x64f00000\0"                 \
 284         "kernel_addr=0x1000000\0"               \
 285         "kernel_addr_sd=0x8000\0"               \
 286         "kernelhdr_addr_sd=0x3000\0"            \
 287         "kernel_start=0x580100000\0"            \
 288         "kernelheader_start=0x580600000\0"      \
 289         "scriptaddr=0x80000000\0"               \
 290         "scripthdraddr=0x80080000\0"            \
 291         "fdtheader_addr_r=0x80100000\0"         \
 292         "kernelheader_addr=0x600000\0"          \
 293         "kernelheader_addr_r=0x80200000\0"      \
 294         "kernel_addr_r=0x81000000\0"            \
 295         "kernelheader_size=0x40000\0"           \
 296         "fdt_addr_r=0x90000000\0"               \
 297         "load_addr=0xa0000000\0"                \
 298         "kernel_size=0x2800000\0"               \
 299         "kernel_size_sd=0x14000\0"              \
 300         "kernelhdr_size_sd=0x20\0"              \
 301         QSPI_MC_INIT_CMD                        \
 302         "mcmemsize=0x70000000\0"                \
 303         BOOTENV                                 \
 304         "boot_scripts=ls1088ardb_boot.scr\0"    \
 305         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 306         "scan_dev_for_boot_part="               \
 307                 "part list ${devtype} ${devnum} devplist; "     \
 308                 "env exists devplist || setenv devplist 1; "    \
 309                 "for distro_bootpart in ${devplist}; do "       \
 310                         "if fstype ${devtype} "                 \
 311                                 "${devnum}:${distro_bootpart} " \
 312                                 "bootfstype; then "             \
 313                                 "run scan_dev_for_boot; "       \
 314                         "fi; "                                  \
 315                 "done\0"                                        \
 316         "boot_a_script="                                        \
 317                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 318                 "${scriptaddr} ${prefix}${script}; "            \
 319         "env exists secureboot && load ${devtype} "             \
 320                 "${devnum}:${distro_bootpart} "                 \
 321                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 322                 "env exists secureboot "                        \
 323                 "&& esbc_validate ${scripthdraddr};"            \
 324                 "source ${scriptaddr}\0"                        \
 325         "installer=load mmc 0:2 $load_addr "                    \
 326                 "/flex_installer_arm64.itb; "                   \
 327                 "env exists mcinitcmd && run mcinitcmd && "     \
 328                 "mmc read 0x80001000 0x6800 0x800;"             \
 329                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 330                 "bootm $load_addr#ls1088ardb\0"                 \
 331         "qspi_bootcmd=echo Trying load from qspi..;"            \
 332                 "sf probe && sf read $load_addr "               \
 333                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 334                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 335                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 336                 "bootm $load_addr#$BOARD\0"                     \
 337                 "sd_bootcmd=echo Trying load from sd card..;"           \
 338                 "mmcinfo; mmc read $load_addr "                 \
 339                 "$kernel_addr_sd $kernel_size_sd ;"             \
 340                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 341                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 342                 " && esbc_validate ${kernelheader_addr_r};"     \
 343                 "bootm $load_addr#$BOARD\0"
 344 #else
 345 #define CONFIG_EXTRA_ENV_SETTINGS               \
 346         "BOARD=ls1088ardb\0"                    \
 347         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 348         "ramdisk_addr=0x800000\0"               \
 349         "ramdisk_size=0x2000000\0"              \
 350         "fdt_high=0xa0000000\0"                 \
 351         "initrd_high=0xffffffffffffffff\0"      \
 352         "fdt_addr=0x64f00000\0"                 \
 353         "kernel_addr=0x1000000\0"               \
 354         "kernel_addr_sd=0x8000\0"               \
 355         "kernelhdr_addr_sd=0x3000\0"            \
 356         "kernel_start=0x580100000\0"            \
 357         "kernelheader_start=0x580800000\0"      \
 358         "scriptaddr=0x80000000\0"               \
 359         "scripthdraddr=0x80080000\0"            \
 360         "fdtheader_addr_r=0x80100000\0"         \
 361         "kernelheader_addr=0x600000\0"          \
 362         "kernelheader_addr_r=0x80200000\0"      \
 363         "kernel_addr_r=0x81000000\0"            \
 364         "kernelheader_size=0x40000\0"           \
 365         "fdt_addr_r=0x90000000\0"               \
 366         "load_addr=0xa0000000\0"                \
 367         "kernel_size=0x2800000\0"               \
 368         "kernel_size_sd=0x14000\0"              \
 369         "kernelhdr_size_sd=0x20\0"              \
 370         MC_INIT_CMD                             \
 371         BOOTENV                                 \
 372         "boot_scripts=ls1088ardb_boot.scr\0"    \
 373         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 374         "scan_dev_for_boot_part="               \
 375                 "part list ${devtype} ${devnum} devplist; "     \
 376                 "env exists devplist || setenv devplist 1; "    \
 377                 "for distro_bootpart in ${devplist}; do "       \
 378                         "if fstype ${devtype} "                 \
 379                                 "${devnum}:${distro_bootpart} " \
 380                                 "bootfstype; then "             \
 381                                 "run scan_dev_for_boot; "       \
 382                         "fi; "                                  \
 383                 "done\0"                                        \
 384         "boot_a_script="                                        \
 385                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 386                 "${scriptaddr} ${prefix}${script}; "            \
 387         "env exists secureboot && load ${devtype} "             \
 388                 "${devnum}:${distro_bootpart} "                 \
 389                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 390                 "&& esbc_validate ${scripthdraddr};"            \
 391                 "source ${scriptaddr}\0"                        \
 392         "installer=load mmc 0:2 $load_addr "                    \
 393                 "/flex_installer_arm64.itb; "                   \
 394                 "env exists mcinitcmd && run mcinitcmd && "     \
 395                 "mmc read 0x80001000 0x6800 0x800;"             \
 396                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 397                 "bootm $load_addr#ls1088ardb\0"                 \
 398         "qspi_bootcmd=echo Trying load from qspi..;"            \
 399                 "sf probe && sf read $load_addr "               \
 400                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 401                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 402                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 403                 "bootm $load_addr#$BOARD\0"                     \
 404                 "sd_bootcmd=echo Trying load from sd card..;"           \
 405                 "mmcinfo; mmc read $load_addr "                 \
 406                 "$kernel_addr_sd $kernel_size_sd ;"             \
 407                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 408                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 409                 " && esbc_validate ${kernelheader_addr_r};"     \
 410                 "bootm $load_addr#$BOARD\0"
 411 #endif /* CONFIG_TFABOOT */
 412
 413 #ifdef CONFIG_TFABOOT
 414 #define QSPI_NOR_BOOTCOMMAND                                    \
 415         "sf read 0x80001000 0xd00000 0x100000;"         \
 416                 "env exists mcinitcmd && env exists secureboot "        \
 417                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 418                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 419                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 420                 "run distro_bootcmd;run qspi_bootcmd;"          \
 421                 "env exists secureboot && esbc_halt;"
 422 #define SD_BOOTCOMMAND                                          \
 423                 "env exists mcinitcmd && mmcinfo; "             \
 424                 "mmc read 0x80001000 0x6800 0x800; "            \
 425                 "env exists mcinitcmd && env exists secureboot "        \
 426                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 427                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 428                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 429                 "run distro_bootcmd;run sd_bootcmd;"            \
 430                 "env exists secureboot && esbc_halt;"
 431 #else
 432 #if defined(CONFIG_QSPI_BOOT)
 433 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 434
 435 /* Try to boot an on-SD kernel first, then do normal distro boot */
 436 #endif
 437 #endif /* CONFIG_TFABOOT */
 438
 439 /* MAC/PHY configuration */
 440 #ifdef CONFIG_FSL_MC_ENET
 441 #define AQ_PHY_ADDR1                    0x00
 442 #define AQR105_IRQ_MASK                 0x00000004
 443
 444 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 445 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 446 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 447 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 448 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 449 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 450 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 451 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 452 #endif
 453 #endif
 454
 455 #ifndef SPL_NO_ENV
 456
 457 #define BOOT_TARGET_DEVICES(func) \
 458         func(MMC, mmc, 0) \
 459         func(USB, usb, 0) \
 460         func(SCSI, scsi, 0) \
 461         func(DHCP, dhcp, na)
 462 #include <config_distro_bootcmd.h>
 463 #endif
 464
 465 #include <asm/fsl_secure_boot.h>
 466
 467 #endif /* __LS1088A_RDB_H */