1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
16 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
18 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
19 #define SPD_EEPROM_ADDRESS 0x51
22 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
23 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
24 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
25 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
27 #define CONFIG_SYS_NOR0_CSPR \
28 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
32 #define CONFIG_SYS_NOR0_CSPR_EARLY \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
37 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
38 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
39 FTIM0_NOR_TEADC(0x1) | \
41 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
42 FTIM1_NOR_TRAD_NOR(0x1))
43 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
44 FTIM2_NOR_TCH(0x0) | \
46 #define CONFIG_SYS_NOR_FTIM3 0x04000000
47 #define CONFIG_SYS_IFC_CCR 0x01000000
50 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
52 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
56 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
57 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
58 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
59 | CSPR_MSEL_NAND /* MSEL = NAND */ \
61 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
63 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
64 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
65 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
66 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
67 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
68 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
69 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
71 /* ONFI NAND Flash mode0 Timing Params */
72 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
73 FTIM0_NAND_TWP(0x18) | \
74 FTIM0_NAND_TWCHT(0x07) | \
76 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
77 FTIM1_NAND_TWBE(0x39) | \
78 FTIM1_NAND_TRR(0x0e) | \
80 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
81 FTIM2_NAND_TREH(0x0a) | \
82 FTIM2_NAND_TWHRE(0x1e))
83 #define CONFIG_SYS_NAND_FTIM3 0x0
85 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
86 #define CONFIG_MTD_NAND_VERIFY_WRITE
88 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
89 #define QIXIS_BRDCFG4_OFFSET 0x54
90 #define QIXIS_LBMAP_SWITCH 2
91 #define QIXIS_QMAP_MASK 0xe0
92 #define QIXIS_QMAP_SHIFT 5
93 #define QIXIS_LBMAP_MASK 0x1f
94 #define QIXIS_LBMAP_SHIFT 5
95 #define QIXIS_LBMAP_DFLTBANK 0x00
96 #define QIXIS_LBMAP_ALTBANK 0x20
97 #define QIXIS_LBMAP_SD 0x00
98 #define QIXIS_LBMAP_EMMC 0x00
99 #define QIXIS_LBMAP_SD_QSPI 0x00
100 #define QIXIS_LBMAP_QSPI 0x00
101 #define QIXIS_RCW_SRC_SD 0x40
102 #define QIXIS_RCW_SRC_EMMC 0x41
103 #define QIXIS_RCW_SRC_QSPI 0x62
104 #define QIXIS_RST_CTL_RESET 0x31
105 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
106 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
107 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
108 #define QIXIS_RST_FORCE_MEM 0x01
110 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
111 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
115 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
120 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
121 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
122 /* QIXIS Timing parameters*/
123 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
124 FTIM0_GPCM_TEADC(0x0e) | \
125 FTIM0_GPCM_TEAHC(0x0e))
126 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
127 FTIM1_GPCM_TRAD(0x3f))
128 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
129 FTIM2_GPCM_TCH(0xf) | \
130 FTIM2_GPCM_TWP(0x3E))
131 #define SYS_FPGA_CS_FTIM3 0x0
133 #if defined(CONFIG_TFABOOT) || \
134 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
135 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
136 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
137 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
138 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
139 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
140 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
141 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
142 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
143 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
144 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
145 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
146 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
147 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
148 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
149 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
150 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
151 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
153 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
154 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
155 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
156 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
157 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
158 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
159 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
160 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
161 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
164 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
166 #define I2C_MUX_CH_VOL_MONITOR 0xA
167 /* Voltage monitor on channel 2*/
168 #define I2C_VOL_MONITOR_ADDR 0x63
169 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
170 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
171 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
172 #define I2C_SVDD_MONITOR_ADDR 0x4F
174 /* The lowest and highest voltage allowed for LS1088ARDB */
175 #define VDD_MV_MIN 819
176 #define VDD_MV_MAX 1212
178 #define PWM_CHANNEL0 0x0
181 * I2C bus multiplexer
183 #define I2C_MUX_PCA_ADDR_PRI 0x77
184 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
185 #define I2C_RETIMER_ADDR 0x18
186 #define I2C_MUX_CH_DEFAULT 0x8
187 #define I2C_MUX_CH5 0xD
194 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
198 /* Initial environment variables */
199 #ifdef CONFIG_TFABOOT
200 #define QSPI_MC_INIT_CMD \
201 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
202 "sf read 0x80e00000 0xE00000 0x100000;" \
203 "env exists secureboot && " \
204 "sf read 0x80640000 0x640000 0x40000 && " \
205 "sf read 0x80680000 0x680000 0x40000 && " \
206 "esbc_validate 0x80640000 && " \
207 "esbc_validate 0x80680000 ;" \
208 "fsl_mc start mc 0x80a00000 0x80e00000\0"
209 #define SD_MC_INIT_CMD \
210 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
211 "mmc read 0x80e00000 0x7000 0x800;" \
212 "env exists secureboot && " \
213 "mmc read 0x80640000 0x3200 0x20 && " \
214 "mmc read 0x80680000 0x3400 0x20 && " \
215 "esbc_validate 0x80640000 && " \
216 "esbc_validate 0x80680000 ;" \
217 "fsl_mc start mc 0x80a00000 0x80e00000\0"
219 #if defined(CONFIG_QSPI_BOOT)
220 #define MC_INIT_CMD \
221 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
222 "sf read 0x80e00000 0xE00000 0x100000;" \
223 "env exists secureboot && " \
224 "sf read 0x80640000 0x640000 0x40000 && " \
225 "sf read 0x80680000 0x680000 0x40000 && " \
226 "esbc_validate 0x80640000 && " \
227 "esbc_validate 0x80680000 ;" \
228 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
229 "mcmemsize=0x70000000\0"
230 #elif defined(CONFIG_SD_BOOT)
231 #define MC_INIT_CMD \
232 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
233 "mmc read 0x80e00000 0x7000 0x800;" \
234 "env exists secureboot && " \
235 "mmc read 0x80640000 0x3200 0x20 && " \
236 "mmc read 0x80680000 0x3400 0x20 && " \
237 "esbc_validate 0x80640000 && " \
238 "esbc_validate 0x80680000 ;" \
239 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
240 "mcmemsize=0x70000000\0"
242 #endif /* CONFIG_TFABOOT */
244 #undef CONFIG_EXTRA_ENV_SETTINGS
245 #ifdef CONFIG_TFABOOT
246 #define CONFIG_EXTRA_ENV_SETTINGS \
247 "BOARD=ls1088ardb\0" \
248 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
249 "ramdisk_addr=0x800000\0" \
250 "ramdisk_size=0x2000000\0" \
251 "fdt_high=0xa0000000\0" \
252 "initrd_high=0xffffffffffffffff\0" \
253 "kernel_addr=0x1000000\0" \
254 "kernel_addr_sd=0x8000\0" \
255 "kernelhdr_addr_sd=0x3000\0" \
256 "kernel_start=0x580100000\0" \
257 "kernelheader_start=0x580600000\0" \
258 "scriptaddr=0x80000000\0" \
259 "scripthdraddr=0x80080000\0" \
260 "fdtheader_addr_r=0x80100000\0" \
261 "kernelheader_addr=0x600000\0" \
262 "kernelheader_addr_r=0x80200000\0" \
263 "kernel_addr_r=0x81000000\0" \
264 "kernelheader_size=0x40000\0" \
265 "fdt_addr_r=0x90000000\0" \
266 "load_addr=0xa0000000\0" \
267 "kernel_size=0x2800000\0" \
268 "kernel_size_sd=0x14000\0" \
269 "kernelhdr_size_sd=0x20\0" \
271 "mcmemsize=0x70000000\0" \
273 "boot_scripts=ls1088ardb_boot.scr\0" \
274 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
275 "scan_dev_for_boot_part=" \
276 "part list ${devtype} ${devnum} devplist; " \
277 "env exists devplist || setenv devplist 1; " \
278 "for distro_bootpart in ${devplist}; do " \
279 "if fstype ${devtype} " \
280 "${devnum}:${distro_bootpart} " \
281 "bootfstype; then " \
282 "run scan_dev_for_boot; " \
286 "load ${devtype} ${devnum}:${distro_bootpart} " \
287 "${scriptaddr} ${prefix}${script}; " \
288 "env exists secureboot && load ${devtype} " \
289 "${devnum}:${distro_bootpart} " \
290 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
291 "env exists secureboot " \
292 "&& esbc_validate ${scripthdraddr};" \
293 "source ${scriptaddr}\0" \
294 "installer=load mmc 0:2 $load_addr " \
295 "/flex_installer_arm64.itb; " \
296 "env exists mcinitcmd && run mcinitcmd && " \
297 "mmc read 0x80001000 0x6800 0x800;" \
298 "fsl_mc lazyapply dpl 0x80001000;" \
299 "bootm $load_addr#ls1088ardb\0" \
300 "qspi_bootcmd=echo Trying load from qspi..;" \
301 "sf probe && sf read $load_addr " \
302 "$kernel_addr $kernel_size ; env exists secureboot " \
303 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
304 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
305 "bootm $load_addr#$BOARD\0" \
306 "sd_bootcmd=echo Trying load from sd card..;" \
307 "mmcinfo; mmc read $load_addr " \
308 "$kernel_addr_sd $kernel_size_sd ;" \
309 "env exists secureboot && mmc read $kernelheader_addr_r "\
310 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
311 " && esbc_validate ${kernelheader_addr_r};" \
312 "bootm $load_addr#$BOARD\0"
314 #define CONFIG_EXTRA_ENV_SETTINGS \
315 "BOARD=ls1088ardb\0" \
316 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
317 "ramdisk_addr=0x800000\0" \
318 "ramdisk_size=0x2000000\0" \
319 "fdt_high=0xa0000000\0" \
320 "initrd_high=0xffffffffffffffff\0" \
321 "kernel_addr=0x1000000\0" \
322 "kernel_addr_sd=0x8000\0" \
323 "kernelhdr_addr_sd=0x3000\0" \
324 "kernel_start=0x580100000\0" \
325 "kernelheader_start=0x580800000\0" \
326 "scriptaddr=0x80000000\0" \
327 "scripthdraddr=0x80080000\0" \
328 "fdtheader_addr_r=0x80100000\0" \
329 "kernelheader_addr=0x600000\0" \
330 "kernelheader_addr_r=0x80200000\0" \
331 "kernel_addr_r=0x81000000\0" \
332 "kernelheader_size=0x40000\0" \
333 "fdt_addr_r=0x90000000\0" \
334 "load_addr=0xa0000000\0" \
335 "kernel_size=0x2800000\0" \
336 "kernel_size_sd=0x14000\0" \
337 "kernelhdr_size_sd=0x20\0" \
340 "boot_scripts=ls1088ardb_boot.scr\0" \
341 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
342 "scan_dev_for_boot_part=" \
343 "part list ${devtype} ${devnum} devplist; " \
344 "env exists devplist || setenv devplist 1; " \
345 "for distro_bootpart in ${devplist}; do " \
346 "if fstype ${devtype} " \
347 "${devnum}:${distro_bootpart} " \
348 "bootfstype; then " \
349 "run scan_dev_for_boot; " \
353 "load ${devtype} ${devnum}:${distro_bootpart} " \
354 "${scriptaddr} ${prefix}${script}; " \
355 "env exists secureboot && load ${devtype} " \
356 "${devnum}:${distro_bootpart} " \
357 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
358 "&& esbc_validate ${scripthdraddr};" \
359 "source ${scriptaddr}\0" \
360 "installer=load mmc 0:2 $load_addr " \
361 "/flex_installer_arm64.itb; " \
362 "env exists mcinitcmd && run mcinitcmd && " \
363 "mmc read 0x80001000 0x6800 0x800;" \
364 "fsl_mc lazyapply dpl 0x80001000;" \
365 "bootm $load_addr#ls1088ardb\0" \
366 "qspi_bootcmd=echo Trying load from qspi..;" \
367 "sf probe && sf read $load_addr " \
368 "$kernel_addr $kernel_size ; env exists secureboot " \
369 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
370 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
371 "bootm $load_addr#$BOARD\0" \
372 "sd_bootcmd=echo Trying load from sd card..;" \
373 "mmcinfo; mmc read $load_addr " \
374 "$kernel_addr_sd $kernel_size_sd ;" \
375 "env exists secureboot && mmc read $kernelheader_addr_r "\
376 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
377 " && esbc_validate ${kernelheader_addr_r};" \
378 "bootm $load_addr#$BOARD\0"
379 #endif /* CONFIG_TFABOOT */
381 #ifdef CONFIG_TFABOOT
382 #define QSPI_NOR_BOOTCOMMAND \
383 "sf read 0x80001000 0xd00000 0x100000;" \
384 "env exists mcinitcmd && env exists secureboot " \
385 " && sf read 0x806C0000 0x6C0000 0x100000 " \
386 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
387 "&& fsl_mc lazyapply dpl 0x80001000;" \
388 "run distro_bootcmd;run qspi_bootcmd;" \
389 "env exists secureboot && esbc_halt;"
390 #define SD_BOOTCOMMAND \
391 "env exists mcinitcmd && mmcinfo; " \
392 "mmc read 0x80001000 0x6800 0x800; " \
393 "env exists mcinitcmd && env exists secureboot " \
394 " && mmc read 0x806C0000 0x3600 0x20 " \
395 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
396 "&& fsl_mc lazyapply dpl 0x80001000;" \
397 "run distro_bootcmd;run sd_bootcmd;" \
398 "env exists secureboot && esbc_halt;"
400 #if defined(CONFIG_QSPI_BOOT)
401 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
403 /* Try to boot an on-SD kernel first, then do normal distro boot */
405 #endif /* CONFIG_TFABOOT */
407 /* MAC/PHY configuration */
408 #ifdef CONFIG_FSL_MC_ENET
409 #define AQ_PHY_ADDR1 0x00
410 #define AQR105_IRQ_MASK 0x00000004
412 #define QSGMII1_PORT1_PHY_ADDR 0x0c
413 #define QSGMII1_PORT2_PHY_ADDR 0x0d
414 #define QSGMII1_PORT3_PHY_ADDR 0x0e
415 #define QSGMII1_PORT4_PHY_ADDR 0x0f
416 #define QSGMII2_PORT1_PHY_ADDR 0x1c
417 #define QSGMII2_PORT2_PHY_ADDR 0x1d
418 #define QSGMII2_PORT3_PHY_ADDR 0x1e
419 #define QSGMII2_PORT4_PHY_ADDR 0x1f
425 #define BOOT_TARGET_DEVICES(func) \
428 func(SCSI, scsi, 0) \
430 #include <config_distro_bootcmd.h>
433 #include <asm/fsl_secure_boot.h>
435 #endif /* __LS1088A_RDB_H */