include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #ifndef CONFIG_SPL_BUILD
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #define SYS_NO_FLASH
  17 #endif
  18
  19 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  20 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  21
  22 #ifdef CONFIG_EMU
  23 #define CONFIG_SYS_FSL_DDR_EMU
  24 #else
  25 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  26 #endif
  27 #define SPD_EEPROM_ADDRESS      0x51
  28 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  29
  30
  31 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  32 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  33 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  34 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  35
  36 #define CONFIG_SYS_NOR0_CSPR                                    \
  37         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  38         CSPR_PORT_SIZE_16                                       | \
  39         CSPR_MSEL_NOR                                           | \
  40         CSPR_V)
  41 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  42         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  43         CSPR_PORT_SIZE_16                                       | \
  44         CSPR_MSEL_NOR                                           | \
  45         CSPR_V)
  46 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  47 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  48                                 FTIM0_NOR_TEADC(0x1) | \
  49                                 FTIM0_NOR_TEAHC(0x1))
  50 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  51                                 FTIM1_NOR_TRAD_NOR(0x1))
  52 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  53                                 FTIM2_NOR_TCH(0x0) | \
  54                                 FTIM2_NOR_TWP(0x1))
  55 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  56 #define CONFIG_SYS_IFC_CCR      0x01000000
  57
  58 #ifndef SYS_NO_FLASH
  59 #define CONFIG_SYS_FLASH_QUIET_TEST
  60 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  61
  62 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  63 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  64 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  65
  66 #define CONFIG_SYS_FLASH_EMPTY_INFO
  67 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  68 #endif
  69 #endif
  70
  71 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  72 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  73
  74 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  75 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  76                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  77                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  78                                 | CSPR_V)
  79 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  80
  81 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  82                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  83                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  84                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  85                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  86                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  87                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  88
  89 /* ONFI NAND Flash mode0 Timing Params */
  90 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  91                                         FTIM0_NAND_TWP(0x18)   | \
  92                                         FTIM0_NAND_TWCHT(0x07) | \
  93                                         FTIM0_NAND_TWH(0x0a))
  94 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  95                                         FTIM1_NAND_TWBE(0x39)  | \
  96                                         FTIM1_NAND_TRR(0x0e)   | \
  97                                         FTIM1_NAND_TRP(0x18))
  98 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
  99                                         FTIM2_NAND_TREH(0x0a) | \
 100                                         FTIM2_NAND_TWHRE(0x1e))
 101 #define CONFIG_SYS_NAND_FTIM3           0x0
 102
 103 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 104 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 105 #define CONFIG_MTD_NAND_VERIFY_WRITE
 106
 107 #ifndef SPL_NO_QIXIS
 108 #define CONFIG_FSL_QIXIS
 109 #endif
 110
 111 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 112 #define QIXIS_BRDCFG4_OFFSET            0x54
 113 #define QIXIS_LBMAP_SWITCH              2
 114 #define QIXIS_QMAP_MASK                 0xe0
 115 #define QIXIS_QMAP_SHIFT                5
 116 #define QIXIS_LBMAP_MASK                0x1f
 117 #define QIXIS_LBMAP_SHIFT               5
 118 #define QIXIS_LBMAP_DFLTBANK            0x00
 119 #define QIXIS_LBMAP_ALTBANK             0x20
 120 #define QIXIS_LBMAP_SD                  0x00
 121 #define QIXIS_LBMAP_EMMC                0x00
 122 #define QIXIS_LBMAP_SD_QSPI             0x00
 123 #define QIXIS_LBMAP_QSPI                0x00
 124 #define QIXIS_RCW_SRC_SD                0x40
 125 #define QIXIS_RCW_SRC_EMMC              0x41
 126 #define QIXIS_RCW_SRC_QSPI              0x62
 127 #define QIXIS_RST_CTL_RESET             0x31
 128 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 129 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 130 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 131 #define QIXIS_RST_FORCE_MEM             0x01
 132
 133 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 134 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 135                                         | CSPR_PORT_SIZE_8 \
 136                                         | CSPR_MSEL_GPCM \
 137                                         | CSPR_V)
 138 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 139                                         | CSPR_PORT_SIZE_8 \
 140                                         | CSPR_MSEL_GPCM \
 141                                         | CSPR_V)
 142
 143 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 144 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 145 /* QIXIS Timing parameters*/
 146 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 147                                         FTIM0_GPCM_TEADC(0x0e) | \
 148                                         FTIM0_GPCM_TEAHC(0x0e))
 149 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 150                                         FTIM1_GPCM_TRAD(0x3f))
 151 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 152                                         FTIM2_GPCM_TCH(0xf) | \
 153                                         FTIM2_GPCM_TWP(0x3E))
 154 #define SYS_FPGA_CS_FTIM3       0x0
 155
 156 #if defined(CONFIG_TFABOOT) || \
 157         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 158 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 159 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 160 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 161 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 162 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 163 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 164 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 165 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 166 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 167 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 168 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 169 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 170 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 171 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 172 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 173 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 174 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 175 #else
 176 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 177 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 178 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 179 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 180 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 181 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 182 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 183 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 184 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 185 #endif
 186
 187 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 188
 189 #define I2C_MUX_CH_VOL_MONITOR         0xA
 190 /* Voltage monitor on channel 2*/
 191 #define I2C_VOL_MONITOR_ADDR           0x63
 192 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 193 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 194 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 195 #define I2C_SVDD_MONITOR_ADDR           0x4F
 196
 197 /* The lowest and highest voltage allowed for LS1088ARDB */
 198 #define VDD_MV_MIN                      819
 199 #define VDD_MV_MAX                      1212
 200
 201 #define PWM_CHANNEL0                    0x0
 202
 203 /*
 204  * I2C bus multiplexer
 205  */
 206 #define I2C_MUX_PCA_ADDR_PRI            0x77
 207 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 208 #define I2C_RETIMER_ADDR                0x18
 209 #define I2C_MUX_CH_DEFAULT              0x8
 210 #define I2C_MUX_CH5                     0xD
 211
 212 #ifndef SPL_NO_RTC
 213 /*
 214 * RTC configuration
 215 */
 216 #define RTC
 217 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 218 #endif
 219
 220 /* EEPROM */
 221 #define CONFIG_SYS_I2C_EEPROM_NXID
 222 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 223
 224 #define CONFIG_FSL_MEMAC
 225
 226 #ifndef SPL_NO_ENV
 227 /* Initial environment variables */
 228 #ifdef CONFIG_TFABOOT
 229 #define QSPI_MC_INIT_CMD                                \
 230         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 231         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 232         "env exists secureboot && "                     \
 233         "sf read 0x80640000 0x640000 0x40000 && "       \
 234         "sf read 0x80680000 0x680000 0x40000 && "       \
 235         "esbc_validate 0x80640000 && "                  \
 236         "esbc_validate 0x80680000 ;"                    \
 237         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 238 #define SD_MC_INIT_CMD                          \
 239         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 240         "mmc read 0x80e00000 0x7000 0x800;"                             \
 241         "env exists secureboot && "                     \
 242         "mmc read 0x80640000 0x3200 0x20 && "           \
 243         "mmc read 0x80680000 0x3400 0x20 && "           \
 244         "esbc_validate 0x80640000 && "                  \
 245         "esbc_validate 0x80680000 ;"                    \
 246         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 247 #else
 248 #if defined(CONFIG_QSPI_BOOT)
 249 #define MC_INIT_CMD                             \
 250         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 251         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 252         "env exists secureboot && "                     \
 253         "sf read 0x80640000 0x640000 0x40000 && "       \
 254         "sf read 0x80680000 0x680000 0x40000 && "       \
 255         "esbc_validate 0x80640000 && "                  \
 256         "esbc_validate 0x80680000 ;"                    \
 257         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 258         "mcmemsize=0x70000000\0"
 259 #elif defined(CONFIG_SD_BOOT)
 260 #define MC_INIT_CMD                             \
 261         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 262         "mmc read 0x80e00000 0x7000 0x800;"                             \
 263         "env exists secureboot && "                     \
 264         "mmc read 0x80640000 0x3200 0x20 && "           \
 265         "mmc read 0x80680000 0x3400 0x20 && "           \
 266         "esbc_validate 0x80640000 && "                  \
 267         "esbc_validate 0x80680000 ;"                    \
 268         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 269         "mcmemsize=0x70000000\0"
 270 #endif
 271 #endif /* CONFIG_TFABOOT */
 272
 273 #undef CONFIG_EXTRA_ENV_SETTINGS
 274 #ifdef CONFIG_TFABOOT
 275 #define CONFIG_EXTRA_ENV_SETTINGS               \
 276         "BOARD=ls1088ardb\0"                    \
 277         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 278         "ramdisk_addr=0x800000\0"               \
 279         "ramdisk_size=0x2000000\0"              \
 280         "fdt_high=0xa0000000\0"                 \
 281         "initrd_high=0xffffffffffffffff\0"      \
 282         "fdt_addr=0x64f00000\0"                 \
 283         "kernel_addr=0x1000000\0"               \
 284         "kernel_addr_sd=0x8000\0"               \
 285         "kernelhdr_addr_sd=0x3000\0"            \
 286         "kernel_start=0x580100000\0"            \
 287         "kernelheader_start=0x580600000\0"      \
 288         "scriptaddr=0x80000000\0"               \
 289         "scripthdraddr=0x80080000\0"            \
 290         "fdtheader_addr_r=0x80100000\0"         \
 291         "kernelheader_addr=0x600000\0"          \
 292         "kernelheader_addr_r=0x80200000\0"      \
 293         "kernel_addr_r=0x81000000\0"            \
 294         "kernelheader_size=0x40000\0"           \
 295         "fdt_addr_r=0x90000000\0"               \
 296         "load_addr=0xa0000000\0"                \
 297         "kernel_size=0x2800000\0"               \
 298         "kernel_size_sd=0x14000\0"              \
 299         "kernelhdr_size_sd=0x20\0"              \
 300         QSPI_MC_INIT_CMD                        \
 301         "mcmemsize=0x70000000\0"                \
 302         BOOTENV                                 \
 303         "boot_scripts=ls1088ardb_boot.scr\0"    \
 304         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 305         "scan_dev_for_boot_part="               \
 306                 "part list ${devtype} ${devnum} devplist; "     \
 307                 "env exists devplist || setenv devplist 1; "    \
 308                 "for distro_bootpart in ${devplist}; do "       \
 309                         "if fstype ${devtype} "                 \
 310                                 "${devnum}:${distro_bootpart} " \
 311                                 "bootfstype; then "             \
 312                                 "run scan_dev_for_boot; "       \
 313                         "fi; "                                  \
 314                 "done\0"                                        \
 315         "boot_a_script="                                        \
 316                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 317                 "${scriptaddr} ${prefix}${script}; "            \
 318         "env exists secureboot && load ${devtype} "             \
 319                 "${devnum}:${distro_bootpart} "                 \
 320                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 321                 "env exists secureboot "                        \
 322                 "&& esbc_validate ${scripthdraddr};"            \
 323                 "source ${scriptaddr}\0"                        \
 324         "installer=load mmc 0:2 $load_addr "                    \
 325                 "/flex_installer_arm64.itb; "                   \
 326                 "env exists mcinitcmd && run mcinitcmd && "     \
 327                 "mmc read 0x80001000 0x6800 0x800;"             \
 328                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 329                 "bootm $load_addr#ls1088ardb\0"                 \
 330         "qspi_bootcmd=echo Trying load from qspi..;"            \
 331                 "sf probe && sf read $load_addr "               \
 332                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 333                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 334                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 335                 "bootm $load_addr#$BOARD\0"                     \
 336                 "sd_bootcmd=echo Trying load from sd card..;"           \
 337                 "mmcinfo; mmc read $load_addr "                 \
 338                 "$kernel_addr_sd $kernel_size_sd ;"             \
 339                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 340                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 341                 " && esbc_validate ${kernelheader_addr_r};"     \
 342                 "bootm $load_addr#$BOARD\0"
 343 #else
 344 #define CONFIG_EXTRA_ENV_SETTINGS               \
 345         "BOARD=ls1088ardb\0"                    \
 346         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 347         "ramdisk_addr=0x800000\0"               \
 348         "ramdisk_size=0x2000000\0"              \
 349         "fdt_high=0xa0000000\0"                 \
 350         "initrd_high=0xffffffffffffffff\0"      \
 351         "fdt_addr=0x64f00000\0"                 \
 352         "kernel_addr=0x1000000\0"               \
 353         "kernel_addr_sd=0x8000\0"               \
 354         "kernelhdr_addr_sd=0x3000\0"            \
 355         "kernel_start=0x580100000\0"            \
 356         "kernelheader_start=0x580800000\0"      \
 357         "scriptaddr=0x80000000\0"               \
 358         "scripthdraddr=0x80080000\0"            \
 359         "fdtheader_addr_r=0x80100000\0"         \
 360         "kernelheader_addr=0x600000\0"          \
 361         "kernelheader_addr_r=0x80200000\0"      \
 362         "kernel_addr_r=0x81000000\0"            \
 363         "kernelheader_size=0x40000\0"           \
 364         "fdt_addr_r=0x90000000\0"               \
 365         "load_addr=0xa0000000\0"                \
 366         "kernel_size=0x2800000\0"               \
 367         "kernel_size_sd=0x14000\0"              \
 368         "kernelhdr_size_sd=0x20\0"              \
 369         MC_INIT_CMD                             \
 370         BOOTENV                                 \
 371         "boot_scripts=ls1088ardb_boot.scr\0"    \
 372         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 373         "scan_dev_for_boot_part="               \
 374                 "part list ${devtype} ${devnum} devplist; "     \
 375                 "env exists devplist || setenv devplist 1; "    \
 376                 "for distro_bootpart in ${devplist}; do "       \
 377                         "if fstype ${devtype} "                 \
 378                                 "${devnum}:${distro_bootpart} " \
 379                                 "bootfstype; then "             \
 380                                 "run scan_dev_for_boot; "       \
 381                         "fi; "                                  \
 382                 "done\0"                                        \
 383         "boot_a_script="                                        \
 384                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 385                 "${scriptaddr} ${prefix}${script}; "            \
 386         "env exists secureboot && load ${devtype} "             \
 387                 "${devnum}:${distro_bootpart} "                 \
 388                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 389                 "&& esbc_validate ${scripthdraddr};"            \
 390                 "source ${scriptaddr}\0"                        \
 391         "installer=load mmc 0:2 $load_addr "                    \
 392                 "/flex_installer_arm64.itb; "                   \
 393                 "env exists mcinitcmd && run mcinitcmd && "     \
 394                 "mmc read 0x80001000 0x6800 0x800;"             \
 395                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 396                 "bootm $load_addr#ls1088ardb\0"                 \
 397         "qspi_bootcmd=echo Trying load from qspi..;"            \
 398                 "sf probe && sf read $load_addr "               \
 399                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 400                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 401                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 402                 "bootm $load_addr#$BOARD\0"                     \
 403                 "sd_bootcmd=echo Trying load from sd card..;"           \
 404                 "mmcinfo; mmc read $load_addr "                 \
 405                 "$kernel_addr_sd $kernel_size_sd ;"             \
 406                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 407                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 408                 " && esbc_validate ${kernelheader_addr_r};"     \
 409                 "bootm $load_addr#$BOARD\0"
 410 #endif /* CONFIG_TFABOOT */
 411
 412 #ifdef CONFIG_TFABOOT
 413 #define QSPI_NOR_BOOTCOMMAND                                    \
 414         "sf read 0x80001000 0xd00000 0x100000;"         \
 415                 "env exists mcinitcmd && env exists secureboot "        \
 416                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 417                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 418                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 419                 "run distro_bootcmd;run qspi_bootcmd;"          \
 420                 "env exists secureboot && esbc_halt;"
 421 #define SD_BOOTCOMMAND                                          \
 422                 "env exists mcinitcmd && mmcinfo; "             \
 423                 "mmc read 0x80001000 0x6800 0x800; "            \
 424                 "env exists mcinitcmd && env exists secureboot "        \
 425                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 426                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 427                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 428                 "run distro_bootcmd;run sd_bootcmd;"            \
 429                 "env exists secureboot && esbc_halt;"
 430 #else
 431 #if defined(CONFIG_QSPI_BOOT)
 432 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 433
 434 /* Try to boot an on-SD kernel first, then do normal distro boot */
 435 #endif
 436 #endif /* CONFIG_TFABOOT */
 437
 438 /* MAC/PHY configuration */
 439 #ifdef CONFIG_FSL_MC_ENET
 440 #define AQ_PHY_ADDR1                    0x00
 441 #define AQR105_IRQ_MASK                 0x00000004
 442
 443 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 444 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 445 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 446 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 447 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 448 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 449 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 450 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 451 #endif
 452 #endif
 453
 454 #ifndef SPL_NO_ENV
 455
 456 #define BOOT_TARGET_DEVICES(func) \
 457         func(MMC, mmc, 0) \
 458         func(USB, usb, 0) \
 459         func(SCSI, scsi, 0) \
 460         func(DHCP, dhcp, na)
 461 #include <config_distro_bootcmd.h>
 462 #endif
 463
 464 #include <asm/fsl_secure_boot.h>
 465
 466 #endif /* __LS1088A_RDB_H */