include/configs/ls1088ardb.h

   1 /*
   2  * Copyright 2017 NXP
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1088A_RDB_H
   8 #define __LS1088A_RDB_H
   9
  10 #include "ls1088a_common.h"
  11
  12 #ifndef SPL_NO_BOARDINFO
  13 #define CONFIG_DISPLAY_BOARDINFO_LATE
  14 #endif
  15
  16 #define CONFIG_MISC_INIT_R
  17
  18 #if defined(CONFIG_QSPI_BOOT)
  19 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  20 #define CONFIG_ENV_SECT_SIZE            0x40000
  21 #elif defined(CONFIG_SD_BOOT)
  22 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
  23 #define CONFIG_SYS_MMC_ENV_DEV          0
  24 #define CONFIG_ENV_SIZE                 0x2000
  25 #else
  26 #define CONFIG_ENV_IS_IN_FLASH
  27 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
  28 #define CONFIG_ENV_SECT_SIZE            0x20000
  29 #define CONFIG_ENV_SIZE                 0x20000
  30 #endif
  31
  32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  33 #ifndef CONFIG_SPL_BUILD
  34 #define CONFIG_QIXIS_I2C_ACCESS
  35 #endif
  36 #define SYS_NO_FLASH
  37 #undef CONFIG_CMD_IMLS
  38 #endif
  39
  40 #define CONFIG_SYS_CLK_FREQ             100000000
  41 #define CONFIG_DDR_CLK_FREQ             100000000
  42 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  43 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  44
  45 #define CONFIG_DDR_SPD
  46 #ifdef CONFIG_EMU
  47 #define CONFIG_SYS_FSL_DDR_EMU
  48 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  49 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  50 #else
  51 #define CONFIG_DDR_ECC
  52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  53 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  54 #endif
  55 #define SPD_EEPROM_ADDRESS      0x51
  56 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  57 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  58
  59
  60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  61 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  62 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  63 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  64
  65 #define CONFIG_SYS_NOR0_CSPR                                    \
  66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  67         CSPR_PORT_SIZE_16                                       | \
  68         CSPR_MSEL_NOR                                           | \
  69         CSPR_V)
  70 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  72         CSPR_PORT_SIZE_16                                       | \
  73         CSPR_MSEL_NOR                                           | \
  74         CSPR_V)
  75 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  76 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  77                                 FTIM0_NOR_TEADC(0x1) | \
  78                                 FTIM0_NOR_TEAHC(0x1))
  79 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  80                                 FTIM1_NOR_TRAD_NOR(0x1))
  81 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  82                                 FTIM2_NOR_TCH(0x0) | \
  83                                 FTIM2_NOR_TWP(0x1))
  84 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  85 #define CONFIG_SYS_IFC_CCR      0x01000000
  86
  87 #ifndef SYS_NO_FLASH
  88 #define CONFIG_FLASH_CFI_DRIVER
  89 #define CONFIG_SYS_FLASH_CFI
  90 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  91 #define CONFIG_SYS_FLASH_QUIET_TEST
  92 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  93
  94 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  95 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  96 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  97 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  98
  99 #define CONFIG_SYS_FLASH_EMPTY_INFO
 100 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 101 #endif
 102 #endif
 103
 104 #ifndef SPL_NO_IFC
 105 #define CONFIG_NAND_FSL_IFC
 106 #endif
 107
 108 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 109 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 110
 111 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 112 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 113                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 114                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 115                                 | CSPR_V)
 116 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 117
 118 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 119                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 120                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 121                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 122                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 123                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 124                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 125
 126 #define CONFIG_SYS_NAND_ONFI_DETECTION
 127
 128 /* ONFI NAND Flash mode0 Timing Params */
 129 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 130                                         FTIM0_NAND_TWP(0x18)   | \
 131                                         FTIM0_NAND_TWCHT(0x07) | \
 132                                         FTIM0_NAND_TWH(0x0a))
 133 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 134                                         FTIM1_NAND_TWBE(0x39)  | \
 135                                         FTIM1_NAND_TRR(0x0e)   | \
 136                                         FTIM1_NAND_TRP(0x18))
 137 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 138                                         FTIM2_NAND_TREH(0x0a) | \
 139                                         FTIM2_NAND_TWHRE(0x1e))
 140 #define CONFIG_SYS_NAND_FTIM3           0x0
 141
 142 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 143 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 144 #define CONFIG_MTD_NAND_VERIFY_WRITE
 145 #define CONFIG_CMD_NAND
 146
 147 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 148
 149 #ifndef SPL_NO_QIXIS
 150 #define CONFIG_FSL_QIXIS
 151 #endif
 152
 153 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 154 #define QIXIS_LBMAP_SWITCH              2
 155 #define QIXIS_QMAP_MASK                 0xe0
 156 #define QIXIS_QMAP_SHIFT                5
 157 #define QIXIS_LBMAP_MASK                0x1f
 158 #define QIXIS_LBMAP_SHIFT               5
 159 #define QIXIS_LBMAP_DFLTBANK            0x00
 160 #define QIXIS_LBMAP_ALTBANK             0x20
 161 #define QIXIS_LBMAP_SD                  0x00
 162 #define QIXIS_LBMAP_SD_QSPI             0x00
 163 #define QIXIS_LBMAP_QSPI                0x00
 164 #define QIXIS_RCW_SRC_SD                0x40
 165 #define QIXIS_RCW_SRC_QSPI              0x62
 166 #define QIXIS_RST_CTL_RESET             0x31
 167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 168 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 170 #define QIXIS_RST_FORCE_MEM             0x01
 171
 172 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 173 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 174                                         | CSPR_PORT_SIZE_8 \
 175                                         | CSPR_MSEL_GPCM \
 176                                         | CSPR_V)
 177 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 178                                         | CSPR_PORT_SIZE_8 \
 179                                         | CSPR_MSEL_GPCM \
 180                                         | CSPR_V)
 181
 182 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 183 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 184 /* QIXIS Timing parameters*/
 185 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 186                                         FTIM0_GPCM_TEADC(0x0e) | \
 187                                         FTIM0_GPCM_TEAHC(0x0e))
 188 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 189                                         FTIM1_GPCM_TRAD(0x3f))
 190 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 191                                         FTIM2_GPCM_TCH(0xf) | \
 192                                         FTIM2_GPCM_TWP(0x3E))
 193 #define SYS_FPGA_CS_FTIM3       0x0
 194
 195 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 196 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 197 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 198 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 199 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 200 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 201 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 202 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 203 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 204 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 205 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 206 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 207 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 208 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 209 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 210 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 211 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 212 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 213 #else
 214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 216 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 217 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 218 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 219 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 220 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 221 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 222 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 223 #endif
 224
 225
 226 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 227
 228 #define I2C_MUX_CH_VOL_MONITOR          0xA
 229 /* Voltage monitor on channel 2*/
 230 #define I2C_VOL_MONITOR_ADDR           0x63
 231 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 232 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 233 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 234
 235 /* PM Bus commands code for LTC3882*/
 236 #define PMBUS_CMD_PAGE                  0x0
 237 #define PMBUS_CMD_READ_VOUT             0x8B
 238 #define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
 239 #define PMBUS_CMD_VOUT_COMMAND          0x21
 240
 241 #define PWM_CHANNEL0                    0x0
 242
 243 /*
 244  * I2C bus multiplexer
 245  */
 246 #define I2C_MUX_PCA_ADDR_PRI            0x77
 247 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 248 #define I2C_RETIMER_ADDR                0x18
 249 #define I2C_MUX_CH_DEFAULT              0x8
 250 #define I2C_MUX_CH5                     0xD
 251
 252 #ifndef SPL_NO_RTC
 253 /*
 254 * RTC configuration
 255 */
 256 #define RTC
 257 #define CONFIG_RTC_PCF8563 1
 258 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 259 #define CONFIG_CMD_DATE
 260 #endif
 261
 262 /* EEPROM */
 263 #define CONFIG_ID_EEPROM
 264 #define CONFIG_SYS_I2C_EEPROM_NXID
 265 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 266 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 267 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 268 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 270
 271 #ifndef SPL_NO_QSPI
 272 /* QSPI device */
 273 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 274 #define CONFIG_FSL_QSPI
 275 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 276 #define FSL_QSPI_FLASH_NUM              2
 277 #endif
 278 #endif
 279
 280 #define CONFIG_CMD_MEMINFO
 281 #define CONFIG_CMD_MEMTEST
 282 #define CONFIG_SYS_MEMTEST_START        0x80000000
 283 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 284
 285 #ifdef CONFIG_SPL_BUILD
 286 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 287 #else
 288 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 289 #endif
 290
 291 #define CONFIG_FSL_MEMAC
 292
 293 #ifndef SPL_NO_ENV
 294 /* Initial environment variables */
 295 #if defined(CONFIG_QSPI_BOOT)
 296 #define MC_INIT_CMD                             \
 297         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 298         "sf read 0x80100000 0xE00000 0x100000;"                         \
 299         "env exists secureboot && "                     \
 300         "sf read 0x80700000 0x700000 0x40000 && "       \
 301         "sf read 0x80740000 0x740000 0x40000 && "       \
 302         "esbc_validate 0x80700000 && "                  \
 303         "esbc_validate 0x80740000 ;"                    \
 304         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 305         "mcmemsize=0x70000000\0"
 306 #elif defined(CONFIG_SD_BOOT)
 307 #define MC_INIT_CMD                             \
 308         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"           \
 309         "mmc read 0x80100000 0x7000 0x800;"                             \
 310         "env exists secureboot && "                     \
 311         "mmc read 0x80700000 0x3800 0x10 && "           \
 312         "mmc read 0x80740000 0x3A00 0x10 && "           \
 313         "esbc_validate 0x80700000 && "                  \
 314         "esbc_validate 0x80740000 ;"                    \
 315         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 316         "mcmemsize=0x70000000\0"
 317 #endif
 318
 319 #undef CONFIG_EXTRA_ENV_SETTINGS
 320 #define CONFIG_EXTRA_ENV_SETTINGS               \
 321         "BOARD=ls1088ardb\0"                    \
 322         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 323         "ramdisk_addr=0x800000\0"               \
 324         "ramdisk_size=0x2000000\0"              \
 325         "fdt_high=0xa0000000\0"                 \
 326         "initrd_high=0xffffffffffffffff\0"      \
 327         "fdt_addr=0x64f00000\0"                 \
 328         "kernel_addr=0x1000000\0"               \
 329         "kernel_addr_sd=0x8000\0"               \
 330         "kernelhdr_addr_sd=0x4000\0"            \
 331         "kernel_start=0x580100000\0"            \
 332         "kernelheader_start=0x580800000\0"      \
 333         "scriptaddr=0x80000000\0"               \
 334         "scripthdraddr=0x80080000\0"            \
 335         "fdtheader_addr_r=0x80100000\0"         \
 336         "kernelheader_addr=0x800000\0"          \
 337         "kernelheader_addr_r=0x80200000\0"      \
 338         "kernel_addr_r=0x81000000\0"            \
 339         "kernelheader_size=0x40000\0"           \
 340         "fdt_addr_r=0x90000000\0"               \
 341         "load_addr=0xa0000000\0"                \
 342         "kernel_size=0x2800000\0"               \
 343         "kernel_size_sd=0x14000\0"              \
 344         "kernelhdr_size_sd=0x10\0"              \
 345         MC_INIT_CMD                             \
 346         BOOTENV                                 \
 347         "boot_scripts=ls1088ardb_boot.scr\0"    \
 348         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 349         "scan_dev_for_boot_part="               \
 350                 "part list ${devtype} ${devnum} devplist; "     \
 351                 "env exists devplist || setenv devplist 1; "    \
 352                 "for distro_bootpart in ${devplist}; do "       \
 353                         "if fstype ${devtype} "                 \
 354                                 "${devnum}:${distro_bootpart} " \
 355                                 "bootfstype; then "             \
 356                                 "run scan_dev_for_boot; "       \
 357                         "fi; "                                  \
 358                 "done\0"                                        \
 359         "scan_dev_for_boot="                                    \
 360                 "echo Scanning ${devtype} "                     \
 361                 "${devnum}:${distro_bootpart}...; "             \
 362                 "for prefix in ${boot_prefixes}; do "           \
 363                         "run scan_dev_for_scripts; "            \
 364                 "done;\0"                                       \
 365         "boot_a_script="                                        \
 366                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 367                 "${scriptaddr} ${prefix}${script}; "            \
 368         "env exists secureboot && load ${devtype} "             \
 369                 "${devnum}:${distro_bootpart} "                 \
 370                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 371                 "&& esbc_validate ${scripthdraddr};"            \
 372                 "source ${scriptaddr}\0"                        \
 373         "installer=load mmc 0:2 $load_addr "                    \
 374                 "/flex_installer_arm64.itb; "                   \
 375                 "env exists mcinitcmd && run mcinitcmd && "     \
 376                 "mmc read 0x80200000 0x6800 0x800;"             \
 377                 "fsl_mc apply dpl 0x80200000;"                  \
 378                 "bootm $load_addr#ls1088ardb\0"                 \
 379         "qspi_bootcmd=echo Trying load from qspi..;"            \
 380                 "sf probe && sf read $load_addr "               \
 381                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 382                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 383                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 384                 "bootm $load_addr#$BOARD\0"                     \
 385                 "sd_bootcmd=echo Trying load from sd card..;"           \
 386                 "mmcinfo; mmc read $load_addr "                 \
 387                 "$kernel_addr_sd $kernel_size_sd ;"             \
 388                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 389                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 390                 " && esbc_validate ${kernelheader_addr_r};"     \
 391                 "bootm $load_addr#$BOARD\0"
 392
 393 #undef CONFIG_BOOTCOMMAND
 394 #if defined(CONFIG_QSPI_BOOT)
 395 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 396 #define CONFIG_BOOTCOMMAND                                      \
 397                 "sf read 0x80200000 0xd00000 0x100000;"         \
 398                 "env exists mcinitcmd && env exists secureboot "        \
 399                 " && sf read 0x80780000 0x780000 0x100000 "     \
 400                 "&& esbc_validate 0x80780000;env exists mcinitcmd "     \
 401                 "&& fsl_mc apply dpl 0x80200000;"               \
 402                 "run distro_bootcmd;run qspi_bootcmd;"          \
 403                 "env exists secureboot && esbc_halt;"
 404
 405 /* Try to boot an on-SD kernel first, then do normal distro boot */
 406 #elif defined(CONFIG_SD_BOOT)
 407 #define CONFIG_BOOTCOMMAND                                      \
 408                 "env exists mcinitcmd && mmcinfo; "             \
 409                 "mmc read 0x80200000 0x6800 0x800; "            \
 410                 "env exists mcinitcmd && env exists secureboot "        \
 411                 " && mmc read 0x80780000 0x3800 0x10 "          \
 412                 "&& esbc_validate 0x80780000;env exists mcinitcmd "     \
 413                 "&& fsl_mc apply dpl 0x80200000;"               \
 414                 "run distro_bootcmd;run sd_bootcmd;"            \
 415                 "env exists secureboot && esbc_halt;"
 416 #endif
 417
 418 /* MAC/PHY configuration */
 419 #ifdef CONFIG_FSL_MC_ENET
 420 #define CONFIG_PHYLIB_10G
 421 #define CONFIG_PHY_GIGE
 422 #define CONFIG_PHYLIB
 423
 424 #define CONFIG_PHY_VITESSE
 425 #define CONFIG_PHY_AQUANTIA
 426 #define AQ_PHY_ADDR1                    0x00
 427 #define AQR105_IRQ_MASK                 0x00000004
 428
 429 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 430 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 431 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 432 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 433 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 434 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 435 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 436 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 437
 438 #define CONFIG_MII
 439 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 440 #define CONFIG_PHY_GIGE
 441 #endif
 442 #endif
 443
 444 /*  MMC  */
 445 #ifdef CONFIG_MMC
 446 #define CONFIG_FSL_ESDHC
 447 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 448 #endif
 449
 450 #ifndef SPL_NO_ENV
 451 #undef CONFIG_CMDLINE_EDITING
 452 #include <config_distro_defaults.h>
 453
 454 #define BOOT_TARGET_DEVICES(func) \
 455         func(MMC, mmc, 0) \
 456         func(SCSI, scsi, 0) \
 457         func(DHCP, dhcp, na)
 458 #include <config_distro_bootcmd.h>
 459 #endif
 460
 461 #include <asm/fsl_secure_boot.h>
 462
 463 #endif /* __LS1088A_RDB_H */