include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #define SYS_NO_FLASH
  14 #endif
  15
  16 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  17
  18 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  19 #define SPD_EEPROM_ADDRESS      0x51
  20 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  21
  22
  23 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  24 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  25 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  26 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  27
  28 #define CONFIG_SYS_NOR0_CSPR                                    \
  29         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  30         CSPR_PORT_SIZE_16                                       | \
  31         CSPR_MSEL_NOR                                           | \
  32         CSPR_V)
  33 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  34         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  35         CSPR_PORT_SIZE_16                                       | \
  36         CSPR_MSEL_NOR                                           | \
  37         CSPR_V)
  38 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  39 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  40                                 FTIM0_NOR_TEADC(0x1) | \
  41                                 FTIM0_NOR_TEAHC(0x1))
  42 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  43                                 FTIM1_NOR_TRAD_NOR(0x1))
  44 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  45                                 FTIM2_NOR_TCH(0x0) | \
  46                                 FTIM2_NOR_TWP(0x1))
  47 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  48 #define CONFIG_SYS_IFC_CCR      0x01000000
  49
  50 #ifndef SYS_NO_FLASH
  51 #define CONFIG_SYS_FLASH_QUIET_TEST
  52 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  53
  54 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  55 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  56 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  57
  58 #define CONFIG_SYS_FLASH_EMPTY_INFO
  59 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  60 #endif
  61 #endif
  62
  63 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  64 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  65
  66 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  67 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  68                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  69                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  70                                 | CSPR_V)
  71 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  72
  73 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  74                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  75                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  76                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  77                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  78                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  79                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  80
  81 /* ONFI NAND Flash mode0 Timing Params */
  82 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
  83                                         FTIM0_NAND_TWP(0x18)   | \
  84                                         FTIM0_NAND_TWCHT(0x07) | \
  85                                         FTIM0_NAND_TWH(0x0a))
  86 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
  87                                         FTIM1_NAND_TWBE(0x39)  | \
  88                                         FTIM1_NAND_TRR(0x0e)   | \
  89                                         FTIM1_NAND_TRP(0x18))
  90 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
  91                                         FTIM2_NAND_TREH(0x0a) | \
  92                                         FTIM2_NAND_TWHRE(0x1e))
  93 #define CONFIG_SYS_NAND_FTIM3           0x0
  94
  95 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
  96 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  97 #define CONFIG_MTD_NAND_VERIFY_WRITE
  98
  99 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 100 #define QIXIS_BRDCFG4_OFFSET            0x54
 101 #define QIXIS_LBMAP_SWITCH              2
 102 #define QIXIS_QMAP_MASK                 0xe0
 103 #define QIXIS_QMAP_SHIFT                5
 104 #define QIXIS_LBMAP_MASK                0x1f
 105 #define QIXIS_LBMAP_SHIFT               5
 106 #define QIXIS_LBMAP_DFLTBANK            0x00
 107 #define QIXIS_LBMAP_ALTBANK             0x20
 108 #define QIXIS_LBMAP_SD                  0x00
 109 #define QIXIS_LBMAP_EMMC                0x00
 110 #define QIXIS_LBMAP_SD_QSPI             0x00
 111 #define QIXIS_LBMAP_QSPI                0x00
 112 #define QIXIS_RCW_SRC_SD                0x40
 113 #define QIXIS_RCW_SRC_EMMC              0x41
 114 #define QIXIS_RCW_SRC_QSPI              0x62
 115 #define QIXIS_RST_CTL_RESET             0x31
 116 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 117 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 118 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 119 #define QIXIS_RST_FORCE_MEM             0x01
 120
 121 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 122 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 123                                         | CSPR_PORT_SIZE_8 \
 124                                         | CSPR_MSEL_GPCM \
 125                                         | CSPR_V)
 126 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 127                                         | CSPR_PORT_SIZE_8 \
 128                                         | CSPR_MSEL_GPCM \
 129                                         | CSPR_V)
 130
 131 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 132 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 133 /* QIXIS Timing parameters*/
 134 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 135                                         FTIM0_GPCM_TEADC(0x0e) | \
 136                                         FTIM0_GPCM_TEAHC(0x0e))
 137 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 138                                         FTIM1_GPCM_TRAD(0x3f))
 139 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 140                                         FTIM2_GPCM_TCH(0xf) | \
 141                                         FTIM2_GPCM_TWP(0x3E))
 142 #define SYS_FPGA_CS_FTIM3       0x0
 143
 144 #if defined(CONFIG_TFABOOT) || \
 145         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 146 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 147 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 148 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 149 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 150 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 151 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 152 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 153 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 154 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 155 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 156 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 157 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 158 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 159 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 160 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 161 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 162 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 163 #else
 164 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 165 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 166 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 167 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 168 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 169 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 170 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 171 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 172 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 173 #endif
 174
 175 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 176
 177 #define I2C_MUX_CH_VOL_MONITOR         0xA
 178 /* Voltage monitor on channel 2*/
 179 #define I2C_VOL_MONITOR_ADDR           0x63
 180 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 181 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 182 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 183 #define I2C_SVDD_MONITOR_ADDR           0x4F
 184
 185 /* The lowest and highest voltage allowed for LS1088ARDB */
 186 #define VDD_MV_MIN                      819
 187 #define VDD_MV_MAX                      1212
 188
 189 #define PWM_CHANNEL0                    0x0
 190
 191 /*
 192  * I2C bus multiplexer
 193  */
 194 #define I2C_MUX_PCA_ADDR_PRI            0x77
 195 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 196 #define I2C_RETIMER_ADDR                0x18
 197 #define I2C_MUX_CH_DEFAULT              0x8
 198 #define I2C_MUX_CH5                     0xD
 199
 200 #ifndef SPL_NO_RTC
 201 /*
 202 * RTC configuration
 203 */
 204 #define RTC
 205 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 206 #endif
 207
 208 /* EEPROM */
 209 #define CONFIG_SYS_I2C_EEPROM_NXID
 210 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 211
 212 #define CONFIG_FSL_MEMAC
 213
 214 #ifndef SPL_NO_ENV
 215 /* Initial environment variables */
 216 #ifdef CONFIG_TFABOOT
 217 #define QSPI_MC_INIT_CMD                                \
 218         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 219         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 220         "env exists secureboot && "                     \
 221         "sf read 0x80640000 0x640000 0x40000 && "       \
 222         "sf read 0x80680000 0x680000 0x40000 && "       \
 223         "esbc_validate 0x80640000 && "                  \
 224         "esbc_validate 0x80680000 ;"                    \
 225         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 226 #define SD_MC_INIT_CMD                          \
 227         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 228         "mmc read 0x80e00000 0x7000 0x800;"                             \
 229         "env exists secureboot && "                     \
 230         "mmc read 0x80640000 0x3200 0x20 && "           \
 231         "mmc read 0x80680000 0x3400 0x20 && "           \
 232         "esbc_validate 0x80640000 && "                  \
 233         "esbc_validate 0x80680000 ;"                    \
 234         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 235 #else
 236 #if defined(CONFIG_QSPI_BOOT)
 237 #define MC_INIT_CMD                             \
 238         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 239         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 240         "env exists secureboot && "                     \
 241         "sf read 0x80640000 0x640000 0x40000 && "       \
 242         "sf read 0x80680000 0x680000 0x40000 && "       \
 243         "esbc_validate 0x80640000 && "                  \
 244         "esbc_validate 0x80680000 ;"                    \
 245         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 246         "mcmemsize=0x70000000\0"
 247 #elif defined(CONFIG_SD_BOOT)
 248 #define MC_INIT_CMD                             \
 249         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 250         "mmc read 0x80e00000 0x7000 0x800;"                             \
 251         "env exists secureboot && "                     \
 252         "mmc read 0x80640000 0x3200 0x20 && "           \
 253         "mmc read 0x80680000 0x3400 0x20 && "           \
 254         "esbc_validate 0x80640000 && "                  \
 255         "esbc_validate 0x80680000 ;"                    \
 256         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 257         "mcmemsize=0x70000000\0"
 258 #endif
 259 #endif /* CONFIG_TFABOOT */
 260
 261 #undef CONFIG_EXTRA_ENV_SETTINGS
 262 #ifdef CONFIG_TFABOOT
 263 #define CONFIG_EXTRA_ENV_SETTINGS               \
 264         "BOARD=ls1088ardb\0"                    \
 265         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 266         "ramdisk_addr=0x800000\0"               \
 267         "ramdisk_size=0x2000000\0"              \
 268         "fdt_high=0xa0000000\0"                 \
 269         "initrd_high=0xffffffffffffffff\0"      \
 270         "kernel_addr=0x1000000\0"               \
 271         "kernel_addr_sd=0x8000\0"               \
 272         "kernelhdr_addr_sd=0x3000\0"            \
 273         "kernel_start=0x580100000\0"            \
 274         "kernelheader_start=0x580600000\0"      \
 275         "scriptaddr=0x80000000\0"               \
 276         "scripthdraddr=0x80080000\0"            \
 277         "fdtheader_addr_r=0x80100000\0"         \
 278         "kernelheader_addr=0x600000\0"          \
 279         "kernelheader_addr_r=0x80200000\0"      \
 280         "kernel_addr_r=0x81000000\0"            \
 281         "kernelheader_size=0x40000\0"           \
 282         "fdt_addr_r=0x90000000\0"               \
 283         "load_addr=0xa0000000\0"                \
 284         "kernel_size=0x2800000\0"               \
 285         "kernel_size_sd=0x14000\0"              \
 286         "kernelhdr_size_sd=0x20\0"              \
 287         QSPI_MC_INIT_CMD                        \
 288         "mcmemsize=0x70000000\0"                \
 289         BOOTENV                                 \
 290         "boot_scripts=ls1088ardb_boot.scr\0"    \
 291         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 292         "scan_dev_for_boot_part="               \
 293                 "part list ${devtype} ${devnum} devplist; "     \
 294                 "env exists devplist || setenv devplist 1; "    \
 295                 "for distro_bootpart in ${devplist}; do "       \
 296                         "if fstype ${devtype} "                 \
 297                                 "${devnum}:${distro_bootpart} " \
 298                                 "bootfstype; then "             \
 299                                 "run scan_dev_for_boot; "       \
 300                         "fi; "                                  \
 301                 "done\0"                                        \
 302         "boot_a_script="                                        \
 303                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 304                 "${scriptaddr} ${prefix}${script}; "            \
 305         "env exists secureboot && load ${devtype} "             \
 306                 "${devnum}:${distro_bootpart} "                 \
 307                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 308                 "env exists secureboot "                        \
 309                 "&& esbc_validate ${scripthdraddr};"            \
 310                 "source ${scriptaddr}\0"                        \
 311         "installer=load mmc 0:2 $load_addr "                    \
 312                 "/flex_installer_arm64.itb; "                   \
 313                 "env exists mcinitcmd && run mcinitcmd && "     \
 314                 "mmc read 0x80001000 0x6800 0x800;"             \
 315                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 316                 "bootm $load_addr#ls1088ardb\0"                 \
 317         "qspi_bootcmd=echo Trying load from qspi..;"            \
 318                 "sf probe && sf read $load_addr "               \
 319                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 320                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 321                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 322                 "bootm $load_addr#$BOARD\0"                     \
 323                 "sd_bootcmd=echo Trying load from sd card..;"           \
 324                 "mmcinfo; mmc read $load_addr "                 \
 325                 "$kernel_addr_sd $kernel_size_sd ;"             \
 326                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 327                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 328                 " && esbc_validate ${kernelheader_addr_r};"     \
 329                 "bootm $load_addr#$BOARD\0"
 330 #else
 331 #define CONFIG_EXTRA_ENV_SETTINGS               \
 332         "BOARD=ls1088ardb\0"                    \
 333         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 334         "ramdisk_addr=0x800000\0"               \
 335         "ramdisk_size=0x2000000\0"              \
 336         "fdt_high=0xa0000000\0"                 \
 337         "initrd_high=0xffffffffffffffff\0"      \
 338         "kernel_addr=0x1000000\0"               \
 339         "kernel_addr_sd=0x8000\0"               \
 340         "kernelhdr_addr_sd=0x3000\0"            \
 341         "kernel_start=0x580100000\0"            \
 342         "kernelheader_start=0x580800000\0"      \
 343         "scriptaddr=0x80000000\0"               \
 344         "scripthdraddr=0x80080000\0"            \
 345         "fdtheader_addr_r=0x80100000\0"         \
 346         "kernelheader_addr=0x600000\0"          \
 347         "kernelheader_addr_r=0x80200000\0"      \
 348         "kernel_addr_r=0x81000000\0"            \
 349         "kernelheader_size=0x40000\0"           \
 350         "fdt_addr_r=0x90000000\0"               \
 351         "load_addr=0xa0000000\0"                \
 352         "kernel_size=0x2800000\0"               \
 353         "kernel_size_sd=0x14000\0"              \
 354         "kernelhdr_size_sd=0x20\0"              \
 355         MC_INIT_CMD                             \
 356         BOOTENV                                 \
 357         "boot_scripts=ls1088ardb_boot.scr\0"    \
 358         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 359         "scan_dev_for_boot_part="               \
 360                 "part list ${devtype} ${devnum} devplist; "     \
 361                 "env exists devplist || setenv devplist 1; "    \
 362                 "for distro_bootpart in ${devplist}; do "       \
 363                         "if fstype ${devtype} "                 \
 364                                 "${devnum}:${distro_bootpart} " \
 365                                 "bootfstype; then "             \
 366                                 "run scan_dev_for_boot; "       \
 367                         "fi; "                                  \
 368                 "done\0"                                        \
 369         "boot_a_script="                                        \
 370                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 371                 "${scriptaddr} ${prefix}${script}; "            \
 372         "env exists secureboot && load ${devtype} "             \
 373                 "${devnum}:${distro_bootpart} "                 \
 374                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 375                 "&& esbc_validate ${scripthdraddr};"            \
 376                 "source ${scriptaddr}\0"                        \
 377         "installer=load mmc 0:2 $load_addr "                    \
 378                 "/flex_installer_arm64.itb; "                   \
 379                 "env exists mcinitcmd && run mcinitcmd && "     \
 380                 "mmc read 0x80001000 0x6800 0x800;"             \
 381                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 382                 "bootm $load_addr#ls1088ardb\0"                 \
 383         "qspi_bootcmd=echo Trying load from qspi..;"            \
 384                 "sf probe && sf read $load_addr "               \
 385                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 386                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 387                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 388                 "bootm $load_addr#$BOARD\0"                     \
 389                 "sd_bootcmd=echo Trying load from sd card..;"           \
 390                 "mmcinfo; mmc read $load_addr "                 \
 391                 "$kernel_addr_sd $kernel_size_sd ;"             \
 392                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 393                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 394                 " && esbc_validate ${kernelheader_addr_r};"     \
 395                 "bootm $load_addr#$BOARD\0"
 396 #endif /* CONFIG_TFABOOT */
 397
 398 #ifdef CONFIG_TFABOOT
 399 #define QSPI_NOR_BOOTCOMMAND                                    \
 400         "sf read 0x80001000 0xd00000 0x100000;"         \
 401                 "env exists mcinitcmd && env exists secureboot "        \
 402                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 403                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 404                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 405                 "run distro_bootcmd;run qspi_bootcmd;"          \
 406                 "env exists secureboot && esbc_halt;"
 407 #define SD_BOOTCOMMAND                                          \
 408                 "env exists mcinitcmd && mmcinfo; "             \
 409                 "mmc read 0x80001000 0x6800 0x800; "            \
 410                 "env exists mcinitcmd && env exists secureboot "        \
 411                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 412                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 413                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 414                 "run distro_bootcmd;run sd_bootcmd;"            \
 415                 "env exists secureboot && esbc_halt;"
 416 #else
 417 #if defined(CONFIG_QSPI_BOOT)
 418 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 419
 420 /* Try to boot an on-SD kernel first, then do normal distro boot */
 421 #endif
 422 #endif /* CONFIG_TFABOOT */
 423
 424 /* MAC/PHY configuration */
 425 #ifdef CONFIG_FSL_MC_ENET
 426 #define AQ_PHY_ADDR1                    0x00
 427 #define AQR105_IRQ_MASK                 0x00000004
 428
 429 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 430 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 431 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 432 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 433 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 434 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 435 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 436 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 437 #endif
 438 #endif
 439
 440 #ifndef SPL_NO_ENV
 441
 442 #define BOOT_TARGET_DEVICES(func) \
 443         func(MMC, mmc, 0) \
 444         func(USB, usb, 0) \
 445         func(SCSI, scsi, 0) \
 446         func(DHCP, dhcp, na)
 447 #include <config_distro_bootcmd.h>
 448 #endif
 449
 450 #include <asm/fsl_secure_boot.h>
 451
 452 #endif /* __LS1088A_RDB_H */