1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
13 #ifndef CONFIG_SPL_BUILD
14 #define CONFIG_QIXIS_I2C_ACCESS
19 #define CONFIG_SYS_CLK_FREQ 100000000
20 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
21 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
24 #define CONFIG_SYS_FSL_DDR_EMU
26 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
28 #define SPD_EEPROM_ADDRESS 0x51
29 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
30 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
33 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
34 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
35 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
36 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
38 #define CONFIG_SYS_NOR0_CSPR \
39 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
43 #define CONFIG_SYS_NOR0_CSPR_EARLY \
44 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
48 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
49 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
50 FTIM0_NOR_TEADC(0x1) | \
52 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
53 FTIM1_NOR_TRAD_NOR(0x1))
54 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
55 FTIM2_NOR_TCH(0x0) | \
57 #define CONFIG_SYS_NOR_FTIM3 0x04000000
58 #define CONFIG_SYS_IFC_CCR 0x01000000
61 #define CONFIG_SYS_FLASH_QUIET_TEST
62 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
64 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
65 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
66 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
67 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
69 #define CONFIG_SYS_FLASH_EMPTY_INFO
70 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
74 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
75 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
77 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
78 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
79 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
80 | CSPR_MSEL_NAND /* MSEL = NAND */ \
82 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
84 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
85 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
86 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
87 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
88 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
89 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
90 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
92 /* ONFI NAND Flash mode0 Timing Params */
93 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
94 FTIM0_NAND_TWP(0x18) | \
95 FTIM0_NAND_TWCHT(0x07) | \
97 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
98 FTIM1_NAND_TWBE(0x39) | \
99 FTIM1_NAND_TRR(0x0e) | \
100 FTIM1_NAND_TRP(0x18))
101 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
102 FTIM2_NAND_TREH(0x0a) | \
103 FTIM2_NAND_TWHRE(0x1e))
104 #define CONFIG_SYS_NAND_FTIM3 0x0
106 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
107 #define CONFIG_SYS_MAX_NAND_DEVICE 1
108 #define CONFIG_MTD_NAND_VERIFY_WRITE
111 #define CONFIG_FSL_QIXIS
114 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
115 #define QIXIS_BRDCFG4_OFFSET 0x54
116 #define QIXIS_LBMAP_SWITCH 2
117 #define QIXIS_QMAP_MASK 0xe0
118 #define QIXIS_QMAP_SHIFT 5
119 #define QIXIS_LBMAP_MASK 0x1f
120 #define QIXIS_LBMAP_SHIFT 5
121 #define QIXIS_LBMAP_DFLTBANK 0x00
122 #define QIXIS_LBMAP_ALTBANK 0x20
123 #define QIXIS_LBMAP_SD 0x00
124 #define QIXIS_LBMAP_EMMC 0x00
125 #define QIXIS_LBMAP_SD_QSPI 0x00
126 #define QIXIS_LBMAP_QSPI 0x00
127 #define QIXIS_RCW_SRC_SD 0x40
128 #define QIXIS_RCW_SRC_EMMC 0x41
129 #define QIXIS_RCW_SRC_QSPI 0x62
130 #define QIXIS_RST_CTL_RESET 0x31
131 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
132 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
133 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
134 #define QIXIS_RST_FORCE_MEM 0x01
136 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
137 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
141 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
146 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
147 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
148 /* QIXIS Timing parameters*/
149 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
150 FTIM0_GPCM_TEADC(0x0e) | \
151 FTIM0_GPCM_TEAHC(0x0e))
152 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
153 FTIM1_GPCM_TRAD(0x3f))
154 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
155 FTIM2_GPCM_TCH(0xf) | \
156 FTIM2_GPCM_TWP(0x3E))
157 #define SYS_FPGA_CS_FTIM3 0x0
159 #if defined(CONFIG_TFABOOT) || \
160 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
161 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
162 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
163 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
164 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
165 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
166 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
167 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
168 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
169 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
170 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
171 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
172 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
173 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
174 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
175 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
176 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
177 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
179 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
180 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
181 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
182 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
183 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
184 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
185 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
186 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
187 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
190 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
192 #define I2C_MUX_CH_VOL_MONITOR 0xA
193 /* Voltage monitor on channel 2*/
194 #define I2C_VOL_MONITOR_ADDR 0x63
195 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
196 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
197 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
198 #define I2C_SVDD_MONITOR_ADDR 0x4F
200 #define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
203 /* The lowest and highest voltage allowed for LS1088ARDB */
204 #define VDD_MV_MIN 819
205 #define VDD_MV_MAX 1212
207 #define CONFIG_VOL_MONITOR_LTC3882_SET
208 #define CONFIG_VOL_MONITOR_LTC3882_READ
210 #define PWM_CHANNEL0 0x0
213 * I2C bus multiplexer
215 #define I2C_MUX_PCA_ADDR_PRI 0x77
216 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
217 #define I2C_RETIMER_ADDR 0x18
218 #define I2C_MUX_CH_DEFAULT 0x8
219 #define I2C_MUX_CH5 0xD
226 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
230 #define CONFIG_SYS_I2C_EEPROM_NXID
231 #define CONFIG_SYS_EEPROM_BUS_NUM 0
233 #ifdef CONFIG_SPL_BUILD
234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
239 #define CONFIG_FSL_MEMAC
242 /* Initial environment variables */
243 #ifdef CONFIG_TFABOOT
244 #define QSPI_MC_INIT_CMD \
245 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
246 "sf read 0x80e00000 0xE00000 0x100000;" \
247 "env exists secureboot && " \
248 "sf read 0x80640000 0x640000 0x40000 && " \
249 "sf read 0x80680000 0x680000 0x40000 && " \
250 "esbc_validate 0x80640000 && " \
251 "esbc_validate 0x80680000 ;" \
252 "fsl_mc start mc 0x80a00000 0x80e00000\0"
253 #define SD_MC_INIT_CMD \
254 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
255 "mmc read 0x80e00000 0x7000 0x800;" \
256 "env exists secureboot && " \
257 "mmc read 0x80640000 0x3200 0x20 && " \
258 "mmc read 0x80680000 0x3400 0x20 && " \
259 "esbc_validate 0x80640000 && " \
260 "esbc_validate 0x80680000 ;" \
261 "fsl_mc start mc 0x80a00000 0x80e00000\0"
263 #if defined(CONFIG_QSPI_BOOT)
264 #define MC_INIT_CMD \
265 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
266 "sf read 0x80e00000 0xE00000 0x100000;" \
267 "env exists secureboot && " \
268 "sf read 0x80640000 0x640000 0x40000 && " \
269 "sf read 0x80680000 0x680000 0x40000 && " \
270 "esbc_validate 0x80640000 && " \
271 "esbc_validate 0x80680000 ;" \
272 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
273 "mcmemsize=0x70000000\0"
274 #elif defined(CONFIG_SD_BOOT)
275 #define MC_INIT_CMD \
276 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
277 "mmc read 0x80e00000 0x7000 0x800;" \
278 "env exists secureboot && " \
279 "mmc read 0x80640000 0x3200 0x20 && " \
280 "mmc read 0x80680000 0x3400 0x20 && " \
281 "esbc_validate 0x80640000 && " \
282 "esbc_validate 0x80680000 ;" \
283 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
284 "mcmemsize=0x70000000\0"
286 #endif /* CONFIG_TFABOOT */
288 #undef CONFIG_EXTRA_ENV_SETTINGS
289 #ifdef CONFIG_TFABOOT
290 #define CONFIG_EXTRA_ENV_SETTINGS \
291 "BOARD=ls1088ardb\0" \
292 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
293 "ramdisk_addr=0x800000\0" \
294 "ramdisk_size=0x2000000\0" \
295 "fdt_high=0xa0000000\0" \
296 "initrd_high=0xffffffffffffffff\0" \
297 "fdt_addr=0x64f00000\0" \
298 "kernel_addr=0x1000000\0" \
299 "kernel_addr_sd=0x8000\0" \
300 "kernelhdr_addr_sd=0x3000\0" \
301 "kernel_start=0x580100000\0" \
302 "kernelheader_start=0x580600000\0" \
303 "scriptaddr=0x80000000\0" \
304 "scripthdraddr=0x80080000\0" \
305 "fdtheader_addr_r=0x80100000\0" \
306 "kernelheader_addr=0x600000\0" \
307 "kernelheader_addr_r=0x80200000\0" \
308 "kernel_addr_r=0x81000000\0" \
309 "kernelheader_size=0x40000\0" \
310 "fdt_addr_r=0x90000000\0" \
311 "load_addr=0xa0000000\0" \
312 "kernel_size=0x2800000\0" \
313 "kernel_size_sd=0x14000\0" \
314 "kernelhdr_size_sd=0x20\0" \
316 "mcmemsize=0x70000000\0" \
318 "boot_scripts=ls1088ardb_boot.scr\0" \
319 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
320 "scan_dev_for_boot_part=" \
321 "part list ${devtype} ${devnum} devplist; " \
322 "env exists devplist || setenv devplist 1; " \
323 "for distro_bootpart in ${devplist}; do " \
324 "if fstype ${devtype} " \
325 "${devnum}:${distro_bootpart} " \
326 "bootfstype; then " \
327 "run scan_dev_for_boot; " \
331 "load ${devtype} ${devnum}:${distro_bootpart} " \
332 "${scriptaddr} ${prefix}${script}; " \
333 "env exists secureboot && load ${devtype} " \
334 "${devnum}:${distro_bootpart} " \
335 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
336 "env exists secureboot " \
337 "&& esbc_validate ${scripthdraddr};" \
338 "source ${scriptaddr}\0" \
339 "installer=load mmc 0:2 $load_addr " \
340 "/flex_installer_arm64.itb; " \
341 "env exists mcinitcmd && run mcinitcmd && " \
342 "mmc read 0x80001000 0x6800 0x800;" \
343 "fsl_mc lazyapply dpl 0x80001000;" \
344 "bootm $load_addr#ls1088ardb\0" \
345 "qspi_bootcmd=echo Trying load from qspi..;" \
346 "sf probe && sf read $load_addr " \
347 "$kernel_addr $kernel_size ; env exists secureboot " \
348 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
349 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
350 "bootm $load_addr#$BOARD\0" \
351 "sd_bootcmd=echo Trying load from sd card..;" \
352 "mmcinfo; mmc read $load_addr " \
353 "$kernel_addr_sd $kernel_size_sd ;" \
354 "env exists secureboot && mmc read $kernelheader_addr_r "\
355 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
356 " && esbc_validate ${kernelheader_addr_r};" \
357 "bootm $load_addr#$BOARD\0"
359 #define CONFIG_EXTRA_ENV_SETTINGS \
360 "BOARD=ls1088ardb\0" \
361 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
362 "ramdisk_addr=0x800000\0" \
363 "ramdisk_size=0x2000000\0" \
364 "fdt_high=0xa0000000\0" \
365 "initrd_high=0xffffffffffffffff\0" \
366 "fdt_addr=0x64f00000\0" \
367 "kernel_addr=0x1000000\0" \
368 "kernel_addr_sd=0x8000\0" \
369 "kernelhdr_addr_sd=0x3000\0" \
370 "kernel_start=0x580100000\0" \
371 "kernelheader_start=0x580800000\0" \
372 "scriptaddr=0x80000000\0" \
373 "scripthdraddr=0x80080000\0" \
374 "fdtheader_addr_r=0x80100000\0" \
375 "kernelheader_addr=0x600000\0" \
376 "kernelheader_addr_r=0x80200000\0" \
377 "kernel_addr_r=0x81000000\0" \
378 "kernelheader_size=0x40000\0" \
379 "fdt_addr_r=0x90000000\0" \
380 "load_addr=0xa0000000\0" \
381 "kernel_size=0x2800000\0" \
382 "kernel_size_sd=0x14000\0" \
383 "kernelhdr_size_sd=0x20\0" \
386 "boot_scripts=ls1088ardb_boot.scr\0" \
387 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
388 "scan_dev_for_boot_part=" \
389 "part list ${devtype} ${devnum} devplist; " \
390 "env exists devplist || setenv devplist 1; " \
391 "for distro_bootpart in ${devplist}; do " \
392 "if fstype ${devtype} " \
393 "${devnum}:${distro_bootpart} " \
394 "bootfstype; then " \
395 "run scan_dev_for_boot; " \
399 "load ${devtype} ${devnum}:${distro_bootpart} " \
400 "${scriptaddr} ${prefix}${script}; " \
401 "env exists secureboot && load ${devtype} " \
402 "${devnum}:${distro_bootpart} " \
403 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
404 "&& esbc_validate ${scripthdraddr};" \
405 "source ${scriptaddr}\0" \
406 "installer=load mmc 0:2 $load_addr " \
407 "/flex_installer_arm64.itb; " \
408 "env exists mcinitcmd && run mcinitcmd && " \
409 "mmc read 0x80001000 0x6800 0x800;" \
410 "fsl_mc lazyapply dpl 0x80001000;" \
411 "bootm $load_addr#ls1088ardb\0" \
412 "qspi_bootcmd=echo Trying load from qspi..;" \
413 "sf probe && sf read $load_addr " \
414 "$kernel_addr $kernel_size ; env exists secureboot " \
415 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
416 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
417 "bootm $load_addr#$BOARD\0" \
418 "sd_bootcmd=echo Trying load from sd card..;" \
419 "mmcinfo; mmc read $load_addr " \
420 "$kernel_addr_sd $kernel_size_sd ;" \
421 "env exists secureboot && mmc read $kernelheader_addr_r "\
422 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
423 " && esbc_validate ${kernelheader_addr_r};" \
424 "bootm $load_addr#$BOARD\0"
425 #endif /* CONFIG_TFABOOT */
427 #undef CONFIG_BOOTCOMMAND
428 #ifdef CONFIG_TFABOOT
429 #define QSPI_NOR_BOOTCOMMAND \
430 "sf read 0x80001000 0xd00000 0x100000;" \
431 "env exists mcinitcmd && env exists secureboot " \
432 " && sf read 0x806C0000 0x6C0000 0x100000 " \
433 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
434 "&& fsl_mc lazyapply dpl 0x80001000;" \
435 "run distro_bootcmd;run qspi_bootcmd;" \
436 "env exists secureboot && esbc_halt;"
437 #define SD_BOOTCOMMAND \
438 "env exists mcinitcmd && mmcinfo; " \
439 "mmc read 0x80001000 0x6800 0x800; " \
440 "env exists mcinitcmd && env exists secureboot " \
441 " && mmc read 0x806C0000 0x3600 0x20 " \
442 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
443 "&& fsl_mc lazyapply dpl 0x80001000;" \
444 "run distro_bootcmd;run sd_bootcmd;" \
445 "env exists secureboot && esbc_halt;"
447 #if defined(CONFIG_QSPI_BOOT)
448 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
449 #define CONFIG_BOOTCOMMAND \
450 "sf read 0x80001000 0xd00000 0x100000;" \
451 "env exists mcinitcmd && env exists secureboot " \
452 " && sf read 0x806C0000 0x6C0000 0x100000 " \
453 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
454 "&& fsl_mc lazyapply dpl 0x80001000;" \
455 "run distro_bootcmd;run qspi_bootcmd;" \
456 "env exists secureboot && esbc_halt;"
458 /* Try to boot an on-SD kernel first, then do normal distro boot */
459 #elif defined(CONFIG_SD_BOOT)
460 #define CONFIG_BOOTCOMMAND \
461 "env exists mcinitcmd && mmcinfo; " \
462 "mmc read 0x80001000 0x6800 0x800; " \
463 "env exists mcinitcmd && env exists secureboot " \
464 " && mmc read 0x806C0000 0x3600 0x20 " \
465 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
466 "&& fsl_mc lazyapply dpl 0x80001000;" \
467 "run distro_bootcmd;run sd_bootcmd;" \
468 "env exists secureboot && esbc_halt;"
470 #endif /* CONFIG_TFABOOT */
472 /* MAC/PHY configuration */
473 #ifdef CONFIG_FSL_MC_ENET
474 #define AQ_PHY_ADDR1 0x00
475 #define AQR105_IRQ_MASK 0x00000004
477 #define QSGMII1_PORT1_PHY_ADDR 0x0c
478 #define QSGMII1_PORT2_PHY_ADDR 0x0d
479 #define QSGMII1_PORT3_PHY_ADDR 0x0e
480 #define QSGMII1_PORT4_PHY_ADDR 0x0f
481 #define QSGMII2_PORT1_PHY_ADDR 0x1c
482 #define QSGMII2_PORT2_PHY_ADDR 0x1d
483 #define QSGMII2_PORT3_PHY_ADDR 0x1e
484 #define QSGMII2_PORT4_PHY_ADDR 0x1f
486 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
487 #define CONFIG_PHY_GIGE
493 #define BOOT_TARGET_DEVICES(func) \
496 func(SCSI, scsi, 0) \
498 #include <config_distro_bootcmd.h>
501 #include <asm/fsl_secure_boot.h>
503 #endif /* __LS1088A_RDB_H */