d0066e3551fdbb4ae837bb33d2a4eb4b5657295c
[platform/kernel/u-boot.git] / include / configs / ls1088ardb.h
1 /*
2  * Copyright 2017 NXP
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __LS1088A_RDB_H
8 #define __LS1088A_RDB_H
9
10 #include "ls1088a_common.h"
11
12 #ifndef SPL_NO_BOARDINFO
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
14 #endif
15
16 #define CONFIG_MISC_INIT_R
17
18 #if defined(CONFIG_QSPI_BOOT)
19 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
20 #define CONFIG_ENV_SECT_SIZE            0x40000
21 #elif defined(CONFIG_SD_BOOT)
22 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
23 #define CONFIG_SYS_MMC_ENV_DEV          0
24 #define CONFIG_ENV_SIZE                 0x2000
25 #else
26 #define CONFIG_ENV_IS_IN_FLASH
27 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
28 #define CONFIG_ENV_SECT_SIZE            0x20000
29 #define CONFIG_ENV_SIZE                 0x20000
30 #endif
31
32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
33 #ifndef CONFIG_SPL_BUILD
34 #define CONFIG_QIXIS_I2C_ACCESS
35 #endif
36 #define SYS_NO_FLASH
37 #undef CONFIG_CMD_IMLS
38 #endif
39
40 #define CONFIG_SYS_CLK_FREQ             100000000
41 #define CONFIG_DDR_CLK_FREQ             100000000
42 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
43 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
44
45 #define CONFIG_DDR_SPD
46 #ifdef CONFIG_EMU
47 #define CONFIG_SYS_FSL_DDR_EMU
48 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
49 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
50 #else
51 #define CONFIG_DDR_ECC
52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
53 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
54 #endif
55 #define SPD_EEPROM_ADDRESS      0x51
56 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
57 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
58
59
60 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
61 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
62 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
63 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
64
65 #define CONFIG_SYS_NOR0_CSPR                                    \
66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
67         CSPR_PORT_SIZE_16                                       | \
68         CSPR_MSEL_NOR                                           | \
69         CSPR_V)
70 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
71         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
72         CSPR_PORT_SIZE_16                                       | \
73         CSPR_MSEL_NOR                                           | \
74         CSPR_V)
75 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
76 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
77                                 FTIM0_NOR_TEADC(0x1) | \
78                                 FTIM0_NOR_TEAHC(0x1))
79 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
80                                 FTIM1_NOR_TRAD_NOR(0x1))
81 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
82                                 FTIM2_NOR_TCH(0x0) | \
83                                 FTIM2_NOR_TWP(0x1))
84 #define CONFIG_SYS_NOR_FTIM3    0x04000000
85 #define CONFIG_SYS_IFC_CCR      0x01000000
86
87 #ifndef SYS_NO_FLASH
88 #define CONFIG_FLASH_CFI_DRIVER
89 #define CONFIG_SYS_FLASH_CFI
90 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
91 #define CONFIG_SYS_FLASH_QUIET_TEST
92 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
93
94 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
95 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
96 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
97 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
98
99 #define CONFIG_SYS_FLASH_EMPTY_INFO
100 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
101 #endif
102 #endif
103
104 #ifndef SPL_NO_IFC
105 #define CONFIG_NAND_FSL_IFC
106 #endif
107
108 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
109 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
110
111 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
112 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
113                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
114                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
115                                 | CSPR_V)
116 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
117
118 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
119                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
120                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
121                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
122                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
123                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
124                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
125
126 #define CONFIG_SYS_NAND_ONFI_DETECTION
127
128 /* ONFI NAND Flash mode0 Timing Params */
129 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
130                                         FTIM0_NAND_TWP(0x18)   | \
131                                         FTIM0_NAND_TWCHT(0x07) | \
132                                         FTIM0_NAND_TWH(0x0a))
133 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
134                                         FTIM1_NAND_TWBE(0x39)  | \
135                                         FTIM1_NAND_TRR(0x0e)   | \
136                                         FTIM1_NAND_TRP(0x18))
137 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
138                                         FTIM2_NAND_TREH(0x0a) | \
139                                         FTIM2_NAND_TWHRE(0x1e))
140 #define CONFIG_SYS_NAND_FTIM3           0x0
141
142 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
143 #define CONFIG_SYS_MAX_NAND_DEVICE      1
144 #define CONFIG_MTD_NAND_VERIFY_WRITE
145 #define CONFIG_CMD_NAND
146
147 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
148
149 #ifndef SPL_NO_QIXIS
150 #define CONFIG_FSL_QIXIS
151 #endif
152
153 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
154 #define QIXIS_LBMAP_SWITCH              2
155 #define QIXIS_QMAP_MASK                 0xe0
156 #define QIXIS_QMAP_SHIFT                5
157 #define QIXIS_LBMAP_MASK                0x1f
158 #define QIXIS_LBMAP_SHIFT               5
159 #define QIXIS_LBMAP_DFLTBANK            0x00
160 #define QIXIS_LBMAP_ALTBANK             0x20
161 #define QIXIS_LBMAP_SD                  0x00
162 #define QIXIS_LBMAP_SD_QSPI             0x00
163 #define QIXIS_LBMAP_QSPI                0x00
164 #define QIXIS_RCW_SRC_SD                0x40
165 #define QIXIS_RCW_SRC_QSPI              0x62
166 #define QIXIS_RST_CTL_RESET             0x31
167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
168 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
170 #define QIXIS_RST_FORCE_MEM             0x01
171
172 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
173 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
174                                         | CSPR_PORT_SIZE_8 \
175                                         | CSPR_MSEL_GPCM \
176                                         | CSPR_V)
177 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
178                                         | CSPR_PORT_SIZE_8 \
179                                         | CSPR_MSEL_GPCM \
180                                         | CSPR_V)
181
182 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
183 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
184 /* QIXIS Timing parameters*/
185 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
186                                         FTIM0_GPCM_TEADC(0x0e) | \
187                                         FTIM0_GPCM_TEAHC(0x0e))
188 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
189                                         FTIM1_GPCM_TRAD(0x3f))
190 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
191                                         FTIM2_GPCM_TCH(0xf) | \
192                                         FTIM2_GPCM_TWP(0x3E))
193 #define SYS_FPGA_CS_FTIM3       0x0
194
195 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
196 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
197 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
198 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
199 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
200 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
201 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
202 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
203 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
204 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
205 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
206 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
207 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
208 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
209 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
210 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
211 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
212 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
213 #else
214 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
215 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
216 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
217 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
218 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
219 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
220 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
221 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
222 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
223 #endif
224
225
226 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
227
228 /*
229  * I2C bus multiplexer
230  */
231 #define I2C_MUX_PCA_ADDR_PRI            0x77
232 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
233 #define I2C_RETIMER_ADDR                0x18
234 #define I2C_MUX_CH_DEFAULT              0x8
235 #define I2C_MUX_CH5                     0xD
236
237 #ifndef SPL_NO_RTC
238 /*
239 * RTC configuration
240 */
241 #define RTC
242 #define CONFIG_RTC_PCF8563 1
243 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
244 #define CONFIG_CMD_DATE
245 #endif
246
247 /* EEPROM */
248 #define CONFIG_ID_EEPROM
249 #define CONFIG_SYS_I2C_EEPROM_NXID
250 #define CONFIG_SYS_EEPROM_BUS_NUM               0
251 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
252 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
255
256 #ifndef SPL_NO_QSPI
257 /* QSPI device */
258 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
259 #define CONFIG_FSL_QSPI
260 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
261 #define FSL_QSPI_FLASH_NUM              2
262 #endif
263 #endif
264
265 #define CONFIG_CMD_MEMINFO
266 #define CONFIG_CMD_MEMTEST
267 #define CONFIG_SYS_MEMTEST_START        0x80000000
268 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
269
270 #ifdef CONFIG_SPL_BUILD
271 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
272 #else
273 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
274 #endif
275
276 #define CONFIG_FSL_MEMAC
277
278 #ifndef SPL_NO_ENV
279 /* Initial environment variables */
280 #if defined(CONFIG_QSPI_BOOT)
281 #define MC_INIT_CMD                             \
282         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
283         "sf read 0x80100000 0xE00000 0x100000;"                         \
284         "env exists secureboot && "                     \
285         "sf read 0x80700000 0x700000 0x40000 && "       \
286         "sf read 0x80740000 0x740000 0x40000 && "       \
287         "esbc_validate 0x80700000 && "                  \
288         "esbc_validate 0x80740000 ;"                    \
289         "fsl_mc start mc 0x80000000 0x80100000\0"       \
290         "mcmemsize=0x70000000\0"
291 #elif defined(CONFIG_SD_BOOT)
292 #define MC_INIT_CMD                             \
293         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"           \
294         "mmc read 0x80100000 0x7000 0x800;"                             \
295         "env exists secureboot && "                     \
296         "mmc read 0x80700000 0x3800 0x10 && "           \
297         "mmc read 0x80740000 0x3A00 0x10 && "           \
298         "esbc_validate 0x80700000 && "                  \
299         "esbc_validate 0x80740000 ;"                    \
300         "fsl_mc start mc 0x80000000 0x80100000\0"       \
301         "mcmemsize=0x70000000\0"
302 #endif
303
304 #undef CONFIG_EXTRA_ENV_SETTINGS
305 #define CONFIG_EXTRA_ENV_SETTINGS               \
306         "BOARD=ls1088ardb\0"                    \
307         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
308         "ramdisk_addr=0x800000\0"               \
309         "ramdisk_size=0x2000000\0"              \
310         "fdt_high=0xa0000000\0"                 \
311         "initrd_high=0xffffffffffffffff\0"      \
312         "fdt_addr=0x64f00000\0"                 \
313         "kernel_addr=0x1000000\0"               \
314         "kernel_addr_sd=0x8000\0"               \
315         "kernelhdr_addr_sd=0x4000\0"            \
316         "kernel_start=0x580100000\0"            \
317         "kernelheader_start=0x580800000\0"      \
318         "scriptaddr=0x80000000\0"               \
319         "scripthdraddr=0x80080000\0"            \
320         "fdtheader_addr_r=0x80100000\0"         \
321         "kernelheader_addr=0x800000\0"          \
322         "kernelheader_addr_r=0x80200000\0"      \
323         "kernel_addr_r=0x81000000\0"            \
324         "kernelheader_size=0x40000\0"           \
325         "fdt_addr_r=0x90000000\0"               \
326         "load_addr=0xa0000000\0"                \
327         "kernel_size=0x2800000\0"               \
328         "kernel_size_sd=0x14000\0"              \
329         "kernelhdr_size_sd=0x10\0"              \
330         MC_INIT_CMD                             \
331         BOOTENV                                 \
332         "boot_scripts=ls1088ardb_boot.scr\0"    \
333         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
334         "scan_dev_for_boot_part="               \
335                 "part list ${devtype} ${devnum} devplist; "     \
336                 "env exists devplist || setenv devplist 1; "    \
337                 "for distro_bootpart in ${devplist}; do "       \
338                         "if fstype ${devtype} "                 \
339                                 "${devnum}:${distro_bootpart} " \
340                                 "bootfstype; then "             \
341                                 "run scan_dev_for_boot; "       \
342                         "fi; "                                  \
343                 "done\0"                                        \
344         "scan_dev_for_boot="                                    \
345                 "echo Scanning ${devtype} "                     \
346                 "${devnum}:${distro_bootpart}...; "             \
347                 "for prefix in ${boot_prefixes}; do "           \
348                         "run scan_dev_for_scripts; "            \
349                 "done;\0"                                       \
350         "boot_a_script="                                        \
351                 "load ${devtype} ${devnum}:${distro_bootpart} " \
352                 "${scriptaddr} ${prefix}${script}; "            \
353         "env exists secureboot && load ${devtype} "             \
354                 "${devnum}:${distro_bootpart} "                 \
355                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
356                 "&& esbc_validate ${scripthdraddr};"            \
357                 "source ${scriptaddr}\0"                        \
358         "installer=load mmc 0:2 $load_addr "                    \
359                 "/flex_installer_arm64.itb; "                   \
360                 "env exists mcinitcmd && run mcinitcmd && "     \
361                 "mmc read 0x80200000 0x6800 0x800;"             \
362                 "fsl_mc apply dpl 0x80200000;"                  \
363                 "bootm $load_addr#ls1088ardb\0"                 \
364         "qspi_bootcmd=echo Trying load from qspi..;"            \
365                 "sf probe && sf read $load_addr "               \
366                 "$kernel_addr $kernel_size ; env exists secureboot "    \
367                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
368                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
369                 "bootm $load_addr#$BOARD\0"                     \
370                 "sd_bootcmd=echo Trying load from sd card..;"           \
371                 "mmcinfo; mmc read $load_addr "                 \
372                 "$kernel_addr_sd $kernel_size_sd ;"             \
373                 "env exists secureboot && mmc read $kernelheader_addr_r "\
374                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
375                 " && esbc_validate ${kernelheader_addr_r};"     \
376                 "bootm $load_addr#$BOARD\0"
377
378 #undef CONFIG_BOOTCOMMAND
379 #if defined(CONFIG_QSPI_BOOT)
380 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
381 #define CONFIG_BOOTCOMMAND                                      \
382                 "sf read 0x80200000 0xd00000 0x100000;"         \
383                 "env exists mcinitcmd && env exists secureboot "        \
384                 " && sf read 0x80780000 0x780000 0x100000 "     \
385                 "&& esbc_validate 0x80780000;env exists mcinitcmd "     \
386                 "&& fsl_mc apply dpl 0x80200000;"               \
387                 "run distro_bootcmd;run qspi_bootcmd;"          \
388                 "env exists secureboot && esbc_halt;"
389
390 /* Try to boot an on-SD kernel first, then do normal distro boot */
391 #elif defined(CONFIG_SD_BOOT)
392 #define CONFIG_BOOTCOMMAND                                      \
393                 "env exists mcinitcmd && mmcinfo; "             \
394                 "mmc read 0x80200000 0x6800 0x800; "            \
395                 "env exists mcinitcmd && env exists secureboot "        \
396                 " && mmc read 0x80780000 0x3800 0x10 "          \
397                 "&& esbc_validate 0x80780000;env exists mcinitcmd "     \
398                 "&& fsl_mc apply dpl 0x80200000;"               \
399                 "run distro_bootcmd;run sd_bootcmd;"            \
400                 "env exists secureboot && esbc_halt;"
401 #endif
402
403 /* MAC/PHY configuration */
404 #ifdef CONFIG_FSL_MC_ENET
405 #define CONFIG_PHYLIB_10G
406 #define CONFIG_PHY_GIGE
407 #define CONFIG_PHYLIB
408
409 #define CONFIG_PHY_VITESSE
410 #define CONFIG_PHY_AQUANTIA
411 #define AQ_PHY_ADDR1                    0x00
412 #define AQR105_IRQ_MASK                 0x00000004
413
414 #define QSGMII1_PORT1_PHY_ADDR          0x0c
415 #define QSGMII1_PORT2_PHY_ADDR          0x0d
416 #define QSGMII1_PORT3_PHY_ADDR          0x0e
417 #define QSGMII1_PORT4_PHY_ADDR          0x0f
418 #define QSGMII2_PORT1_PHY_ADDR          0x1c
419 #define QSGMII2_PORT2_PHY_ADDR          0x1d
420 #define QSGMII2_PORT3_PHY_ADDR          0x1e
421 #define QSGMII2_PORT4_PHY_ADDR          0x1f
422
423 #define CONFIG_MII
424 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
425 #define CONFIG_PHY_GIGE
426 #endif
427 #endif
428
429 /*  MMC  */
430 #ifdef CONFIG_MMC
431 #define CONFIG_FSL_ESDHC
432 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
433 #endif
434
435 #ifndef SPL_NO_ENV
436 #undef CONFIG_CMDLINE_EDITING
437 #include <config_distro_defaults.h>
438
439 #define BOOT_TARGET_DEVICES(func) \
440         func(MMC, mmc, 0) \
441         func(SCSI, scsi, 0) \
442         func(DHCP, dhcp, na)
443 #include <config_distro_bootcmd.h>
444 #endif
445
446 #include <asm/fsl_secure_boot.h>
447
448 #endif /* __LS1088A_RDB_H */