1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
16 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
19 #define CONFIG_SYS_FSL_DDR_EMU
21 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
23 #define SPD_EEPROM_ADDRESS 0x51
24 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
27 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
28 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
29 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
30 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
32 #define CONFIG_SYS_NOR0_CSPR \
33 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
37 #define CONFIG_SYS_NOR0_CSPR_EARLY \
38 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
42 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
43 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
44 FTIM0_NOR_TEADC(0x1) | \
46 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
47 FTIM1_NOR_TRAD_NOR(0x1))
48 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
49 FTIM2_NOR_TCH(0x0) | \
51 #define CONFIG_SYS_NOR_FTIM3 0x04000000
52 #define CONFIG_SYS_IFC_CCR 0x01000000
55 #define CONFIG_SYS_FLASH_QUIET_TEST
56 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
58 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
59 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
60 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
62 #define CONFIG_SYS_FLASH_EMPTY_INFO
63 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
67 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
68 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
70 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
71 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
72 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
73 | CSPR_MSEL_NAND /* MSEL = NAND */ \
75 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
77 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
78 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
79 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
80 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
81 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
82 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
83 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
85 /* ONFI NAND Flash mode0 Timing Params */
86 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
87 FTIM0_NAND_TWP(0x18) | \
88 FTIM0_NAND_TWCHT(0x07) | \
90 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
91 FTIM1_NAND_TWBE(0x39) | \
92 FTIM1_NAND_TRR(0x0e) | \
94 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
95 FTIM2_NAND_TREH(0x0a) | \
96 FTIM2_NAND_TWHRE(0x1e))
97 #define CONFIG_SYS_NAND_FTIM3 0x0
99 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
100 #define CONFIG_SYS_MAX_NAND_DEVICE 1
101 #define CONFIG_MTD_NAND_VERIFY_WRITE
103 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
104 #define QIXIS_BRDCFG4_OFFSET 0x54
105 #define QIXIS_LBMAP_SWITCH 2
106 #define QIXIS_QMAP_MASK 0xe0
107 #define QIXIS_QMAP_SHIFT 5
108 #define QIXIS_LBMAP_MASK 0x1f
109 #define QIXIS_LBMAP_SHIFT 5
110 #define QIXIS_LBMAP_DFLTBANK 0x00
111 #define QIXIS_LBMAP_ALTBANK 0x20
112 #define QIXIS_LBMAP_SD 0x00
113 #define QIXIS_LBMAP_EMMC 0x00
114 #define QIXIS_LBMAP_SD_QSPI 0x00
115 #define QIXIS_LBMAP_QSPI 0x00
116 #define QIXIS_RCW_SRC_SD 0x40
117 #define QIXIS_RCW_SRC_EMMC 0x41
118 #define QIXIS_RCW_SRC_QSPI 0x62
119 #define QIXIS_RST_CTL_RESET 0x31
120 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
121 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
122 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
123 #define QIXIS_RST_FORCE_MEM 0x01
125 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
126 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
130 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
135 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
136 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
137 /* QIXIS Timing parameters*/
138 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
139 FTIM0_GPCM_TEADC(0x0e) | \
140 FTIM0_GPCM_TEAHC(0x0e))
141 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
142 FTIM1_GPCM_TRAD(0x3f))
143 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
144 FTIM2_GPCM_TCH(0xf) | \
145 FTIM2_GPCM_TWP(0x3E))
146 #define SYS_FPGA_CS_FTIM3 0x0
148 #if defined(CONFIG_TFABOOT) || \
149 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
150 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
151 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
152 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
153 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
154 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
155 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
156 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
157 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
158 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
159 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
160 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
161 #define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
162 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
163 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
164 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
165 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
166 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
168 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
169 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
170 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
171 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
172 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
173 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
174 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
175 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
176 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
179 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
181 #define I2C_MUX_CH_VOL_MONITOR 0xA
182 /* Voltage monitor on channel 2*/
183 #define I2C_VOL_MONITOR_ADDR 0x63
184 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
185 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
186 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
187 #define I2C_SVDD_MONITOR_ADDR 0x4F
189 /* The lowest and highest voltage allowed for LS1088ARDB */
190 #define VDD_MV_MIN 819
191 #define VDD_MV_MAX 1212
193 #define PWM_CHANNEL0 0x0
196 * I2C bus multiplexer
198 #define I2C_MUX_PCA_ADDR_PRI 0x77
199 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
200 #define I2C_RETIMER_ADDR 0x18
201 #define I2C_MUX_CH_DEFAULT 0x8
202 #define I2C_MUX_CH5 0xD
209 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
213 #define CONFIG_SYS_I2C_EEPROM_NXID
214 #define CONFIG_SYS_EEPROM_BUS_NUM 0
216 #define CONFIG_FSL_MEMAC
219 /* Initial environment variables */
220 #ifdef CONFIG_TFABOOT
221 #define QSPI_MC_INIT_CMD \
222 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
223 "sf read 0x80e00000 0xE00000 0x100000;" \
224 "env exists secureboot && " \
225 "sf read 0x80640000 0x640000 0x40000 && " \
226 "sf read 0x80680000 0x680000 0x40000 && " \
227 "esbc_validate 0x80640000 && " \
228 "esbc_validate 0x80680000 ;" \
229 "fsl_mc start mc 0x80a00000 0x80e00000\0"
230 #define SD_MC_INIT_CMD \
231 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
232 "mmc read 0x80e00000 0x7000 0x800;" \
233 "env exists secureboot && " \
234 "mmc read 0x80640000 0x3200 0x20 && " \
235 "mmc read 0x80680000 0x3400 0x20 && " \
236 "esbc_validate 0x80640000 && " \
237 "esbc_validate 0x80680000 ;" \
238 "fsl_mc start mc 0x80a00000 0x80e00000\0"
240 #if defined(CONFIG_QSPI_BOOT)
241 #define MC_INIT_CMD \
242 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
243 "sf read 0x80e00000 0xE00000 0x100000;" \
244 "env exists secureboot && " \
245 "sf read 0x80640000 0x640000 0x40000 && " \
246 "sf read 0x80680000 0x680000 0x40000 && " \
247 "esbc_validate 0x80640000 && " \
248 "esbc_validate 0x80680000 ;" \
249 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
250 "mcmemsize=0x70000000\0"
251 #elif defined(CONFIG_SD_BOOT)
252 #define MC_INIT_CMD \
253 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
254 "mmc read 0x80e00000 0x7000 0x800;" \
255 "env exists secureboot && " \
256 "mmc read 0x80640000 0x3200 0x20 && " \
257 "mmc read 0x80680000 0x3400 0x20 && " \
258 "esbc_validate 0x80640000 && " \
259 "esbc_validate 0x80680000 ;" \
260 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
261 "mcmemsize=0x70000000\0"
263 #endif /* CONFIG_TFABOOT */
265 #undef CONFIG_EXTRA_ENV_SETTINGS
266 #ifdef CONFIG_TFABOOT
267 #define CONFIG_EXTRA_ENV_SETTINGS \
268 "BOARD=ls1088ardb\0" \
269 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
270 "ramdisk_addr=0x800000\0" \
271 "ramdisk_size=0x2000000\0" \
272 "fdt_high=0xa0000000\0" \
273 "initrd_high=0xffffffffffffffff\0" \
274 "kernel_addr=0x1000000\0" \
275 "kernel_addr_sd=0x8000\0" \
276 "kernelhdr_addr_sd=0x3000\0" \
277 "kernel_start=0x580100000\0" \
278 "kernelheader_start=0x580600000\0" \
279 "scriptaddr=0x80000000\0" \
280 "scripthdraddr=0x80080000\0" \
281 "fdtheader_addr_r=0x80100000\0" \
282 "kernelheader_addr=0x600000\0" \
283 "kernelheader_addr_r=0x80200000\0" \
284 "kernel_addr_r=0x81000000\0" \
285 "kernelheader_size=0x40000\0" \
286 "fdt_addr_r=0x90000000\0" \
287 "load_addr=0xa0000000\0" \
288 "kernel_size=0x2800000\0" \
289 "kernel_size_sd=0x14000\0" \
290 "kernelhdr_size_sd=0x20\0" \
292 "mcmemsize=0x70000000\0" \
294 "boot_scripts=ls1088ardb_boot.scr\0" \
295 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
296 "scan_dev_for_boot_part=" \
297 "part list ${devtype} ${devnum} devplist; " \
298 "env exists devplist || setenv devplist 1; " \
299 "for distro_bootpart in ${devplist}; do " \
300 "if fstype ${devtype} " \
301 "${devnum}:${distro_bootpart} " \
302 "bootfstype; then " \
303 "run scan_dev_for_boot; " \
307 "load ${devtype} ${devnum}:${distro_bootpart} " \
308 "${scriptaddr} ${prefix}${script}; " \
309 "env exists secureboot && load ${devtype} " \
310 "${devnum}:${distro_bootpart} " \
311 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
312 "env exists secureboot " \
313 "&& esbc_validate ${scripthdraddr};" \
314 "source ${scriptaddr}\0" \
315 "installer=load mmc 0:2 $load_addr " \
316 "/flex_installer_arm64.itb; " \
317 "env exists mcinitcmd && run mcinitcmd && " \
318 "mmc read 0x80001000 0x6800 0x800;" \
319 "fsl_mc lazyapply dpl 0x80001000;" \
320 "bootm $load_addr#ls1088ardb\0" \
321 "qspi_bootcmd=echo Trying load from qspi..;" \
322 "sf probe && sf read $load_addr " \
323 "$kernel_addr $kernel_size ; env exists secureboot " \
324 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
325 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
326 "bootm $load_addr#$BOARD\0" \
327 "sd_bootcmd=echo Trying load from sd card..;" \
328 "mmcinfo; mmc read $load_addr " \
329 "$kernel_addr_sd $kernel_size_sd ;" \
330 "env exists secureboot && mmc read $kernelheader_addr_r "\
331 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
332 " && esbc_validate ${kernelheader_addr_r};" \
333 "bootm $load_addr#$BOARD\0"
335 #define CONFIG_EXTRA_ENV_SETTINGS \
336 "BOARD=ls1088ardb\0" \
337 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
338 "ramdisk_addr=0x800000\0" \
339 "ramdisk_size=0x2000000\0" \
340 "fdt_high=0xa0000000\0" \
341 "initrd_high=0xffffffffffffffff\0" \
342 "kernel_addr=0x1000000\0" \
343 "kernel_addr_sd=0x8000\0" \
344 "kernelhdr_addr_sd=0x3000\0" \
345 "kernel_start=0x580100000\0" \
346 "kernelheader_start=0x580800000\0" \
347 "scriptaddr=0x80000000\0" \
348 "scripthdraddr=0x80080000\0" \
349 "fdtheader_addr_r=0x80100000\0" \
350 "kernelheader_addr=0x600000\0" \
351 "kernelheader_addr_r=0x80200000\0" \
352 "kernel_addr_r=0x81000000\0" \
353 "kernelheader_size=0x40000\0" \
354 "fdt_addr_r=0x90000000\0" \
355 "load_addr=0xa0000000\0" \
356 "kernel_size=0x2800000\0" \
357 "kernel_size_sd=0x14000\0" \
358 "kernelhdr_size_sd=0x20\0" \
361 "boot_scripts=ls1088ardb_boot.scr\0" \
362 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
363 "scan_dev_for_boot_part=" \
364 "part list ${devtype} ${devnum} devplist; " \
365 "env exists devplist || setenv devplist 1; " \
366 "for distro_bootpart in ${devplist}; do " \
367 "if fstype ${devtype} " \
368 "${devnum}:${distro_bootpart} " \
369 "bootfstype; then " \
370 "run scan_dev_for_boot; " \
374 "load ${devtype} ${devnum}:${distro_bootpart} " \
375 "${scriptaddr} ${prefix}${script}; " \
376 "env exists secureboot && load ${devtype} " \
377 "${devnum}:${distro_bootpart} " \
378 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
379 "&& esbc_validate ${scripthdraddr};" \
380 "source ${scriptaddr}\0" \
381 "installer=load mmc 0:2 $load_addr " \
382 "/flex_installer_arm64.itb; " \
383 "env exists mcinitcmd && run mcinitcmd && " \
384 "mmc read 0x80001000 0x6800 0x800;" \
385 "fsl_mc lazyapply dpl 0x80001000;" \
386 "bootm $load_addr#ls1088ardb\0" \
387 "qspi_bootcmd=echo Trying load from qspi..;" \
388 "sf probe && sf read $load_addr " \
389 "$kernel_addr $kernel_size ; env exists secureboot " \
390 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
391 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
392 "bootm $load_addr#$BOARD\0" \
393 "sd_bootcmd=echo Trying load from sd card..;" \
394 "mmcinfo; mmc read $load_addr " \
395 "$kernel_addr_sd $kernel_size_sd ;" \
396 "env exists secureboot && mmc read $kernelheader_addr_r "\
397 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
398 " && esbc_validate ${kernelheader_addr_r};" \
399 "bootm $load_addr#$BOARD\0"
400 #endif /* CONFIG_TFABOOT */
402 #ifdef CONFIG_TFABOOT
403 #define QSPI_NOR_BOOTCOMMAND \
404 "sf read 0x80001000 0xd00000 0x100000;" \
405 "env exists mcinitcmd && env exists secureboot " \
406 " && sf read 0x806C0000 0x6C0000 0x100000 " \
407 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
408 "&& fsl_mc lazyapply dpl 0x80001000;" \
409 "run distro_bootcmd;run qspi_bootcmd;" \
410 "env exists secureboot && esbc_halt;"
411 #define SD_BOOTCOMMAND \
412 "env exists mcinitcmd && mmcinfo; " \
413 "mmc read 0x80001000 0x6800 0x800; " \
414 "env exists mcinitcmd && env exists secureboot " \
415 " && mmc read 0x806C0000 0x3600 0x20 " \
416 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
417 "&& fsl_mc lazyapply dpl 0x80001000;" \
418 "run distro_bootcmd;run sd_bootcmd;" \
419 "env exists secureboot && esbc_halt;"
421 #if defined(CONFIG_QSPI_BOOT)
422 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
424 /* Try to boot an on-SD kernel first, then do normal distro boot */
426 #endif /* CONFIG_TFABOOT */
428 /* MAC/PHY configuration */
429 #ifdef CONFIG_FSL_MC_ENET
430 #define AQ_PHY_ADDR1 0x00
431 #define AQR105_IRQ_MASK 0x00000004
433 #define QSGMII1_PORT1_PHY_ADDR 0x0c
434 #define QSGMII1_PORT2_PHY_ADDR 0x0d
435 #define QSGMII1_PORT3_PHY_ADDR 0x0e
436 #define QSGMII1_PORT4_PHY_ADDR 0x0f
437 #define QSGMII2_PORT1_PHY_ADDR 0x1c
438 #define QSGMII2_PORT2_PHY_ADDR 0x1d
439 #define QSGMII2_PORT3_PHY_ADDR 0x1e
440 #define QSGMII2_PORT4_PHY_ADDR 0x1f
446 #define BOOT_TARGET_DEVICES(func) \
449 func(SCSI, scsi, 0) \
451 #include <config_distro_bootcmd.h>
454 #include <asm/fsl_secure_boot.h>
456 #endif /* __LS1088A_RDB_H */