include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #define SYS_NO_FLASH
  14 #endif
  15
  16 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  17
  18 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  19 #define SPD_EEPROM_ADDRESS      0x51
  20
  21
  22 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  23 #define CFG_SYS_NOR0_CSPR_EXT   (0x0)
  24 #define CFG_SYS_NOR_AMASK               IFC_AMASK(128 * 1024 * 1024)
  25 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
  26
  27 #define CFG_SYS_NOR0_CSPR                                       \
  28         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS)                | \
  29         CSPR_PORT_SIZE_16                                       | \
  30         CSPR_MSEL_NOR                                           | \
  31         CSPR_V)
  32 #define CFG_SYS_NOR0_CSPR_EARLY                         \
  33         (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY)  | \
  34         CSPR_PORT_SIZE_16                                       | \
  35         CSPR_MSEL_NOR                                           | \
  36         CSPR_V)
  37 #define CFG_SYS_NOR_CSOR        CSOR_NOR_ADM_SHIFT(6)
  38 #define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x1) | \
  39                                 FTIM0_NOR_TEADC(0x1) | \
  40                                 FTIM0_NOR_TEAHC(0x1))
  41 #define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x1) | \
  42                                 FTIM1_NOR_TRAD_NOR(0x1))
  43 #define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x0) | \
  44                                 FTIM2_NOR_TCH(0x0) | \
  45                                 FTIM2_NOR_TWP(0x1))
  46 #define CFG_SYS_NOR_FTIM3       0x04000000
  47 #define CFG_SYS_IFC_CCR 0x01000000
  48
  49 #ifndef SYS_NO_FLASH
  50 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  51
  52 #define CFG_SYS_FLASH_BANKS_LIST        { CFG_SYS_FLASH_BASE }
  53 #endif
  54 #endif
  55
  56 #define CFG_SYS_NAND_CSPR_EXT   (0x0)
  57 #define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
  58                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  59                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  60                                 | CSPR_V)
  61 #define CFG_SYS_NAND_AMASK      IFC_AMASK(64 * 1024)
  62
  63 #define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  64                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  65                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  66                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  67                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  68                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  69                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  70
  71 /* ONFI NAND Flash mode0 Timing Params */
  72 #define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
  73                                         FTIM0_NAND_TWP(0x18)   | \
  74                                         FTIM0_NAND_TWCHT(0x07) | \
  75                                         FTIM0_NAND_TWH(0x0a))
  76 #define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
  77                                         FTIM1_NAND_TWBE(0x39)  | \
  78                                         FTIM1_NAND_TRR(0x0e)   | \
  79                                         FTIM1_NAND_TRP(0x18))
  80 #define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
  81                                         FTIM2_NAND_TREH(0x0a) | \
  82                                         FTIM2_NAND_TWHRE(0x1e))
  83 #define CFG_SYS_NAND_FTIM3              0x0
  84
  85 #define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
  86 #define CONFIG_MTD_NAND_VERIFY_WRITE
  87
  88 #define CFG_SYS_I2C_FPGA_ADDR   0x66
  89 #define QIXIS_BRDCFG4_OFFSET            0x54
  90 #define QIXIS_LBMAP_SWITCH              2
  91 #define QIXIS_QMAP_MASK                 0xe0
  92 #define QIXIS_QMAP_SHIFT                5
  93 #define QIXIS_LBMAP_MASK                0x1f
  94 #define QIXIS_LBMAP_SHIFT               5
  95 #define QIXIS_LBMAP_DFLTBANK            0x00
  96 #define QIXIS_LBMAP_ALTBANK             0x20
  97 #define QIXIS_LBMAP_SD                  0x00
  98 #define QIXIS_LBMAP_EMMC                0x00
  99 #define QIXIS_LBMAP_SD_QSPI             0x00
 100 #define QIXIS_LBMAP_QSPI                0x00
 101 #define QIXIS_RCW_SRC_SD                0x40
 102 #define QIXIS_RCW_SRC_EMMC              0x41
 103 #define QIXIS_RCW_SRC_QSPI              0x62
 104 #define QIXIS_RST_CTL_RESET             0x31
 105 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 106 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 107 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 108 #define QIXIS_RST_FORCE_MEM             0x01
 109
 110 #define CFG_SYS_FPGA_CSPR_EXT   (0x0)
 111 #define CFG_SYS_FPGA_CSPR               (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 112                                         | CSPR_PORT_SIZE_8 \
 113                                         | CSPR_MSEL_GPCM \
 114                                         | CSPR_V)
 115 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 116                                         | CSPR_PORT_SIZE_8 \
 117                                         | CSPR_MSEL_GPCM \
 118                                         | CSPR_V)
 119
 120 #define CFG_SYS_FPGA_AMASK              IFC_AMASK(64*1024)
 121 #define CFG_SYS_FPGA_CSOR               CSOR_GPCM_ADM_SHIFT(0)
 122 /* QIXIS Timing parameters*/
 123 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 124                                         FTIM0_GPCM_TEADC(0x0e) | \
 125                                         FTIM0_GPCM_TEAHC(0x0e))
 126 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 127                                         FTIM1_GPCM_TRAD(0x3f))
 128 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 129                                         FTIM2_GPCM_TCH(0xf) | \
 130                                         FTIM2_GPCM_TWP(0x3E))
 131 #define SYS_FPGA_CS_FTIM3       0x0
 132
 133 #if defined(CONFIG_TFABOOT) || \
 134         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 135 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 136 #define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 137 #define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 138 #define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 139 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 140 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 141 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 142 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 143 #define CFG_SYS_CSPR2_EXT               CFG_SYS_FPGA_CSPR_EXT
 144 #define CFG_SYS_CSPR2           CFG_SYS_FPGA_CSPR
 145 #define CFG_SYS_CSPR2_FINAL             SYS_FPGA_CSPR_FINAL
 146 #define CFG_SYS_AMASK2          CFG_SYS_FPGA_AMASK
 147 #define CFG_SYS_CSOR2           CFG_SYS_FPGA_CSOR
 148 #define CFG_SYS_CS2_FTIM0               SYS_FPGA_CS_FTIM0
 149 #define CFG_SYS_CS2_FTIM1               SYS_FPGA_CS_FTIM1
 150 #define CFG_SYS_CS2_FTIM2               SYS_FPGA_CS_FTIM2
 151 #define CFG_SYS_CS2_FTIM3               SYS_FPGA_CS_FTIM3
 152 #else
 153 #define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 154 #define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR_EARLY
 155 #define CFG_SYS_CSPR0_FINAL             CFG_SYS_NOR0_CSPR
 156 #define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 157 #define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 158 #define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 159 #define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 160 #define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 161 #define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 162 #endif
 163
 164 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 165
 166 #define I2C_MUX_CH_VOL_MONITOR         0xA
 167 /* Voltage monitor on channel 2*/
 168 #define I2C_VOL_MONITOR_ADDR           0x63
 169 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 170 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 171 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 172 #define I2C_SVDD_MONITOR_ADDR           0x4F
 173
 174 /* The lowest and highest voltage allowed for LS1088ARDB */
 175 #define VDD_MV_MIN                      819
 176 #define VDD_MV_MAX                      1212
 177
 178 #define PWM_CHANNEL0                    0x0
 179
 180 /*
 181  * I2C bus multiplexer
 182  */
 183 #define I2C_MUX_PCA_ADDR_PRI            0x77
 184 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 185 #define I2C_RETIMER_ADDR                0x18
 186 #define I2C_MUX_CH_DEFAULT              0x8
 187 #define I2C_MUX_CH5                     0xD
 188
 189 /*
 190 * RTC configuration
 191 */
 192 #define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 193
 194 #ifndef SPL_NO_ENV
 195 /* Initial environment variables */
 196 #ifdef CONFIG_TFABOOT
 197 #define QSPI_MC_INIT_CMD                                \
 198         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 199         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 200         "env exists secureboot && "                     \
 201         "sf read 0x80640000 0x640000 0x40000 && "       \
 202         "sf read 0x80680000 0x680000 0x40000 && "       \
 203         "esbc_validate 0x80640000 && "                  \
 204         "esbc_validate 0x80680000 ;"                    \
 205         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 206 #define SD_MC_INIT_CMD                          \
 207         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 208         "mmc read 0x80e00000 0x7000 0x800;"                             \
 209         "env exists secureboot && "                     \
 210         "mmc read 0x80640000 0x3200 0x20 && "           \
 211         "mmc read 0x80680000 0x3400 0x20 && "           \
 212         "esbc_validate 0x80640000 && "                  \
 213         "esbc_validate 0x80680000 ;"                    \
 214         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 215 #else
 216 #if defined(CONFIG_QSPI_BOOT)
 217 #define MC_INIT_CMD                             \
 218         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 219         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 220         "env exists secureboot && "                     \
 221         "sf read 0x80640000 0x640000 0x40000 && "       \
 222         "sf read 0x80680000 0x680000 0x40000 && "       \
 223         "esbc_validate 0x80640000 && "                  \
 224         "esbc_validate 0x80680000 ;"                    \
 225         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 226         "mcmemsize=0x70000000\0"
 227 #elif defined(CONFIG_SD_BOOT)
 228 #define MC_INIT_CMD                             \
 229         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 230         "mmc read 0x80e00000 0x7000 0x800;"                             \
 231         "env exists secureboot && "                     \
 232         "mmc read 0x80640000 0x3200 0x20 && "           \
 233         "mmc read 0x80680000 0x3400 0x20 && "           \
 234         "esbc_validate 0x80640000 && "                  \
 235         "esbc_validate 0x80680000 ;"                    \
 236         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 237         "mcmemsize=0x70000000\0"
 238 #endif
 239 #endif /* CONFIG_TFABOOT */
 240
 241 #undef CONFIG_EXTRA_ENV_SETTINGS
 242 #ifdef CONFIG_TFABOOT
 243 #define CONFIG_EXTRA_ENV_SETTINGS               \
 244         "BOARD=ls1088ardb\0"                    \
 245         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 246         "ramdisk_addr=0x800000\0"               \
 247         "ramdisk_size=0x2000000\0"              \
 248         "fdt_high=0xa0000000\0"                 \
 249         "initrd_high=0xffffffffffffffff\0"      \
 250         "kernel_addr=0x1000000\0"               \
 251         "kernel_addr_sd=0x8000\0"               \
 252         "kernelhdr_addr_sd=0x3000\0"            \
 253         "kernel_start=0x580100000\0"            \
 254         "kernelheader_start=0x580600000\0"      \
 255         "scriptaddr=0x80000000\0"               \
 256         "scripthdraddr=0x80080000\0"            \
 257         "fdtheader_addr_r=0x80100000\0"         \
 258         "kernelheader_addr=0x600000\0"          \
 259         "kernelheader_addr_r=0x80200000\0"      \
 260         "kernel_addr_r=0x81000000\0"            \
 261         "kernelheader_size=0x40000\0"           \
 262         "fdt_addr_r=0x90000000\0"               \
 263         "load_addr=0xa0000000\0"                \
 264         "kernel_size=0x2800000\0"               \
 265         "kernel_size_sd=0x14000\0"              \
 266         "kernelhdr_size_sd=0x20\0"              \
 267         QSPI_MC_INIT_CMD                        \
 268         "mcmemsize=0x70000000\0"                \
 269         BOOTENV                                 \
 270         "boot_scripts=ls1088ardb_boot.scr\0"    \
 271         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 272         "scan_dev_for_boot_part="               \
 273                 "part list ${devtype} ${devnum} devplist; "     \
 274                 "env exists devplist || setenv devplist 1; "    \
 275                 "for distro_bootpart in ${devplist}; do "       \
 276                         "if fstype ${devtype} "                 \
 277                                 "${devnum}:${distro_bootpart} " \
 278                                 "bootfstype; then "             \
 279                                 "run scan_dev_for_boot; "       \
 280                         "fi; "                                  \
 281                 "done\0"                                        \
 282         "boot_a_script="                                        \
 283                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 284                 "${scriptaddr} ${prefix}${script}; "            \
 285         "env exists secureboot && load ${devtype} "             \
 286                 "${devnum}:${distro_bootpart} "                 \
 287                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 288                 "env exists secureboot "                        \
 289                 "&& esbc_validate ${scripthdraddr};"            \
 290                 "source ${scriptaddr}\0"                        \
 291         "installer=load mmc 0:2 $load_addr "                    \
 292                 "/flex_installer_arm64.itb; "                   \
 293                 "env exists mcinitcmd && run mcinitcmd && "     \
 294                 "mmc read 0x80001000 0x6800 0x800;"             \
 295                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 296                 "bootm $load_addr#ls1088ardb\0"                 \
 297         "qspi_bootcmd=echo Trying load from qspi..;"            \
 298                 "sf probe && sf read $load_addr "               \
 299                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 300                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 301                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 302                 "bootm $load_addr#$BOARD\0"                     \
 303                 "sd_bootcmd=echo Trying load from sd card..;"           \
 304                 "mmcinfo; mmc read $load_addr "                 \
 305                 "$kernel_addr_sd $kernel_size_sd ;"             \
 306                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 307                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 308                 " && esbc_validate ${kernelheader_addr_r};"     \
 309                 "bootm $load_addr#$BOARD\0"
 310 #else
 311 #define CONFIG_EXTRA_ENV_SETTINGS               \
 312         "BOARD=ls1088ardb\0"                    \
 313         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 314         "ramdisk_addr=0x800000\0"               \
 315         "ramdisk_size=0x2000000\0"              \
 316         "fdt_high=0xa0000000\0"                 \
 317         "initrd_high=0xffffffffffffffff\0"      \
 318         "kernel_addr=0x1000000\0"               \
 319         "kernel_addr_sd=0x8000\0"               \
 320         "kernelhdr_addr_sd=0x3000\0"            \
 321         "kernel_start=0x580100000\0"            \
 322         "kernelheader_start=0x580800000\0"      \
 323         "scriptaddr=0x80000000\0"               \
 324         "scripthdraddr=0x80080000\0"            \
 325         "fdtheader_addr_r=0x80100000\0"         \
 326         "kernelheader_addr=0x600000\0"          \
 327         "kernelheader_addr_r=0x80200000\0"      \
 328         "kernel_addr_r=0x81000000\0"            \
 329         "kernelheader_size=0x40000\0"           \
 330         "fdt_addr_r=0x90000000\0"               \
 331         "load_addr=0xa0000000\0"                \
 332         "kernel_size=0x2800000\0"               \
 333         "kernel_size_sd=0x14000\0"              \
 334         "kernelhdr_size_sd=0x20\0"              \
 335         MC_INIT_CMD                             \
 336         BOOTENV                                 \
 337         "boot_scripts=ls1088ardb_boot.scr\0"    \
 338         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 339         "scan_dev_for_boot_part="               \
 340                 "part list ${devtype} ${devnum} devplist; "     \
 341                 "env exists devplist || setenv devplist 1; "    \
 342                 "for distro_bootpart in ${devplist}; do "       \
 343                         "if fstype ${devtype} "                 \
 344                                 "${devnum}:${distro_bootpart} " \
 345                                 "bootfstype; then "             \
 346                                 "run scan_dev_for_boot; "       \
 347                         "fi; "                                  \
 348                 "done\0"                                        \
 349         "boot_a_script="                                        \
 350                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 351                 "${scriptaddr} ${prefix}${script}; "            \
 352         "env exists secureboot && load ${devtype} "             \
 353                 "${devnum}:${distro_bootpart} "                 \
 354                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 355                 "&& esbc_validate ${scripthdraddr};"            \
 356                 "source ${scriptaddr}\0"                        \
 357         "installer=load mmc 0:2 $load_addr "                    \
 358                 "/flex_installer_arm64.itb; "                   \
 359                 "env exists mcinitcmd && run mcinitcmd && "     \
 360                 "mmc read 0x80001000 0x6800 0x800;"             \
 361                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 362                 "bootm $load_addr#ls1088ardb\0"                 \
 363         "qspi_bootcmd=echo Trying load from qspi..;"            \
 364                 "sf probe && sf read $load_addr "               \
 365                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 366                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 367                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 368                 "bootm $load_addr#$BOARD\0"                     \
 369                 "sd_bootcmd=echo Trying load from sd card..;"           \
 370                 "mmcinfo; mmc read $load_addr "                 \
 371                 "$kernel_addr_sd $kernel_size_sd ;"             \
 372                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 373                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 374                 " && esbc_validate ${kernelheader_addr_r};"     \
 375                 "bootm $load_addr#$BOARD\0"
 376 #endif /* CONFIG_TFABOOT */
 377
 378 #ifdef CONFIG_TFABOOT
 379 #define QSPI_NOR_BOOTCOMMAND                                    \
 380         "sf read 0x80001000 0xd00000 0x100000;"         \
 381                 "env exists mcinitcmd && env exists secureboot "        \
 382                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 383                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 384                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 385                 "run distro_bootcmd;run qspi_bootcmd;"          \
 386                 "env exists secureboot && esbc_halt;"
 387 #define SD_BOOTCOMMAND                                          \
 388                 "env exists mcinitcmd && mmcinfo; "             \
 389                 "mmc read 0x80001000 0x6800 0x800; "            \
 390                 "env exists mcinitcmd && env exists secureboot "        \
 391                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 392                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 393                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 394                 "run distro_bootcmd;run sd_bootcmd;"            \
 395                 "env exists secureboot && esbc_halt;"
 396 #else
 397 #if defined(CONFIG_QSPI_BOOT)
 398 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 399
 400 /* Try to boot an on-SD kernel first, then do normal distro boot */
 401 #endif
 402 #endif /* CONFIG_TFABOOT */
 403
 404 /* MAC/PHY configuration */
 405 #ifdef CONFIG_FSL_MC_ENET
 406 #define AQ_PHY_ADDR1                    0x00
 407 #define AQR105_IRQ_MASK                 0x00000004
 408
 409 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 410 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 411 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 412 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 413 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 414 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 415 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 416 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 417 #endif
 418 #endif
 419
 420 #ifndef SPL_NO_ENV
 421
 422 #define BOOT_TARGET_DEVICES(func) \
 423         func(MMC, mmc, 0) \
 424         func(USB, usb, 0) \
 425         func(SCSI, scsi, 0) \
 426         func(DHCP, dhcp, na)
 427 #include <config_distro_bootcmd.h>
 428 #endif
 429
 430 #include <asm/fsl_secure_boot.h>
 431
 432 #endif /* __LS1088A_RDB_H */