include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #define CONFIG_SYS_MMC_ENV_DEV          0
  12
  13 #if defined(CONFIG_TFABOOT) || \
  14         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  15 #ifndef CONFIG_SPL_BUILD
  16 #define CONFIG_QIXIS_I2C_ACCESS
  17 #endif
  18 #define SYS_NO_FLASH
  19 #undef CONFIG_CMD_IMLS
  20 #endif
  21
  22 #define CONFIG_SYS_CLK_FREQ             100000000
  23 #define CONFIG_DDR_CLK_FREQ             100000000
  24 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  25 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  26
  27 #define CONFIG_DDR_SPD
  28 #ifdef CONFIG_EMU
  29 #define CONFIG_SYS_FSL_DDR_EMU
  30 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  31 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  32 #else
  33 #define CONFIG_DDR_ECC
  34 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  35 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  36 #endif
  37 #define SPD_EEPROM_ADDRESS      0x51
  38 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  39 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  40
  41
  42 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  43 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  44 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  45 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  46
  47 #define CONFIG_SYS_NOR0_CSPR                                    \
  48         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  49         CSPR_PORT_SIZE_16                                       | \
  50         CSPR_MSEL_NOR                                           | \
  51         CSPR_V)
  52 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  53         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  54         CSPR_PORT_SIZE_16                                       | \
  55         CSPR_MSEL_NOR                                           | \
  56         CSPR_V)
  57 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  58 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  59                                 FTIM0_NOR_TEADC(0x1) | \
  60                                 FTIM0_NOR_TEAHC(0x1))
  61 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  62                                 FTIM1_NOR_TRAD_NOR(0x1))
  63 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  64                                 FTIM2_NOR_TCH(0x0) | \
  65                                 FTIM2_NOR_TWP(0x1))
  66 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  67 #define CONFIG_SYS_IFC_CCR      0x01000000
  68
  69 #ifndef SYS_NO_FLASH
  70 #define CONFIG_SYS_FLASH_QUIET_TEST
  71 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  72
  73 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  74 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  75 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  76 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  77
  78 #define CONFIG_SYS_FLASH_EMPTY_INFO
  79 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  80 #endif
  81 #endif
  82
  83 #ifndef SPL_NO_IFC
  84 #define CONFIG_NAND_FSL_IFC
  85 #endif
  86
  87 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  88 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  89
  90 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  91 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  92                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  93                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  94                                 | CSPR_V)
  95 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  96
  97 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  98                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  99                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 100                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 101                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 102                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 103                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 104
 105 #define CONFIG_SYS_NAND_ONFI_DETECTION
 106
 107 /* ONFI NAND Flash mode0 Timing Params */
 108 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 109                                         FTIM0_NAND_TWP(0x18)   | \
 110                                         FTIM0_NAND_TWCHT(0x07) | \
 111                                         FTIM0_NAND_TWH(0x0a))
 112 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 113                                         FTIM1_NAND_TWBE(0x39)  | \
 114                                         FTIM1_NAND_TRR(0x0e)   | \
 115                                         FTIM1_NAND_TRP(0x18))
 116 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 117                                         FTIM2_NAND_TREH(0x0a) | \
 118                                         FTIM2_NAND_TWHRE(0x1e))
 119 #define CONFIG_SYS_NAND_FTIM3           0x0
 120
 121 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 122 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 123 #define CONFIG_MTD_NAND_VERIFY_WRITE
 124 #define CONFIG_CMD_NAND
 125
 126 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 127
 128 #ifndef SPL_NO_QIXIS
 129 #define CONFIG_FSL_QIXIS
 130 #endif
 131
 132 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 133 #define QIXIS_BRDCFG4_OFFSET            0x54
 134 #define QIXIS_LBMAP_SWITCH              2
 135 #define QIXIS_QMAP_MASK                 0xe0
 136 #define QIXIS_QMAP_SHIFT                5
 137 #define QIXIS_LBMAP_MASK                0x1f
 138 #define QIXIS_LBMAP_SHIFT               5
 139 #define QIXIS_LBMAP_DFLTBANK            0x00
 140 #define QIXIS_LBMAP_ALTBANK             0x20
 141 #define QIXIS_LBMAP_SD                  0x00
 142 #define QIXIS_LBMAP_EMMC                0x00
 143 #define QIXIS_LBMAP_SD_QSPI             0x00
 144 #define QIXIS_LBMAP_QSPI                0x00
 145 #define QIXIS_RCW_SRC_SD                0x40
 146 #define QIXIS_RCW_SRC_EMMC              0x41
 147 #define QIXIS_RCW_SRC_QSPI              0x62
 148 #define QIXIS_RST_CTL_RESET             0x31
 149 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 150 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 151 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 152 #define QIXIS_RST_FORCE_MEM             0x01
 153
 154 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 155 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 156                                         | CSPR_PORT_SIZE_8 \
 157                                         | CSPR_MSEL_GPCM \
 158                                         | CSPR_V)
 159 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 160                                         | CSPR_PORT_SIZE_8 \
 161                                         | CSPR_MSEL_GPCM \
 162                                         | CSPR_V)
 163
 164 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 165 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 166 /* QIXIS Timing parameters*/
 167 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 168                                         FTIM0_GPCM_TEADC(0x0e) | \
 169                                         FTIM0_GPCM_TEAHC(0x0e))
 170 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 171                                         FTIM1_GPCM_TRAD(0x3f))
 172 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 173                                         FTIM2_GPCM_TCH(0xf) | \
 174                                         FTIM2_GPCM_TWP(0x3E))
 175 #define SYS_FPGA_CS_FTIM3       0x0
 176
 177 #if defined(CONFIG_TFABOOT) || \
 178         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 179 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 180 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 181 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 182 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 183 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 184 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 185 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 186 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 187 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 188 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 189 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 190 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 191 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 192 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 193 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 194 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 195 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 196 #else
 197 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 198 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 199 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 200 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 201 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 202 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 203 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 204 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 205 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 206 #endif
 207
 208 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 209
 210 #define I2C_MUX_CH_VOL_MONITOR          0xA
 211 /* Voltage monitor on channel 2*/
 212 #define I2C_VOL_MONITOR_ADDR           0x63
 213 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 214 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 215 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 216 #define I2C_SVDD_MONITOR_ADDR           0x4F
 217
 218 #define CONFIG_VID_FLS_ENV              "ls1088ardb_vdd_mv"
 219 #define CONFIG_VID
 220
 221 /* The lowest and highest voltage allowed for LS1088ARDB */
 222 #define VDD_MV_MIN                      819
 223 #define VDD_MV_MAX                      1212
 224
 225 #define CONFIG_VOL_MONITOR_LTC3882_SET
 226 #define CONFIG_VOL_MONITOR_LTC3882_READ
 227
 228 /* PM Bus commands code for LTC3882*/
 229 #define PMBUS_CMD_PAGE                  0x0
 230 #define PMBUS_CMD_READ_VOUT             0x8B
 231 #define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
 232 #define PMBUS_CMD_VOUT_COMMAND          0x21
 233
 234 #define PWM_CHANNEL0                    0x0
 235
 236 /*
 237  * I2C bus multiplexer
 238  */
 239 #define I2C_MUX_PCA_ADDR_PRI            0x77
 240 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 241 #define I2C_RETIMER_ADDR                0x18
 242 #define I2C_MUX_CH_DEFAULT              0x8
 243 #define I2C_MUX_CH5                     0xD
 244
 245 #ifndef SPL_NO_RTC
 246 /*
 247 * RTC configuration
 248 */
 249 #define RTC
 250 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 251 #endif
 252
 253 /* EEPROM */
 254 #define CONFIG_ID_EEPROM
 255 #define CONFIG_SYS_I2C_EEPROM_NXID
 256 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 257 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 261
 262 #define CONFIG_CMD_MEMINFO
 263
 264 #ifdef CONFIG_SPL_BUILD
 265 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 266 #else
 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 268 #endif
 269
 270 #define CONFIG_FSL_MEMAC
 271
 272 #ifndef SPL_NO_ENV
 273 /* Initial environment variables */
 274 #ifdef CONFIG_TFABOOT
 275 #define QSPI_MC_INIT_CMD                                \
 276         "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"    \
 277         "sf read 0x80100000 0xE00000 0x100000;"                         \
 278         "env exists secureboot && "                     \
 279         "sf read 0x80640000 0x640000 0x40000 && "       \
 280         "sf read 0x80680000 0x680000 0x40000 && "       \
 281         "esbc_validate 0x80640000 && "                  \
 282         "esbc_validate 0x80680000 ;"                    \
 283         "fsl_mc start mc 0x80000000 0x80100000\0"
 284 #define SD_MC_INIT_CMD                          \
 285         "mmcinfo;mmc read 0x80000000 0x5000 0x800;"             \
 286         "mmc read 0x80100000 0x7000 0x800;"                             \
 287         "env exists secureboot && "                     \
 288         "mmc read 0x80640000 0x3200 0x20 && "           \
 289         "mmc read 0x80680000 0x3400 0x20 && "           \
 290         "esbc_validate 0x80640000 && "                  \
 291         "esbc_validate 0x80680000 ;"                    \
 292         "fsl_mc start mc 0x80000000 0x80100000\0"
 293 #else
 294 #if defined(CONFIG_QSPI_BOOT)
 295 #define MC_INIT_CMD                             \
 296         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 297         "sf read 0x80100000 0xE00000 0x100000;"                         \
 298         "env exists secureboot && "                     \
 299         "sf read 0x80640000 0x640000 0x40000 && "       \
 300         "sf read 0x80680000 0x680000 0x40000 && "       \
 301         "esbc_validate 0x80640000 && "                  \
 302         "esbc_validate 0x80680000 ;"                    \
 303         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 304         "mcmemsize=0x70000000\0"
 305 #elif defined(CONFIG_SD_BOOT)
 306 #define MC_INIT_CMD                             \
 307         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"           \
 308         "mmc read 0x80100000 0x7000 0x800;"                             \
 309         "env exists secureboot && "                     \
 310         "mmc read 0x80640000 0x3200 0x20 && "           \
 311         "mmc read 0x80680000 0x3400 0x20 && "           \
 312         "esbc_validate 0x80640000 && "                  \
 313         "esbc_validate 0x80680000 ;"                    \
 314         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 315         "mcmemsize=0x70000000\0"
 316 #endif
 317 #endif /* CONFIG_TFABOOT */
 318
 319 #undef CONFIG_EXTRA_ENV_SETTINGS
 320 #ifdef CONFIG_TFABOOT
 321 #define CONFIG_EXTRA_ENV_SETTINGS               \
 322         "BOARD=ls1088ardb\0"                    \
 323         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 324         "ramdisk_addr=0x800000\0"               \
 325         "ramdisk_size=0x2000000\0"              \
 326         "fdt_high=0xa0000000\0"                 \
 327         "initrd_high=0xffffffffffffffff\0"      \
 328         "fdt_addr=0x64f00000\0"                 \
 329         "kernel_addr=0x1000000\0"               \
 330         "kernel_addr_sd=0x8000\0"               \
 331         "kernelhdr_addr_sd=0x3000\0"            \
 332         "kernel_start=0x580100000\0"            \
 333         "kernelheader_start=0x580600000\0"      \
 334         "scriptaddr=0x80000000\0"               \
 335         "scripthdraddr=0x80080000\0"            \
 336         "fdtheader_addr_r=0x80100000\0"         \
 337         "kernelheader_addr=0x600000\0"          \
 338         "kernelheader_addr_r=0x80200000\0"      \
 339         "kernel_addr_r=0x81000000\0"            \
 340         "kernelheader_size=0x40000\0"           \
 341         "fdt_addr_r=0x90000000\0"               \
 342         "load_addr=0xa0000000\0"                \
 343         "kernel_size=0x2800000\0"               \
 344         "kernel_size_sd=0x14000\0"              \
 345         "kernelhdr_size_sd=0x20\0"              \
 346         QSPI_MC_INIT_CMD                        \
 347         "mcmemsize=0x70000000\0"                \
 348         BOOTENV                                 \
 349         "boot_scripts=ls1088ardb_boot.scr\0"    \
 350         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 351         "scan_dev_for_boot_part="               \
 352                 "part list ${devtype} ${devnum} devplist; "     \
 353                 "env exists devplist || setenv devplist 1; "    \
 354                 "for distro_bootpart in ${devplist}; do "       \
 355                         "if fstype ${devtype} "                 \
 356                                 "${devnum}:${distro_bootpart} " \
 357                                 "bootfstype; then "             \
 358                                 "run scan_dev_for_boot; "       \
 359                         "fi; "                                  \
 360                 "done\0"                                        \
 361         "boot_a_script="                                        \
 362                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 363                 "${scriptaddr} ${prefix}${script}; "            \
 364         "env exists secureboot && load ${devtype} "             \
 365                 "${devnum}:${distro_bootpart} "                 \
 366                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 367                 "env exists secureboot "                        \
 368                 "&& esbc_validate ${scripthdraddr};"            \
 369                 "source ${scriptaddr}\0"                        \
 370         "installer=load mmc 0:2 $load_addr "                    \
 371                 "/flex_installer_arm64.itb; "                   \
 372                 "env exists mcinitcmd && run mcinitcmd && "     \
 373                 "mmc read 0x80001000 0x6800 0x800;"             \
 374                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 375                 "bootm $load_addr#ls1088ardb\0"                 \
 376         "qspi_bootcmd=echo Trying load from qspi..;"            \
 377                 "sf probe && sf read $load_addr "               \
 378                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 379                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 380                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 381                 "bootm $load_addr#$BOARD\0"                     \
 382                 "sd_bootcmd=echo Trying load from sd card..;"           \
 383                 "mmcinfo; mmc read $load_addr "                 \
 384                 "$kernel_addr_sd $kernel_size_sd ;"             \
 385                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 386                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 387                 " && esbc_validate ${kernelheader_addr_r};"     \
 388                 "bootm $load_addr#$BOARD\0"
 389 #else
 390 #define CONFIG_EXTRA_ENV_SETTINGS               \
 391         "BOARD=ls1088ardb\0"                    \
 392         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 393         "ramdisk_addr=0x800000\0"               \
 394         "ramdisk_size=0x2000000\0"              \
 395         "fdt_high=0xa0000000\0"                 \
 396         "initrd_high=0xffffffffffffffff\0"      \
 397         "fdt_addr=0x64f00000\0"                 \
 398         "kernel_addr=0x1000000\0"               \
 399         "kernel_addr_sd=0x8000\0"               \
 400         "kernelhdr_addr_sd=0x3000\0"            \
 401         "kernel_start=0x580100000\0"            \
 402         "kernelheader_start=0x580800000\0"      \
 403         "scriptaddr=0x80000000\0"               \
 404         "scripthdraddr=0x80080000\0"            \
 405         "fdtheader_addr_r=0x80100000\0"         \
 406         "kernelheader_addr=0x600000\0"          \
 407         "kernelheader_addr_r=0x80200000\0"      \
 408         "kernel_addr_r=0x81000000\0"            \
 409         "kernelheader_size=0x40000\0"           \
 410         "fdt_addr_r=0x90000000\0"               \
 411         "load_addr=0xa0000000\0"                \
 412         "kernel_size=0x2800000\0"               \
 413         "kernel_size_sd=0x14000\0"              \
 414         "kernelhdr_size_sd=0x20\0"              \
 415         MC_INIT_CMD                             \
 416         BOOTENV                                 \
 417         "boot_scripts=ls1088ardb_boot.scr\0"    \
 418         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 419         "scan_dev_for_boot_part="               \
 420                 "part list ${devtype} ${devnum} devplist; "     \
 421                 "env exists devplist || setenv devplist 1; "    \
 422                 "for distro_bootpart in ${devplist}; do "       \
 423                         "if fstype ${devtype} "                 \
 424                                 "${devnum}:${distro_bootpart} " \
 425                                 "bootfstype; then "             \
 426                                 "run scan_dev_for_boot; "       \
 427                         "fi; "                                  \
 428                 "done\0"                                        \
 429         "boot_a_script="                                        \
 430                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 431                 "${scriptaddr} ${prefix}${script}; "            \
 432         "env exists secureboot && load ${devtype} "             \
 433                 "${devnum}:${distro_bootpart} "                 \
 434                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 435                 "&& esbc_validate ${scripthdraddr};"            \
 436                 "source ${scriptaddr}\0"                        \
 437         "installer=load mmc 0:2 $load_addr "                    \
 438                 "/flex_installer_arm64.itb; "                   \
 439                 "env exists mcinitcmd && run mcinitcmd && "     \
 440                 "mmc read 0x80001000 0x6800 0x800;"             \
 441                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 442                 "bootm $load_addr#ls1088ardb\0"                 \
 443         "qspi_bootcmd=echo Trying load from qspi..;"            \
 444                 "sf probe && sf read $load_addr "               \
 445                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 446                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 447                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 448                 "bootm $load_addr#$BOARD\0"                     \
 449                 "sd_bootcmd=echo Trying load from sd card..;"           \
 450                 "mmcinfo; mmc read $load_addr "                 \
 451                 "$kernel_addr_sd $kernel_size_sd ;"             \
 452                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 453                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 454                 " && esbc_validate ${kernelheader_addr_r};"     \
 455                 "bootm $load_addr#$BOARD\0"
 456 #endif /* CONFIG_TFABOOT */
 457
 458 #undef CONFIG_BOOTCOMMAND
 459 #ifdef CONFIG_TFABOOT
 460 #define QSPI_NOR_BOOTCOMMAND                                    \
 461         "sf read 0x80001000 0xd00000 0x100000;"         \
 462                 "env exists mcinitcmd && env exists secureboot "        \
 463                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 464                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 465                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 466                 "run distro_bootcmd;run qspi_bootcmd;"          \
 467                 "env exists secureboot && esbc_halt;"
 468 #define SD_BOOTCOMMAND                                          \
 469                 "env exists mcinitcmd && mmcinfo; "             \
 470                 "mmc read 0x80001000 0x6800 0x800; "            \
 471                 "env exists mcinitcmd && env exists secureboot "        \
 472                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 473                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 474                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 475                 "run distro_bootcmd;run sd_bootcmd;"            \
 476                 "env exists secureboot && esbc_halt;"
 477 #else
 478 #if defined(CONFIG_QSPI_BOOT)
 479 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 480 #define CONFIG_BOOTCOMMAND                                      \
 481                 "sf read 0x80001000 0xd00000 0x100000;"         \
 482                 "env exists mcinitcmd && env exists secureboot "        \
 483                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 484                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 485                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 486                 "run distro_bootcmd;run qspi_bootcmd;"          \
 487                 "env exists secureboot && esbc_halt;"
 488
 489 /* Try to boot an on-SD kernel first, then do normal distro boot */
 490 #elif defined(CONFIG_SD_BOOT)
 491 #define CONFIG_BOOTCOMMAND                                      \
 492                 "env exists mcinitcmd && mmcinfo; "             \
 493                 "mmc read 0x80001000 0x6800 0x800; "            \
 494                 "env exists mcinitcmd && env exists secureboot "        \
 495                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 496                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 497                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 498                 "run distro_bootcmd;run sd_bootcmd;"            \
 499                 "env exists secureboot && esbc_halt;"
 500 #endif
 501 #endif /* CONFIG_TFABOOT */
 502
 503 /* MAC/PHY configuration */
 504 #ifdef CONFIG_FSL_MC_ENET
 505 #define AQ_PHY_ADDR1                    0x00
 506 #define AQR105_IRQ_MASK                 0x00000004
 507
 508 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 509 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 510 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 511 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 512 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 513 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 514 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 515 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 516
 517 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 518 #define CONFIG_PHY_GIGE
 519 #endif
 520 #endif
 521
 522 /*  MMC  */
 523 #ifdef CONFIG_MMC
 524 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 525 #endif
 526
 527 #ifndef SPL_NO_ENV
 528
 529 #define BOOT_TARGET_DEVICES(func) \
 530         func(MMC, mmc, 0) \
 531         func(SCSI, scsi, 0) \
 532         func(DHCP, dhcp, na)
 533 #include <config_distro_bootcmd.h>
 534 #endif
 535
 536 #include <asm/fsl_secure_boot.h>
 537
 538 #endif /* __LS1088A_RDB_H */