include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #define CONFIG_MISC_INIT_R
  12
  13 #if defined(CONFIG_QSPI_BOOT)
  14 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  15 #define CONFIG_ENV_SECT_SIZE            0x40000
  16 #elif defined(CONFIG_SD_BOOT)
  17 #define CONFIG_ENV_OFFSET               (3 * 1024 * 1024)
  18 #define CONFIG_SYS_MMC_ENV_DEV          0
  19 #define CONFIG_ENV_SIZE                 0x2000
  20 #else
  21 #define CONFIG_ENV_IS_IN_FLASH
  22 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
  23 #define CONFIG_ENV_SECT_SIZE            0x20000
  24 #define CONFIG_ENV_SIZE                 0x20000
  25 #endif
  26
  27 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  28 #ifndef CONFIG_SPL_BUILD
  29 #define CONFIG_QIXIS_I2C_ACCESS
  30 #endif
  31 #define SYS_NO_FLASH
  32 #undef CONFIG_CMD_IMLS
  33 #endif
  34
  35 #define CONFIG_SYS_CLK_FREQ             100000000
  36 #define CONFIG_DDR_CLK_FREQ             100000000
  37 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  38 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  39
  40 #define CONFIG_DDR_SPD
  41 #ifdef CONFIG_EMU
  42 #define CONFIG_SYS_FSL_DDR_EMU
  43 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  44 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  45 #else
  46 #define CONFIG_DDR_ECC
  47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  48 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  49 #endif
  50 #define SPD_EEPROM_ADDRESS      0x51
  51 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  52 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  53
  54
  55 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  56 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  57 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  58 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  59
  60 #define CONFIG_SYS_NOR0_CSPR                                    \
  61         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  62         CSPR_PORT_SIZE_16                                       | \
  63         CSPR_MSEL_NOR                                           | \
  64         CSPR_V)
  65 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  66         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  67         CSPR_PORT_SIZE_16                                       | \
  68         CSPR_MSEL_NOR                                           | \
  69         CSPR_V)
  70 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  71 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  72                                 FTIM0_NOR_TEADC(0x1) | \
  73                                 FTIM0_NOR_TEAHC(0x1))
  74 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  75                                 FTIM1_NOR_TRAD_NOR(0x1))
  76 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  77                                 FTIM2_NOR_TCH(0x0) | \
  78                                 FTIM2_NOR_TWP(0x1))
  79 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  80 #define CONFIG_SYS_IFC_CCR      0x01000000
  81
  82 #ifndef SYS_NO_FLASH
  83 #define CONFIG_FLASH_CFI_DRIVER
  84 #define CONFIG_SYS_FLASH_CFI
  85 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  86 #define CONFIG_SYS_FLASH_QUIET_TEST
  87 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  88
  89 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  90 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  91 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  92 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  93
  94 #define CONFIG_SYS_FLASH_EMPTY_INFO
  95 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  96 #endif
  97 #endif
  98
  99 #ifndef SPL_NO_IFC
 100 #define CONFIG_NAND_FSL_IFC
 101 #endif
 102
 103 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 104 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 105
 106 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 107 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 108                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 109                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 110                                 | CSPR_V)
 111 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 112
 113 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 114                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 115                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 116                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 117                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 118                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 119                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 120
 121 #define CONFIG_SYS_NAND_ONFI_DETECTION
 122
 123 /* ONFI NAND Flash mode0 Timing Params */
 124 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 125                                         FTIM0_NAND_TWP(0x18)   | \
 126                                         FTIM0_NAND_TWCHT(0x07) | \
 127                                         FTIM0_NAND_TWH(0x0a))
 128 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 129                                         FTIM1_NAND_TWBE(0x39)  | \
 130                                         FTIM1_NAND_TRR(0x0e)   | \
 131                                         FTIM1_NAND_TRP(0x18))
 132 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 133                                         FTIM2_NAND_TREH(0x0a) | \
 134                                         FTIM2_NAND_TWHRE(0x1e))
 135 #define CONFIG_SYS_NAND_FTIM3           0x0
 136
 137 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 138 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 139 #define CONFIG_MTD_NAND_VERIFY_WRITE
 140 #define CONFIG_CMD_NAND
 141
 142 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 143
 144 #ifndef SPL_NO_QIXIS
 145 #define CONFIG_FSL_QIXIS
 146 #endif
 147
 148 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 149 #define QIXIS_BRDCFG4_OFFSET            0x54
 150 #define QIXIS_LBMAP_SWITCH              2
 151 #define QIXIS_QMAP_MASK                 0xe0
 152 #define QIXIS_QMAP_SHIFT                5
 153 #define QIXIS_LBMAP_MASK                0x1f
 154 #define QIXIS_LBMAP_SHIFT               5
 155 #define QIXIS_LBMAP_DFLTBANK            0x00
 156 #define QIXIS_LBMAP_ALTBANK             0x20
 157 #define QIXIS_LBMAP_SD                  0x00
 158 #define QIXIS_LBMAP_EMMC                0x00
 159 #define QIXIS_LBMAP_SD_QSPI             0x00
 160 #define QIXIS_LBMAP_QSPI                0x00
 161 #define QIXIS_RCW_SRC_SD                0x40
 162 #define QIXIS_RCW_SRC_EMMC              0x41
 163 #define QIXIS_RCW_SRC_QSPI              0x62
 164 #define QIXIS_RST_CTL_RESET             0x31
 165 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 166 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 167 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 168 #define QIXIS_RST_FORCE_MEM             0x01
 169
 170 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 171 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 172                                         | CSPR_PORT_SIZE_8 \
 173                                         | CSPR_MSEL_GPCM \
 174                                         | CSPR_V)
 175 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 176                                         | CSPR_PORT_SIZE_8 \
 177                                         | CSPR_MSEL_GPCM \
 178                                         | CSPR_V)
 179
 180 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 181 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 182 /* QIXIS Timing parameters*/
 183 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 184                                         FTIM0_GPCM_TEADC(0x0e) | \
 185                                         FTIM0_GPCM_TEAHC(0x0e))
 186 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 187                                         FTIM1_GPCM_TRAD(0x3f))
 188 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 189                                         FTIM2_GPCM_TCH(0xf) | \
 190                                         FTIM2_GPCM_TWP(0x3E))
 191 #define SYS_FPGA_CS_FTIM3       0x0
 192
 193 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 194 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 195 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 196 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 197 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 198 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 199 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 200 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 201 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 202 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 203 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 204 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 205 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 206 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 207 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 208 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 209 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 210 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 211 #else
 212 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 213 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 214 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 215 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 216 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 217 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 218 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 219 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 220 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 221 #endif
 222
 223
 224 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 225
 226 #define I2C_MUX_CH_VOL_MONITOR          0xA
 227 /* Voltage monitor on channel 2*/
 228 #define I2C_VOL_MONITOR_ADDR           0x63
 229 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 230 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 231 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 232 #define I2C_SVDD_MONITOR_ADDR           0x4F
 233
 234 #define CONFIG_VID_FLS_ENV              "ls1088ardb_vdd_mv"
 235 #define CONFIG_VID
 236
 237 /* The lowest and highest voltage allowed for LS1088ARDB */
 238 #define VDD_MV_MIN                      819
 239 #define VDD_MV_MAX                      1212
 240
 241 #define CONFIG_VOL_MONITOR_LTC3882_SET
 242 #define CONFIG_VOL_MONITOR_LTC3882_READ
 243
 244 /* PM Bus commands code for LTC3882*/
 245 #define PMBUS_CMD_PAGE                  0x0
 246 #define PMBUS_CMD_READ_VOUT             0x8B
 247 #define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
 248 #define PMBUS_CMD_VOUT_COMMAND          0x21
 249
 250 #define PWM_CHANNEL0                    0x0
 251
 252 /*
 253  * I2C bus multiplexer
 254  */
 255 #define I2C_MUX_PCA_ADDR_PRI            0x77
 256 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 257 #define I2C_RETIMER_ADDR                0x18
 258 #define I2C_MUX_CH_DEFAULT              0x8
 259 #define I2C_MUX_CH5                     0xD
 260
 261 #ifndef SPL_NO_RTC
 262 /*
 263 * RTC configuration
 264 */
 265 #define RTC
 266 #define CONFIG_RTC_PCF8563 1
 267 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 268 #define CONFIG_CMD_DATE
 269 #endif
 270
 271 /* EEPROM */
 272 #define CONFIG_ID_EEPROM
 273 #define CONFIG_SYS_I2C_EEPROM_NXID
 274 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 275 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 276 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 277 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 278 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 279
 280 #ifndef SPL_NO_QSPI
 281 /* QSPI device */
 282 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 283 #define CONFIG_FSL_QSPI
 284 #define FSL_QSPI_FLASH_SIZE             (1 << 26)
 285 #define FSL_QSPI_FLASH_NUM              2
 286 #endif
 287 #endif
 288
 289 #define CONFIG_CMD_MEMINFO
 290 #define CONFIG_SYS_MEMTEST_START        0x80000000
 291 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 292
 293 #ifdef CONFIG_SPL_BUILD
 294 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 295 #else
 296 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 297 #endif
 298
 299 #define CONFIG_FSL_MEMAC
 300
 301 #ifndef SPL_NO_ENV
 302 /* Initial environment variables */
 303 #if defined(CONFIG_QSPI_BOOT)
 304 #define MC_INIT_CMD                             \
 305         "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;"  \
 306         "sf read 0x80100000 0xE00000 0x100000;"                         \
 307         "env exists secureboot && "                     \
 308         "sf read 0x80700000 0x700000 0x40000 && "       \
 309         "sf read 0x80740000 0x740000 0x40000 && "       \
 310         "esbc_validate 0x80700000 && "                  \
 311         "esbc_validate 0x80740000 ;"                    \
 312         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 313         "mcmemsize=0x70000000\0"
 314 #elif defined(CONFIG_SD_BOOT)
 315 #define MC_INIT_CMD                             \
 316         "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"           \
 317         "mmc read 0x80100000 0x7000 0x800;"                             \
 318         "env exists secureboot && "                     \
 319         "mmc read 0x80700000 0x3800 0x10 && "           \
 320         "mmc read 0x80740000 0x3A00 0x10 && "           \
 321         "esbc_validate 0x80700000 && "                  \
 322         "esbc_validate 0x80740000 ;"                    \
 323         "fsl_mc start mc 0x80000000 0x80100000\0"       \
 324         "mcmemsize=0x70000000\0"
 325 #endif
 326
 327 #undef CONFIG_EXTRA_ENV_SETTINGS
 328 #define CONFIG_EXTRA_ENV_SETTINGS               \
 329         "BOARD=ls1088ardb\0"                    \
 330         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 331         "ramdisk_addr=0x800000\0"               \
 332         "ramdisk_size=0x2000000\0"              \
 333         "fdt_high=0xa0000000\0"                 \
 334         "initrd_high=0xffffffffffffffff\0"      \
 335         "fdt_addr=0x64f00000\0"                 \
 336         "kernel_addr=0x1000000\0"               \
 337         "kernel_addr_sd=0x8000\0"               \
 338         "kernelhdr_addr_sd=0x4000\0"            \
 339         "kernel_start=0x580100000\0"            \
 340         "kernelheader_start=0x580800000\0"      \
 341         "scriptaddr=0x80000000\0"               \
 342         "scripthdraddr=0x80080000\0"            \
 343         "fdtheader_addr_r=0x80100000\0"         \
 344         "kernelheader_addr=0x800000\0"          \
 345         "kernelheader_addr_r=0x80200000\0"      \
 346         "kernel_addr_r=0x81000000\0"            \
 347         "kernelheader_size=0x40000\0"           \
 348         "fdt_addr_r=0x90000000\0"               \
 349         "load_addr=0xa0000000\0"                \
 350         "kernel_size=0x2800000\0"               \
 351         "kernel_size_sd=0x14000\0"              \
 352         "kernelhdr_size_sd=0x10\0"              \
 353         MC_INIT_CMD                             \
 354         BOOTENV                                 \
 355         "boot_scripts=ls1088ardb_boot.scr\0"    \
 356         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 357         "scan_dev_for_boot_part="               \
 358                 "part list ${devtype} ${devnum} devplist; "     \
 359                 "env exists devplist || setenv devplist 1; "    \
 360                 "for distro_bootpart in ${devplist}; do "       \
 361                         "if fstype ${devtype} "                 \
 362                                 "${devnum}:${distro_bootpart} " \
 363                                 "bootfstype; then "             \
 364                                 "run scan_dev_for_boot; "       \
 365                         "fi; "                                  \
 366                 "done\0"                                        \
 367         "scan_dev_for_boot="                                    \
 368                 "echo Scanning ${devtype} "                     \
 369                 "${devnum}:${distro_bootpart}...; "             \
 370                 "for prefix in ${boot_prefixes}; do "           \
 371                         "run scan_dev_for_scripts; "            \
 372                 "done;\0"                                       \
 373         "boot_a_script="                                        \
 374                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 375                 "${scriptaddr} ${prefix}${script}; "            \
 376         "env exists secureboot && load ${devtype} "             \
 377                 "${devnum}:${distro_bootpart} "                 \
 378                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 379                 "&& esbc_validate ${scripthdraddr};"            \
 380                 "source ${scriptaddr}\0"                        \
 381         "installer=load mmc 0:2 $load_addr "                    \
 382                 "/flex_installer_arm64.itb; "                   \
 383                 "env exists mcinitcmd && run mcinitcmd && "     \
 384                 "mmc read 0x80001000 0x6800 0x800;"             \
 385                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 386                 "bootm $load_addr#ls1088ardb\0"                 \
 387         "qspi_bootcmd=echo Trying load from qspi..;"            \
 388                 "sf probe && sf read $load_addr "               \
 389                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 390                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 391                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 392                 "bootm $load_addr#$BOARD\0"                     \
 393                 "sd_bootcmd=echo Trying load from sd card..;"           \
 394                 "mmcinfo; mmc read $load_addr "                 \
 395                 "$kernel_addr_sd $kernel_size_sd ;"             \
 396                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 397                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 398                 " && esbc_validate ${kernelheader_addr_r};"     \
 399                 "bootm $load_addr#$BOARD\0"
 400
 401 #undef CONFIG_BOOTCOMMAND
 402 #if defined(CONFIG_QSPI_BOOT)
 403 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 404 #define CONFIG_BOOTCOMMAND                                      \
 405                 "sf read 0x80001000 0xd00000 0x100000;"         \
 406                 "env exists mcinitcmd && env exists secureboot "        \
 407                 " && sf read 0x80780000 0x780000 0x100000 "     \
 408                 "&& esbc_validate 0x80780000;env exists mcinitcmd "     \
 409                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 410                 "run distro_bootcmd;run qspi_bootcmd;"          \
 411                 "env exists secureboot && esbc_halt;"
 412
 413 /* Try to boot an on-SD kernel first, then do normal distro boot */
 414 #elif defined(CONFIG_SD_BOOT)
 415 #define CONFIG_BOOTCOMMAND                                      \
 416                 "env exists mcinitcmd && mmcinfo; "             \
 417                 "mmc read 0x80001000 0x6800 0x800; "            \
 418                 "env exists mcinitcmd && env exists secureboot "        \
 419                 " && mmc read 0x80780000 0x3C00 0x10 "          \
 420                 "&& esbc_validate 0x80780000;env exists mcinitcmd "     \
 421                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 422                 "run distro_bootcmd;run sd_bootcmd;"            \
 423                 "env exists secureboot && esbc_halt;"
 424 #endif
 425
 426 /* MAC/PHY configuration */
 427 #ifdef CONFIG_FSL_MC_ENET
 428 #define CONFIG_PHYLIB_10G
 429 #define CONFIG_PHY_GIGE
 430 #define CONFIG_PHYLIB
 431
 432 #define CONFIG_PHY_VITESSE
 433 #define CONFIG_PHY_AQUANTIA
 434 #define AQ_PHY_ADDR1                    0x00
 435 #define AQR105_IRQ_MASK                 0x00000004
 436
 437 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 438 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 439 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 440 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 441 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 442 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 443 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 444 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 445
 446 #define CONFIG_MII
 447 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 448 #define CONFIG_PHY_GIGE
 449 #endif
 450 #endif
 451
 452 /*  MMC  */
 453 #ifdef CONFIG_MMC
 454 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 455 #endif
 456
 457 #ifndef SPL_NO_ENV
 458
 459 #define BOOT_TARGET_DEVICES(func) \
 460         func(MMC, mmc, 0) \
 461         func(SCSI, scsi, 0) \
 462         func(DHCP, dhcp, na)
 463 #include <config_distro_bootcmd.h>
 464 #endif
 465
 466 #include <asm/fsl_secure_boot.h>
 467
 468 #endif /* __LS1088A_RDB_H */