1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_RDB_H
7 #define __LS1088A_RDB_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_TFABOOT) || \
12 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
16 #define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
18 #define SPD_EEPROM_ADDRESS 0x51
21 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
22 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
23 #define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
24 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
26 #define CFG_SYS_NOR0_CSPR \
27 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
31 #define CFG_SYS_NOR0_CSPR_EARLY \
32 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
36 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
37 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
38 FTIM0_NOR_TEADC(0x1) | \
40 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
41 FTIM1_NOR_TRAD_NOR(0x1))
42 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
43 FTIM2_NOR_TCH(0x0) | \
45 #define CFG_SYS_NOR_FTIM3 0x04000000
46 #define CFG_SYS_IFC_CCR 0x01000000
49 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
53 #define CFG_SYS_NAND_CSPR_EXT (0x0)
54 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
55 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
56 | CSPR_MSEL_NAND /* MSEL = NAND */ \
58 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
60 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
61 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
62 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
63 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
64 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
65 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
66 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
68 /* ONFI NAND Flash mode0 Timing Params */
69 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
70 FTIM0_NAND_TWP(0x18) | \
71 FTIM0_NAND_TWCHT(0x07) | \
73 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
74 FTIM1_NAND_TWBE(0x39) | \
75 FTIM1_NAND_TRR(0x0e) | \
77 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
78 FTIM2_NAND_TREH(0x0a) | \
79 FTIM2_NAND_TWHRE(0x1e))
80 #define CFG_SYS_NAND_FTIM3 0x0
82 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
84 #define CFG_SYS_I2C_FPGA_ADDR 0x66
85 #define QIXIS_BRDCFG4_OFFSET 0x54
86 #define QIXIS_LBMAP_SWITCH 2
87 #define QIXIS_QMAP_MASK 0xe0
88 #define QIXIS_QMAP_SHIFT 5
89 #define QIXIS_LBMAP_MASK 0x1f
90 #define QIXIS_LBMAP_SHIFT 5
91 #define QIXIS_LBMAP_DFLTBANK 0x00
92 #define QIXIS_LBMAP_ALTBANK 0x20
93 #define QIXIS_LBMAP_SD 0x00
94 #define QIXIS_LBMAP_EMMC 0x00
95 #define QIXIS_LBMAP_SD_QSPI 0x00
96 #define QIXIS_LBMAP_QSPI 0x00
97 #define QIXIS_RCW_SRC_SD 0x40
98 #define QIXIS_RCW_SRC_EMMC 0x41
99 #define QIXIS_RCW_SRC_QSPI 0x62
100 #define QIXIS_RST_CTL_RESET 0x31
101 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
102 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
103 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
104 #define QIXIS_RST_FORCE_MEM 0x01
106 #define CFG_SYS_FPGA_CSPR_EXT (0x0)
107 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
111 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
116 #define CFG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
117 #define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
118 /* QIXIS Timing parameters*/
119 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
120 FTIM0_GPCM_TEADC(0x0e) | \
121 FTIM0_GPCM_TEAHC(0x0e))
122 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
123 FTIM1_GPCM_TRAD(0x3f))
124 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
125 FTIM2_GPCM_TCH(0xf) | \
126 FTIM2_GPCM_TWP(0x3E))
127 #define SYS_FPGA_CS_FTIM3 0x0
129 #if defined(CONFIG_TFABOOT) || \
130 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
131 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
132 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
133 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
134 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
135 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
136 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
137 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
138 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
139 #define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT
140 #define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR
141 #define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
142 #define CFG_SYS_AMASK2 CFG_SYS_FPGA_AMASK
143 #define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR
144 #define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
145 #define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
146 #define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
147 #define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
149 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
150 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
151 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
152 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
153 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
154 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
155 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
156 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
157 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
160 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
162 #define I2C_MUX_CH_VOL_MONITOR 0xA
163 /* Voltage monitor on channel 2*/
164 #define I2C_VOL_MONITOR_ADDR 0x63
165 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
166 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
167 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
168 #define I2C_SVDD_MONITOR_ADDR 0x4F
170 /* The lowest and highest voltage allowed for LS1088ARDB */
171 #define VDD_MV_MIN 819
172 #define VDD_MV_MAX 1212
174 #define PWM_CHANNEL0 0x0
177 * I2C bus multiplexer
179 #define I2C_MUX_PCA_ADDR_PRI 0x77
180 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
181 #define I2C_RETIMER_ADDR 0x18
182 #define I2C_MUX_CH_DEFAULT 0x8
183 #define I2C_MUX_CH5 0xD
188 #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
191 /* Initial environment variables */
192 #ifdef CONFIG_TFABOOT
193 #define QSPI_MC_INIT_CMD \
194 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
195 "sf read 0x80e00000 0xE00000 0x100000;" \
196 "env exists secureboot && " \
197 "sf read 0x80640000 0x640000 0x40000 && " \
198 "sf read 0x80680000 0x680000 0x40000 && " \
199 "esbc_validate 0x80640000 && " \
200 "esbc_validate 0x80680000 ;" \
201 "fsl_mc start mc 0x80a00000 0x80e00000\0"
202 #define SD_MC_INIT_CMD \
203 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
204 "mmc read 0x80e00000 0x7000 0x800;" \
205 "env exists secureboot && " \
206 "mmc read 0x80640000 0x3200 0x20 && " \
207 "mmc read 0x80680000 0x3400 0x20 && " \
208 "esbc_validate 0x80640000 && " \
209 "esbc_validate 0x80680000 ;" \
210 "fsl_mc start mc 0x80a00000 0x80e00000\0"
212 #if defined(CONFIG_QSPI_BOOT)
213 #define MC_INIT_CMD \
214 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
215 "sf read 0x80e00000 0xE00000 0x100000;" \
216 "env exists secureboot && " \
217 "sf read 0x80640000 0x640000 0x40000 && " \
218 "sf read 0x80680000 0x680000 0x40000 && " \
219 "esbc_validate 0x80640000 && " \
220 "esbc_validate 0x80680000 ;" \
221 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
222 "mcmemsize=0x70000000\0"
223 #elif defined(CONFIG_SD_BOOT)
224 #define MC_INIT_CMD \
225 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
226 "mmc read 0x80e00000 0x7000 0x800;" \
227 "env exists secureboot && " \
228 "mmc read 0x80640000 0x3200 0x20 && " \
229 "mmc read 0x80680000 0x3400 0x20 && " \
230 "esbc_validate 0x80640000 && " \
231 "esbc_validate 0x80680000 ;" \
232 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
233 "mcmemsize=0x70000000\0"
235 #endif /* CONFIG_TFABOOT */
237 #undef CONFIG_EXTRA_ENV_SETTINGS
238 #ifdef CONFIG_TFABOOT
239 #define CONFIG_EXTRA_ENV_SETTINGS \
240 "BOARD=ls1088ardb\0" \
241 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
242 "ramdisk_addr=0x800000\0" \
243 "ramdisk_size=0x2000000\0" \
244 "fdt_high=0xa0000000\0" \
245 "initrd_high=0xffffffffffffffff\0" \
246 "kernel_addr=0x1000000\0" \
247 "kernel_addr_sd=0x8000\0" \
248 "kernelhdr_addr_sd=0x3000\0" \
249 "kernel_start=0x580100000\0" \
250 "kernelheader_start=0x580600000\0" \
251 "scriptaddr=0x80000000\0" \
252 "scripthdraddr=0x80080000\0" \
253 "fdtheader_addr_r=0x80100000\0" \
254 "kernelheader_addr=0x600000\0" \
255 "kernelheader_addr_r=0x80200000\0" \
256 "kernel_addr_r=0x81000000\0" \
257 "kernelheader_size=0x40000\0" \
258 "fdt_addr_r=0x90000000\0" \
259 "load_addr=0xa0000000\0" \
260 "kernel_size=0x2800000\0" \
261 "kernel_size_sd=0x14000\0" \
262 "kernelhdr_size_sd=0x20\0" \
264 "mcmemsize=0x70000000\0" \
266 "boot_scripts=ls1088ardb_boot.scr\0" \
267 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
268 "scan_dev_for_boot_part=" \
269 "part list ${devtype} ${devnum} devplist; " \
270 "env exists devplist || setenv devplist 1; " \
271 "for distro_bootpart in ${devplist}; do " \
272 "if fstype ${devtype} " \
273 "${devnum}:${distro_bootpart} " \
274 "bootfstype; then " \
275 "run scan_dev_for_boot; " \
279 "load ${devtype} ${devnum}:${distro_bootpart} " \
280 "${scriptaddr} ${prefix}${script}; " \
281 "env exists secureboot && load ${devtype} " \
282 "${devnum}:${distro_bootpart} " \
283 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
284 "env exists secureboot " \
285 "&& esbc_validate ${scripthdraddr};" \
286 "source ${scriptaddr}\0" \
287 "installer=load mmc 0:2 $load_addr " \
288 "/flex_installer_arm64.itb; " \
289 "env exists mcinitcmd && run mcinitcmd && " \
290 "mmc read 0x80001000 0x6800 0x800;" \
291 "fsl_mc lazyapply dpl 0x80001000;" \
292 "bootm $load_addr#ls1088ardb\0" \
293 "qspi_bootcmd=echo Trying load from qspi..;" \
294 "sf probe && sf read $load_addr " \
295 "$kernel_addr $kernel_size ; env exists secureboot " \
296 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
297 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
298 "bootm $load_addr#$BOARD\0" \
299 "sd_bootcmd=echo Trying load from sd card..;" \
300 "mmcinfo; mmc read $load_addr " \
301 "$kernel_addr_sd $kernel_size_sd ;" \
302 "env exists secureboot && mmc read $kernelheader_addr_r "\
303 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
304 " && esbc_validate ${kernelheader_addr_r};" \
305 "bootm $load_addr#$BOARD\0"
307 #define CONFIG_EXTRA_ENV_SETTINGS \
308 "BOARD=ls1088ardb\0" \
309 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
310 "ramdisk_addr=0x800000\0" \
311 "ramdisk_size=0x2000000\0" \
312 "fdt_high=0xa0000000\0" \
313 "initrd_high=0xffffffffffffffff\0" \
314 "kernel_addr=0x1000000\0" \
315 "kernel_addr_sd=0x8000\0" \
316 "kernelhdr_addr_sd=0x3000\0" \
317 "kernel_start=0x580100000\0" \
318 "kernelheader_start=0x580800000\0" \
319 "scriptaddr=0x80000000\0" \
320 "scripthdraddr=0x80080000\0" \
321 "fdtheader_addr_r=0x80100000\0" \
322 "kernelheader_addr=0x600000\0" \
323 "kernelheader_addr_r=0x80200000\0" \
324 "kernel_addr_r=0x81000000\0" \
325 "kernelheader_size=0x40000\0" \
326 "fdt_addr_r=0x90000000\0" \
327 "load_addr=0xa0000000\0" \
328 "kernel_size=0x2800000\0" \
329 "kernel_size_sd=0x14000\0" \
330 "kernelhdr_size_sd=0x20\0" \
333 "boot_scripts=ls1088ardb_boot.scr\0" \
334 "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
335 "scan_dev_for_boot_part=" \
336 "part list ${devtype} ${devnum} devplist; " \
337 "env exists devplist || setenv devplist 1; " \
338 "for distro_bootpart in ${devplist}; do " \
339 "if fstype ${devtype} " \
340 "${devnum}:${distro_bootpart} " \
341 "bootfstype; then " \
342 "run scan_dev_for_boot; " \
346 "load ${devtype} ${devnum}:${distro_bootpart} " \
347 "${scriptaddr} ${prefix}${script}; " \
348 "env exists secureboot && load ${devtype} " \
349 "${devnum}:${distro_bootpart} " \
350 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
351 "&& esbc_validate ${scripthdraddr};" \
352 "source ${scriptaddr}\0" \
353 "installer=load mmc 0:2 $load_addr " \
354 "/flex_installer_arm64.itb; " \
355 "env exists mcinitcmd && run mcinitcmd && " \
356 "mmc read 0x80001000 0x6800 0x800;" \
357 "fsl_mc lazyapply dpl 0x80001000;" \
358 "bootm $load_addr#ls1088ardb\0" \
359 "qspi_bootcmd=echo Trying load from qspi..;" \
360 "sf probe && sf read $load_addr " \
361 "$kernel_addr $kernel_size ; env exists secureboot " \
362 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
363 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
364 "bootm $load_addr#$BOARD\0" \
365 "sd_bootcmd=echo Trying load from sd card..;" \
366 "mmcinfo; mmc read $load_addr " \
367 "$kernel_addr_sd $kernel_size_sd ;" \
368 "env exists secureboot && mmc read $kernelheader_addr_r "\
369 "$kernelhdr_addr_sd $kernelhdr_size_sd " \
370 " && esbc_validate ${kernelheader_addr_r};" \
371 "bootm $load_addr#$BOARD\0"
372 #endif /* CONFIG_TFABOOT */
374 #ifdef CONFIG_TFABOOT
375 #define QSPI_NOR_BOOTCOMMAND \
376 "sf read 0x80001000 0xd00000 0x100000;" \
377 "env exists mcinitcmd && env exists secureboot " \
378 " && sf read 0x806C0000 0x6C0000 0x100000 " \
379 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
380 "&& fsl_mc lazyapply dpl 0x80001000;" \
381 "run distro_bootcmd;run qspi_bootcmd;" \
382 "env exists secureboot && esbc_halt;"
383 #define SD_BOOTCOMMAND \
384 "env exists mcinitcmd && mmcinfo; " \
385 "mmc read 0x80001000 0x6800 0x800; " \
386 "env exists mcinitcmd && env exists secureboot " \
387 " && mmc read 0x806C0000 0x3600 0x20 " \
388 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
389 "&& fsl_mc lazyapply dpl 0x80001000;" \
390 "run distro_bootcmd;run sd_bootcmd;" \
391 "env exists secureboot && esbc_halt;"
393 #if defined(CONFIG_QSPI_BOOT)
394 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
396 /* Try to boot an on-SD kernel first, then do normal distro boot */
398 #endif /* CONFIG_TFABOOT */
400 /* MAC/PHY configuration */
401 #ifdef CONFIG_FSL_MC_ENET
402 #define AQ_PHY_ADDR1 0x00
403 #define AQR105_IRQ_MASK 0x00000004
405 #define QSGMII1_PORT1_PHY_ADDR 0x0c
406 #define QSGMII1_PORT2_PHY_ADDR 0x0d
407 #define QSGMII1_PORT3_PHY_ADDR 0x0e
408 #define QSGMII1_PORT4_PHY_ADDR 0x0f
409 #define QSGMII2_PORT1_PHY_ADDR 0x1c
410 #define QSGMII2_PORT2_PHY_ADDR 0x1d
411 #define QSGMII2_PORT3_PHY_ADDR 0x1e
412 #define QSGMII2_PORT4_PHY_ADDR 0x1f
418 #define BOOT_TARGET_DEVICES(func) \
421 func(SCSI, scsi, 0) \
423 #include <config_distro_bootcmd.h>
426 #include <asm/fsl_secure_boot.h>
428 #endif /* __LS1088A_RDB_H */