include/configs/ls1088aqds.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_QDS_H
   7 #define __LS1088A_QDS_H
   8
   9 #include "ls1088a_common.h"
  10
  11
  12 #ifndef __ASSEMBLY__
  13 unsigned long get_board_sys_clk(void);
  14 #endif
  15
  16 #ifdef CONFIG_TFABOOT
  17 #define CONFIG_MISC_INIT_R
  18 #endif
  19
  20 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  21 #define CONFIG_QIXIS_I2C_ACCESS
  22 #define SYS_NO_FLASH
  23
  24 #define CONFIG_SYS_CLK_FREQ             100000000
  25 #else
  26 #define CONFIG_QIXIS_I2C_ACCESS
  27 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  28 #endif
  29
  30 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  31 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  32
  33 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  34
  35 #define CONFIG_DDR_SPD
  36 #define CONFIG_DDR_ECC
  37 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  38 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  39 #define SPD_EEPROM_ADDRESS              0x51
  40 #define CONFIG_SYS_SPD_BUS_NUM          0
  41
  42
  43 /*
  44  * IFC Definitions
  45  */
  46 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  47 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  48 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  49 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  50
  51 #define CONFIG_SYS_NOR0_CSPR                                    \
  52         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  53         CSPR_PORT_SIZE_16                                       | \
  54         CSPR_MSEL_NOR                                           | \
  55         CSPR_V)
  56 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  57         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  58         CSPR_PORT_SIZE_16                                       | \
  59         CSPR_MSEL_NOR                                           | \
  60         CSPR_V)
  61 #define CONFIG_SYS_NOR1_CSPR                                    \
  62         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
  63         CSPR_PORT_SIZE_16                                       | \
  64         CSPR_MSEL_NOR                                           | \
  65         CSPR_V)
  66 #define CONFIG_SYS_NOR1_CSPR_EARLY                              \
  67         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
  68         CSPR_PORT_SIZE_16                                       | \
  69         CSPR_MSEL_NOR                                           | \
  70         CSPR_V)
  71 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  72 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  73                                 FTIM0_NOR_TEADC(0x5) | \
  74                                 FTIM0_NOR_TAVDS(0x6) | \
  75                                 FTIM0_NOR_TEAHC(0x5))
  76 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  77                                 FTIM1_NOR_TRAD_NOR(0x1a) | \
  78                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  79 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x8) | \
  80                                 FTIM2_NOR_TCH(0x8) | \
  81                                 FTIM2_NOR_TWPH(0xe) | \
  82                                 FTIM2_NOR_TWP(0x1c))
  83 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  84 #define CONFIG_SYS_IFC_CCR      0x01000000
  85
  86 #ifndef SYS_NO_FLASH
  87 #define CONFIG_SYS_FLASH_QUIET_TEST
  88 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  89
  90 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
  91 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  92 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  93 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  94
  95 #define CONFIG_SYS_FLASH_EMPTY_INFO
  96 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  97                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  98 #endif
  99 #endif
 100
 101 #define CONFIG_NAND_FSL_IFC
 102 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 103 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 104
 105 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 106 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 107                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 108                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 109                                 | CSPR_V)
 110 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 111
 112 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 113                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 114                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 115                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 116                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 117                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 118                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 119
 120 #define CONFIG_SYS_NAND_ONFI_DETECTION
 121
 122 /* ONFI NAND Flash mode0 Timing Params */
 123 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 124                                         FTIM0_NAND_TWP(0x18)   | \
 125                                         FTIM0_NAND_TWCHT(0x07) | \
 126                                         FTIM0_NAND_TWH(0x0a))
 127 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 128                                         FTIM1_NAND_TWBE(0x39)  | \
 129                                         FTIM1_NAND_TRR(0x0e)   | \
 130                                         FTIM1_NAND_TRP(0x18))
 131 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 132                                         FTIM2_NAND_TREH(0x0a) | \
 133                                         FTIM2_NAND_TWHRE(0x1e))
 134 #define CONFIG_SYS_NAND_FTIM3           0x0
 135
 136 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 137 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 138 #define CONFIG_MTD_NAND_VERIFY_WRITE
 139
 140 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 141
 142 #define CONFIG_FSL_QIXIS
 143 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 144 #define QIXIS_LBMAP_SWITCH              6
 145 #define QIXIS_QMAP_MASK                 0xe0
 146 #define QIXIS_QMAP_SHIFT                5
 147 #define QIXIS_LBMAP_MASK                0x0f
 148 #define QIXIS_LBMAP_SHIFT               0
 149 #define QIXIS_LBMAP_DFLTBANK            0x0e
 150 #define QIXIS_LBMAP_ALTBANK             0x2e
 151 #define QIXIS_LBMAP_SD                  0x00
 152 #define QIXIS_LBMAP_EMMC                0x00
 153 #define QIXIS_LBMAP_IFC                 0x00
 154 #define QIXIS_LBMAP_SD_QSPI             0x0e
 155 #define QIXIS_LBMAP_QSPI                0x0e
 156 #define QIXIS_RCW_SRC_IFC               0x25
 157 #define QIXIS_RCW_SRC_SD                0x40
 158 #define QIXIS_RCW_SRC_EMMC              0x41
 159 #define QIXIS_RCW_SRC_QSPI              0x62
 160 #define QIXIS_RST_CTL_RESET             0x41
 161 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 162 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 163 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 164 #define QIXIS_RST_FORCE_MEM             0x01
 165 #define QIXIS_STAT_PRES1                0xb
 166 #define QIXIS_SDID_MASK                 0x07
 167 #define QIXIS_ESDHC_NO_ADAPTER          0x7
 168
 169 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 170 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 171                                         | CSPR_PORT_SIZE_8 \
 172                                         | CSPR_MSEL_GPCM \
 173                                         | CSPR_V)
 174 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 175                                         | CSPR_PORT_SIZE_8 \
 176                                         | CSPR_MSEL_GPCM \
 177                                         | CSPR_V)
 178
 179 #define SYS_FPGA_AMASK          IFC_AMASK(64 * 1024)
 180 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 181 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 182 #else
 183 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(12)
 184 #endif
 185 /* QIXIS Timing parameters*/
 186 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 187                                         FTIM0_GPCM_TEADC(0x0e) | \
 188                                         FTIM0_GPCM_TEAHC(0x0e))
 189 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 190                                         FTIM1_GPCM_TRAD(0x3f))
 191 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 192                                         FTIM2_GPCM_TCH(0xf) | \
 193                                         FTIM2_GPCM_TWP(0x3E))
 194 #define SYS_FPGA_CS_FTIM3       0x0
 195
 196 #ifdef CONFIG_TFABOOT
 197 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 198 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 199 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 200 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 201 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 202 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 203 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 204 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 205 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 206 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 207 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 208 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 209 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 210 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 211 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 212 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 213 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 214 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 215 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 216 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 217 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 218 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 219 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 220 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 221 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 222 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 223 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 224 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 225 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 226 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 227 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 228 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 229 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 230 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 231 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 232 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 233 #else
 234 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 235 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 236 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 237 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 238 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 239 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 240 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 241 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 242 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 243 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 244 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 245 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 246 #define CONFIG_SYS_AMASK2               SYS_FPGA_AMASK
 247 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 248 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 249 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 250 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 251 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 252 #else
 253 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 254 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 255 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 256 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 257 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 258 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 259 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 260 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 261 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 262 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 263 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR_EARLY
 264 #define CONFIG_SYS_CSPR1_FINAL          CONFIG_SYS_NOR1_CSPR
 265 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK_EARLY
 266 #define CONFIG_SYS_AMASK1_FINAL         CONFIG_SYS_NOR_AMASK
 267 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 268 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 269 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 270 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 271 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 272 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 273 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 274 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 275 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 276 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 277 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 278 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 279 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 280 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 281 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 282 #define CONFIG_SYS_CSPR3_FINAL          SYS_FPGA_CSPR_FINAL
 283 #define CONFIG_SYS_AMASK3               SYS_FPGA_AMASK
 284 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 285 #define CONFIG_SYS_CS3_FTIM0            SYS_FPGA_CS_FTIM0
 286 #define CONFIG_SYS_CS3_FTIM1            SYS_FPGA_CS_FTIM1
 287 #define CONFIG_SYS_CS3_FTIM2            SYS_FPGA_CS_FTIM2
 288 #define CONFIG_SYS_CS3_FTIM3            SYS_FPGA_CS_FTIM3
 289 #endif
 290 #endif
 291
 292 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 293
 294 /*
 295  * I2C bus multiplexer
 296  */
 297 #define I2C_MUX_PCA_ADDR_PRI            0x77
 298 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 299 #define I2C_RETIMER_ADDR                0x18
 300 #define I2C_RETIMER_ADDR2               0x19
 301 #define I2C_MUX_CH_DEFAULT              0x8
 302 #define I2C_MUX_CH5                     0xD
 303
 304 #define I2C_MUX_CH_VOL_MONITOR          0xA
 305
 306 /* Voltage monitor on channel 2*/
 307 #define I2C_VOL_MONITOR_ADDR           0x63
 308 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 309 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 310 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 311 #define I2C_SVDD_MONITOR_ADDR           0x4F
 312
 313 #define CONFIG_VID_FLS_ENV              "ls1088aqds_vdd_mv"
 314 #define CONFIG_VID
 315
 316 /* The lowest and highest voltage allowed for LS1088AQDS */
 317 #define VDD_MV_MIN                      819
 318 #define VDD_MV_MAX                      1212
 319
 320 #define CONFIG_VOL_MONITOR_LTC3882_SET
 321 #define CONFIG_VOL_MONITOR_LTC3882_READ
 322
 323 #define PWM_CHANNEL0                    0x0
 324
 325 /*
 326 * RTC configuration
 327 */
 328 #define RTC
 329 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 330
 331 /* EEPROM */
 332 #define CONFIG_SYS_I2C_EEPROM_NXID
 333 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 334
 335 #ifdef CONFIG_FSL_DSPI
 336 #define CONFIG_SPI_FLASH_STMICRO
 337 #define CONFIG_SPI_FLASH_SST
 338 #define CONFIG_SPI_FLASH_EON
 339 #if !defined(CONFIG_TFABOOT) && \
 340         !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 341 #endif
 342 #endif
 343
 344 #ifdef CONFIG_SPL_BUILD
 345 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 346 #else
 347 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 348 #endif
 349
 350 #define CONFIG_FSL_MEMAC
 351
 352 /*  MMC  */
 353 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
 354         QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
 355
 356 #define COMMON_ENV \
 357         "kernelheader_addr_r=0x80200000\0"      \
 358         "fdtheader_addr_r=0x80100000\0"         \
 359         "kernel_addr_r=0x81000000\0"            \
 360         "fdt_addr_r=0x90000000\0"               \
 361         "load_addr=0xa0000000\0"
 362
 363 /* Initial environment variables */
 364 #ifdef CONFIG_NXP_ESBC
 365 #undef CONFIG_EXTRA_ENV_SETTINGS
 366 #define CONFIG_EXTRA_ENV_SETTINGS               \
 367         COMMON_ENV                              \
 368         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 369         "loadaddr=0x90100000\0"                 \
 370         "kernel_addr=0x100000\0"                \
 371         "ramdisk_addr=0x800000\0"               \
 372         "ramdisk_size=0x2000000\0"              \
 373         "fdt_high=0xa0000000\0"                 \
 374         "initrd_high=0xffffffffffffffff\0"      \
 375         "kernel_start=0x1000000\0"              \
 376         "kernel_load=0xa0000000\0"              \
 377         "kernel_size=0x2800000\0"               \
 378         "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;"  \
 379         "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
 380         "sf read 0xa0e00000 0xe00000 0x100000;" \
 381         "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;"  \
 382         "fsl_mc start mc 0xa0a00000 0xa0e00000\0"                       \
 383         "mcmemsize=0x70000000 \0"
 384 #else /* if !(CONFIG_NXP_ESBC) */
 385 #ifdef CONFIG_TFABOOT
 386 #define QSPI_MC_INIT_CMD                                \
 387         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 388         "sf read 0x80e00000 0xE00000 0x100000;" \
 389         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 390 #define SD_MC_INIT_CMD                          \
 391         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 392         "mmc read 0x80e00000 0x7000 0x800;" \
 393         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 394 #define IFC_MC_INIT_CMD                         \
 395         "fsl_mc start mc 0x580A00000 0x580E00000\0"
 396
 397 #undef CONFIG_EXTRA_ENV_SETTINGS
 398 #define CONFIG_EXTRA_ENV_SETTINGS               \
 399         COMMON_ENV                              \
 400         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 401         "loadaddr=0x90100000\0"                 \
 402         "kernel_addr=0x100000\0"                \
 403         "kernel_addr_sd=0x800\0"                \
 404         "ramdisk_addr=0x800000\0"               \
 405         "ramdisk_size=0x2000000\0"              \
 406         "fdt_high=0xa0000000\0"                 \
 407         "initrd_high=0xffffffffffffffff\0"      \
 408         "kernel_start=0x1000000\0"              \
 409         "kernel_start_sd=0x8000\0"              \
 410         "kernel_load=0xa0000000\0"              \
 411         "kernel_size=0x2800000\0"               \
 412         "kernel_size_sd=0x14000\0"               \
 413         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 414         "sf read 0x80e00000 0xE00000 0x100000;" \
 415         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 416         "mcmemsize=0x70000000 \0"               \
 417         "BOARD=ls1088aqds\0" \
 418         "scriptaddr=0x80000000\0"               \
 419         "scripthdraddr=0x80080000\0"            \
 420         BOOTENV                                 \
 421         "boot_scripts=ls1088aqds_boot.scr\0"    \
 422         "boot_script_hdr=hdr_ls1088aqds_bs.out\0"       \
 423         "scan_dev_for_boot_part="               \
 424                 "part list ${devtype} ${devnum} devplist; "     \
 425                 "env exists devplist || setenv devplist 1; "    \
 426                 "for distro_bootpart in ${devplist}; do "       \
 427                         "if fstype ${devtype} "                 \
 428                                 "${devnum}:${distro_bootpart} " \
 429                                 "bootfstype; then "             \
 430                                 "run scan_dev_for_boot; "       \
 431                         "fi; "                                  \
 432                 "done\0"                                        \
 433         "boot_a_script="                                        \
 434                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 435                 "${scriptaddr} ${prefix}${script}; "            \
 436         "env exists secureboot && load ${devtype} "             \
 437                 "${devnum}:${distro_bootpart} "                 \
 438                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 439                 "env exists secureboot "                        \
 440                 "&& esbc_validate ${scripthdraddr};"            \
 441                 "source ${scriptaddr}\0"                        \
 442         "qspi_bootcmd=echo Trying load from qspi..; " \
 443                 "sf probe 0:0; " \
 444                 "sf read 0x80001000 0xd00000 0x100000; " \
 445                 "fsl_mc lazyapply dpl 0x80001000 && " \
 446                 "sf read $kernel_load $kernel_start " \
 447                 "$kernel_size && bootm $kernel_load#$BOARD\0" \
 448         "sd_bootcmd=echo Trying load from sd card..; " \
 449                 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
 450                 "fsl_mc lazyapply dpl 0x80001000 && " \
 451                 "mmc read $kernel_load $kernel_start_sd " \
 452                 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
 453         "nor_bootcmd=echo Trying load from nor..; " \
 454                 "fsl_mc lazyapply dpl 0x580d00000 && " \
 455                 "cp.b $kernel_start $kernel_load " \
 456                 "$kernel_size && bootm $kernel_load#$BOARD\0"
 457 #else
 458 #if defined(CONFIG_QSPI_BOOT)
 459 #undef CONFIG_EXTRA_ENV_SETTINGS
 460 #define CONFIG_EXTRA_ENV_SETTINGS               \
 461         COMMON_ENV                              \
 462         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 463         "loadaddr=0x90100000\0"                 \
 464         "kernel_addr=0x100000\0"                \
 465         "ramdisk_addr=0x800000\0"               \
 466         "ramdisk_size=0x2000000\0"              \
 467         "fdt_high=0xa0000000\0"                 \
 468         "initrd_high=0xffffffffffffffff\0"      \
 469         "kernel_start=0x1000000\0"              \
 470         "kernel_load=0xa0000000\0"              \
 471         "kernel_size=0x2800000\0"               \
 472         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 473         "sf read 0x80e00000 0xE00000 0x100000;" \
 474         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 475         "mcmemsize=0x70000000 \0"
 476 #elif defined(CONFIG_SD_BOOT)
 477 #undef CONFIG_EXTRA_ENV_SETTINGS
 478 #define CONFIG_EXTRA_ENV_SETTINGS               \
 479         COMMON_ENV                              \
 480         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 481         "loadaddr=0x90100000\0"                 \
 482         "kernel_addr=0x800\0"                \
 483         "ramdisk_addr=0x800000\0"               \
 484         "ramdisk_size=0x2000000\0"              \
 485         "fdt_high=0xa0000000\0"                 \
 486         "initrd_high=0xffffffffffffffff\0"      \
 487         "kernel_start=0x8000\0"              \
 488         "kernel_load=0xa0000000\0"              \
 489         "kernel_size=0x14000\0"               \
 490         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
 491         "mmc read 0x80e00000 0x7000 0x800;" \
 492         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 493         "mcmemsize=0x70000000 \0"
 494 #else   /* NOR BOOT */
 495 #undef CONFIG_EXTRA_ENV_SETTINGS
 496 #define CONFIG_EXTRA_ENV_SETTINGS               \
 497         COMMON_ENV                              \
 498         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 499         "loadaddr=0x90100000\0"                 \
 500         "kernel_addr=0x100000\0"                \
 501         "ramdisk_addr=0x800000\0"               \
 502         "ramdisk_size=0x2000000\0"              \
 503         "fdt_high=0xa0000000\0"                 \
 504         "initrd_high=0xffffffffffffffff\0"      \
 505         "kernel_start=0x1000000\0"              \
 506         "kernel_load=0xa0000000\0"              \
 507         "kernel_size=0x2800000\0"               \
 508         "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0"   \
 509         "mcmemsize=0x70000000 \0"
 510 #endif
 511 #endif /* CONFIG_TFABOOT */
 512 #endif /* CONFIG_NXP_ESBC */
 513
 514 #ifdef CONFIG_TFABOOT
 515 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "   \
 516                            "env exists secureboot && esbc_halt;;"
 517 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "     \
 518                            "env exists secureboot && esbc_halt;;"
 519 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "   \
 520                            "env exists secureboot && esbc_halt;;"
 521 #endif
 522
 523 #ifdef CONFIG_FSL_MC_ENET
 524 #define CONFIG_FSL_MEMAC
 525 #define RGMII_PHY1_ADDR         0x1
 526 #define RGMII_PHY2_ADDR         0x2
 527 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 528 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
 529 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 530 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 531
 532 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
 533 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
 534 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
 535 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
 536 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
 537 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
 538 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
 539 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
 540 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
 541 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
 542 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
 543 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
 544 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 545 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
 546 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 547 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 548
 549 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 550 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 551
 552 #endif
 553
 554 #define BOOT_TARGET_DEVICES(func) \
 555         func(USB, usb, 0) \
 556         func(MMC, mmc, 0) \
 557         func(SCSI, scsi, 0) \
 558         func(DHCP, dhcp, na)
 559 #include <config_distro_bootcmd.h>
 560
 561 #include <asm/fsl_secure_boot.h>
 562
 563 #endif /* __LS1088A_QDS_H */