4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1088A_QDS_H
8 #define __LS1088A_QDS_H
10 #include "ls1088a_common.h"
14 unsigned long get_board_sys_clk(void);
15 unsigned long get_board_ddr_clk(void);
19 #if defined(CONFIG_QSPI_BOOT)
20 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
21 #define CONFIG_ENV_SECT_SIZE 0x40000
22 #elif defined(CONFIG_SD_BOOT)
23 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
24 #define CONFIG_SYS_MMC_ENV_DEV 0
25 #define CONFIG_ENV_SIZE 0x2000
27 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
28 #define CONFIG_ENV_SECT_SIZE 0x20000
29 #define CONFIG_ENV_SIZE 0x20000
32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
33 #define CONFIG_QIXIS_I2C_ACCESS
36 #undef CONFIG_CMD_IMLS
37 #define CONFIG_SYS_CLK_FREQ 100000000
38 #define CONFIG_DDR_CLK_FREQ 100000000
40 #define CONFIG_QIXIS_I2C_ACCESS
41 #define CONFIG_SYS_I2C_EARLY_INIT
42 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
43 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
46 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
47 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
49 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
51 #define CONFIG_DDR_SPD
52 #define CONFIG_DDR_ECC
53 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
55 #define SPD_EEPROM_ADDRESS 0x51
56 #define CONFIG_SYS_SPD_BUS_NUM 0
62 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
63 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
64 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
65 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
67 #define CONFIG_SYS_NOR0_CSPR \
68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
72 #define CONFIG_SYS_NOR0_CSPR_EARLY \
73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
77 #define CONFIG_SYS_NOR1_CSPR \
78 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
82 #define CONFIG_SYS_NOR1_CSPR_EARLY \
83 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
87 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
88 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
89 FTIM0_NOR_TEADC(0x5) | \
90 FTIM0_NOR_TAVDS(0x6) | \
92 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
93 FTIM1_NOR_TRAD_NOR(0x1a) | \
94 FTIM1_NOR_TSEQRAD_NOR(0x13))
95 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
96 FTIM2_NOR_TCH(0x8) | \
97 FTIM2_NOR_TWPH(0xe) | \
99 #define CONFIG_SYS_NOR_FTIM3 0x04000000
100 #define CONFIG_SYS_IFC_CCR 0x01000000
103 #define CONFIG_FLASH_CFI_DRIVER
104 #define CONFIG_SYS_FLASH_CFI
105 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
106 #define CONFIG_SYS_FLASH_QUIET_TEST
107 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
109 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
110 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
111 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
112 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
114 #define CONFIG_SYS_FLASH_EMPTY_INFO
115 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
116 CONFIG_SYS_FLASH_BASE + 0x40000000}
120 #define CONFIG_NAND_FSL_IFC
121 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
122 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
124 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
125 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
126 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
127 | CSPR_MSEL_NAND /* MSEL = NAND */ \
129 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
131 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
132 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
133 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
134 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
135 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
136 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
137 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
139 #define CONFIG_SYS_NAND_ONFI_DETECTION
141 /* ONFI NAND Flash mode0 Timing Params */
142 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
143 FTIM0_NAND_TWP(0x18) | \
144 FTIM0_NAND_TWCHT(0x07) | \
145 FTIM0_NAND_TWH(0x0a))
146 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
147 FTIM1_NAND_TWBE(0x39) | \
148 FTIM1_NAND_TRR(0x0e) | \
149 FTIM1_NAND_TRP(0x18))
150 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
151 FTIM2_NAND_TREH(0x0a) | \
152 FTIM2_NAND_TWHRE(0x1e))
153 #define CONFIG_SYS_NAND_FTIM3 0x0
155 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
156 #define CONFIG_SYS_MAX_NAND_DEVICE 1
157 #define CONFIG_MTD_NAND_VERIFY_WRITE
158 #define CONFIG_CMD_NAND
160 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
162 #define CONFIG_FSL_QIXIS
163 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
164 #define QIXIS_LBMAP_SWITCH 6
165 #define QIXIS_QMAP_MASK 0xe0
166 #define QIXIS_QMAP_SHIFT 5
167 #define QIXIS_LBMAP_MASK 0x0f
168 #define QIXIS_LBMAP_SHIFT 0
169 #define QIXIS_LBMAP_DFLTBANK 0x0e
170 #define QIXIS_LBMAP_ALTBANK 0x2e
171 #define QIXIS_LBMAP_SD 0x00
172 #define QIXIS_LBMAP_EMMC 0x00
173 #define QIXIS_LBMAP_IFC 0x00
174 #define QIXIS_LBMAP_SD_QSPI 0x0e
175 #define QIXIS_LBMAP_QSPI 0x0e
176 #define QIXIS_RCW_SRC_IFC 0x25
177 #define QIXIS_RCW_SRC_SD 0x40
178 #define QIXIS_RCW_SRC_EMMC 0x41
179 #define QIXIS_RCW_SRC_QSPI 0x62
180 #define QIXIS_RST_CTL_RESET 0x41
181 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
182 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
183 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
184 #define QIXIS_RST_FORCE_MEM 0x01
185 #define QIXIS_STAT_PRES1 0xb
186 #define QIXIS_SDID_MASK 0x07
187 #define QIXIS_ESDHC_NO_ADAPTER 0x7
189 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
190 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
194 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
199 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
200 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
201 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
203 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
205 /* QIXIS Timing parameters*/
206 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
207 FTIM0_GPCM_TEADC(0x0e) | \
208 FTIM0_GPCM_TEAHC(0x0e))
209 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
210 FTIM1_GPCM_TRAD(0x3f))
211 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
212 FTIM2_GPCM_TCH(0xf) | \
213 FTIM2_GPCM_TWP(0x3E))
214 #define SYS_FPGA_CS_FTIM3 0x0
216 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
217 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
218 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
219 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
220 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
221 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
222 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
223 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
224 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
225 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
226 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
227 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
228 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
229 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
230 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
231 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
232 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
233 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
235 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
236 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
237 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
238 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
239 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
240 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
241 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
242 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
243 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
244 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
245 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
246 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
247 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
248 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
249 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
250 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
251 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
252 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
253 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
254 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
255 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
256 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
257 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
258 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
259 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
260 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
261 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
262 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
263 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
264 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
265 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
266 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
267 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
268 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
269 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
270 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
273 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
276 * I2C bus multiplexer
278 #define I2C_MUX_PCA_ADDR_PRI 0x77
279 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
280 #define I2C_RETIMER_ADDR 0x18
281 #define I2C_RETIMER_ADDR2 0x19
282 #define I2C_MUX_CH_DEFAULT 0x8
283 #define I2C_MUX_CH5 0xD
285 #define I2C_MUX_CH_VOL_MONITOR 0xA
287 /* Voltage monitor on channel 2*/
288 #define I2C_VOL_MONITOR_ADDR 0x63
289 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
290 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
291 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
292 #define I2C_SVDD_MONITOR_ADDR 0x4F
294 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
297 /* The lowest and highest voltage allowed for LS1088AQDS */
298 #define VDD_MV_MIN 819
299 #define VDD_MV_MAX 1212
301 #define CONFIG_VOL_MONITOR_LTC3882_SET
302 #define CONFIG_VOL_MONITOR_LTC3882_READ
304 /* PM Bus commands code for LTC3882*/
305 #define PMBUS_CMD_PAGE 0x0
306 #define PMBUS_CMD_READ_VOUT 0x8B
307 #define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
308 #define PMBUS_CMD_VOUT_COMMAND 0x21
310 #define PWM_CHANNEL0 0x0
316 #define CONFIG_RTC_PCF8563 1
317 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
318 #define CONFIG_CMD_DATE
321 #define CONFIG_ID_EEPROM
322 #define CONFIG_SYS_I2C_EEPROM_NXID
323 #define CONFIG_SYS_EEPROM_BUS_NUM 0
324 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
325 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
327 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
330 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
331 #define CONFIG_FSL_QSPI
332 #define FSL_QSPI_FLASH_SIZE (1 << 26)
333 #define FSL_QSPI_FLASH_NUM 2
337 #ifdef CONFIG_FSL_DSPI
338 #define CONFIG_SPI_FLASH_STMICRO
339 #define CONFIG_SPI_FLASH_SST
340 #define CONFIG_SPI_FLASH_EON
341 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
342 #define CONFIG_SF_DEFAULT_BUS 1
343 #define CONFIG_SF_DEFAULT_CS 0
347 #define CONFIG_CMD_MEMINFO
348 #define CONFIG_SYS_MEMTEST_START 0x80000000
349 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
351 #ifdef CONFIG_SPL_BUILD
352 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
354 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
357 #define CONFIG_FSL_MEMAC
360 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
361 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
362 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
364 /* Initial environment variables */
365 #ifdef CONFIG_SECURE_BOOT
366 #undef CONFIG_EXTRA_ENV_SETTINGS
367 #define CONFIG_EXTRA_ENV_SETTINGS \
368 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
369 "loadaddr=0x90100000\0" \
370 "kernel_addr=0x100000\0" \
371 "ramdisk_addr=0x800000\0" \
372 "ramdisk_size=0x2000000\0" \
373 "fdt_high=0xa0000000\0" \
374 "initrd_high=0xffffffffffffffff\0" \
375 "kernel_start=0x1000000\0" \
376 "kernel_load=0xa0000000\0" \
377 "kernel_size=0x2800000\0" \
378 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
379 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
380 "sf read 0xa0e00000 0xe00000 0x100000;" \
381 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
382 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
383 "mcmemsize=0x70000000 \0"
384 #else /* if !(CONFIG_SECURE_BOOT) */
385 #if defined(CONFIG_QSPI_BOOT)
386 #undef CONFIG_EXTRA_ENV_SETTINGS
387 #define CONFIG_EXTRA_ENV_SETTINGS \
388 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
389 "loadaddr=0x90100000\0" \
390 "kernel_addr=0x100000\0" \
391 "ramdisk_addr=0x800000\0" \
392 "ramdisk_size=0x2000000\0" \
393 "fdt_high=0xa0000000\0" \
394 "initrd_high=0xffffffffffffffff\0" \
395 "kernel_start=0x1000000\0" \
396 "kernel_load=0xa0000000\0" \
397 "kernel_size=0x2800000\0" \
398 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
399 "sf read 0x80100000 0xE00000 0x100000;" \
400 "fsl_mc start mc 0x80000000 0x80100000\0" \
401 "mcmemsize=0x70000000 \0"
402 #elif defined(CONFIG_SD_BOOT)
403 #undef CONFIG_EXTRA_ENV_SETTINGS
404 #define CONFIG_EXTRA_ENV_SETTINGS \
405 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
406 "loadaddr=0x90100000\0" \
407 "kernel_addr=0x800\0" \
408 "ramdisk_addr=0x800000\0" \
409 "ramdisk_size=0x2000000\0" \
410 "fdt_high=0xa0000000\0" \
411 "initrd_high=0xffffffffffffffff\0" \
412 "kernel_start=0x8000\0" \
413 "kernel_load=0xa0000000\0" \
414 "kernel_size=0x14000\0" \
415 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
416 "mmc read 0x80100000 0x7000 0x800;" \
417 "fsl_mc start mc 0x80000000 0x80100000\0" \
418 "mcmemsize=0x70000000 \0"
420 #undef CONFIG_EXTRA_ENV_SETTINGS
421 #define CONFIG_EXTRA_ENV_SETTINGS \
422 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
423 "loadaddr=0x90100000\0" \
424 "kernel_addr=0x100000\0" \
425 "ramdisk_addr=0x800000\0" \
426 "ramdisk_size=0x2000000\0" \
427 "fdt_high=0xa0000000\0" \
428 "initrd_high=0xffffffffffffffff\0" \
429 "kernel_start=0x1000000\0" \
430 "kernel_load=0xa0000000\0" \
431 "kernel_size=0x2800000\0" \
432 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
433 "mcmemsize=0x70000000 \0"
435 #endif /* CONFIG_SECURE_BOOT */
437 #ifdef CONFIG_FSL_MC_ENET
438 #define CONFIG_FSL_MEMAC
439 #define CONFIG_PHYLIB
440 #define CONFIG_PHYLIB_10G
441 #define CONFIG_PHY_VITESSE
442 #define CONFIG_PHY_REALTEK
443 #define CONFIG_PHY_TERANETICS
444 #define RGMII_PHY1_ADDR 0x1
445 #define RGMII_PHY2_ADDR 0x2
446 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
447 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
448 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
449 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
451 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
452 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
453 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
454 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
455 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
456 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
457 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
458 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
459 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
460 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
461 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
462 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
463 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
464 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
465 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
466 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
468 #define CONFIG_MII /* MII PHY management */
469 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
470 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
474 #define BOOT_TARGET_DEVICES(func) \
477 func(SCSI, scsi, 0) \
479 #include <config_distro_bootcmd.h>
481 #include <asm/fsl_secure_boot.h>
483 #endif /* __LS1088A_QDS_H */