1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
13 unsigned long get_board_sys_clk(void);
16 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
17 #define CONFIG_QIXIS_I2C_ACCESS
20 #define CONFIG_SYS_CLK_FREQ 100000000
22 #define CONFIG_QIXIS_I2C_ACCESS
23 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
27 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
29 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
31 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
32 #define SPD_EEPROM_ADDRESS 0x51
33 #define CONFIG_SYS_SPD_BUS_NUM 0
39 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
40 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
41 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
42 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
44 #define CONFIG_SYS_NOR0_CSPR \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
49 #define CONFIG_SYS_NOR0_CSPR_EARLY \
50 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
54 #define CONFIG_SYS_NOR1_CSPR \
55 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
59 #define CONFIG_SYS_NOR1_CSPR_EARLY \
60 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
64 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
65 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
66 FTIM0_NOR_TEADC(0x5) | \
67 FTIM0_NOR_TAVDS(0x6) | \
69 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
70 FTIM1_NOR_TRAD_NOR(0x1a) | \
71 FTIM1_NOR_TSEQRAD_NOR(0x13))
72 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
73 FTIM2_NOR_TCH(0x8) | \
74 FTIM2_NOR_TWPH(0xe) | \
76 #define CONFIG_SYS_NOR_FTIM3 0x04000000
77 #define CONFIG_SYS_IFC_CCR 0x01000000
80 #define CONFIG_SYS_FLASH_QUIET_TEST
81 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
83 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
84 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
85 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
86 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
88 #define CONFIG_SYS_FLASH_EMPTY_INFO
89 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
90 CONFIG_SYS_FLASH_BASE + 0x40000000}
94 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
95 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
97 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
98 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
99 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
100 | CSPR_MSEL_NAND /* MSEL = NAND */ \
102 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
104 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
105 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
106 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
107 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
108 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
109 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
110 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
112 /* ONFI NAND Flash mode0 Timing Params */
113 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
114 FTIM0_NAND_TWP(0x18) | \
115 FTIM0_NAND_TWCHT(0x07) | \
116 FTIM0_NAND_TWH(0x0a))
117 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
118 FTIM1_NAND_TWBE(0x39) | \
119 FTIM1_NAND_TRR(0x0e) | \
120 FTIM1_NAND_TRP(0x18))
121 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
122 FTIM2_NAND_TREH(0x0a) | \
123 FTIM2_NAND_TWHRE(0x1e))
124 #define CONFIG_SYS_NAND_FTIM3 0x0
126 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
127 #define CONFIG_SYS_MAX_NAND_DEVICE 1
128 #define CONFIG_MTD_NAND_VERIFY_WRITE
130 #define CONFIG_FSL_QIXIS
131 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
132 #define QIXIS_LBMAP_SWITCH 6
133 #define QIXIS_QMAP_MASK 0xe0
134 #define QIXIS_QMAP_SHIFT 5
135 #define QIXIS_LBMAP_MASK 0x0f
136 #define QIXIS_LBMAP_SHIFT 0
137 #define QIXIS_LBMAP_DFLTBANK 0x0e
138 #define QIXIS_LBMAP_ALTBANK 0x2e
139 #define QIXIS_LBMAP_SD 0x00
140 #define QIXIS_LBMAP_EMMC 0x00
141 #define QIXIS_LBMAP_IFC 0x00
142 #define QIXIS_LBMAP_SD_QSPI 0x0e
143 #define QIXIS_LBMAP_QSPI 0x0e
144 #define QIXIS_RCW_SRC_IFC 0x25
145 #define QIXIS_RCW_SRC_SD 0x40
146 #define QIXIS_RCW_SRC_EMMC 0x41
147 #define QIXIS_RCW_SRC_QSPI 0x62
148 #define QIXIS_RST_CTL_RESET 0x41
149 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
150 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
151 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
152 #define QIXIS_RST_FORCE_MEM 0x01
153 #define QIXIS_STAT_PRES1 0xb
154 #define QIXIS_SDID_MASK 0x07
155 #define QIXIS_ESDHC_NO_ADAPTER 0x7
157 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
158 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
162 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
167 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
168 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
169 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
171 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
173 /* QIXIS Timing parameters*/
174 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
175 FTIM0_GPCM_TEADC(0x0e) | \
176 FTIM0_GPCM_TEAHC(0x0e))
177 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
178 FTIM1_GPCM_TRAD(0x3f))
179 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
180 FTIM2_GPCM_TCH(0xf) | \
181 FTIM2_GPCM_TWP(0x3E))
182 #define SYS_FPGA_CS_FTIM3 0x0
184 #ifdef CONFIG_TFABOOT
185 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
186 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
187 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
188 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
189 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
190 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
191 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
192 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
193 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
194 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
195 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
196 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
197 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
198 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
199 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
200 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
201 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
202 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
203 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
204 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
205 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
206 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
207 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
208 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
209 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
210 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
211 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
212 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
213 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
214 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
215 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
216 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
217 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
218 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
219 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
220 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
222 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
223 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
224 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
225 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
226 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
227 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
228 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
229 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
230 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
231 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
232 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
233 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
234 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
235 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
236 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
237 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
238 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
239 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
241 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
242 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
243 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
244 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
245 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
246 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
247 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
248 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
249 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
250 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
251 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
252 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
253 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
254 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
255 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
256 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
257 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
258 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
259 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
260 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
261 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
262 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
263 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
264 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
265 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
266 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
267 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
268 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
269 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
270 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
271 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
272 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
273 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
274 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
275 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
276 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
280 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
283 * I2C bus multiplexer
285 #define I2C_MUX_PCA_ADDR_PRI 0x77
286 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
287 #define I2C_RETIMER_ADDR 0x18
288 #define I2C_RETIMER_ADDR2 0x19
289 #define I2C_MUX_CH_DEFAULT 0x8
290 #define I2C_MUX_CH5 0xD
292 #define I2C_MUX_CH_VOL_MONITOR 0xA
294 /* Voltage monitor on channel 2*/
295 #define I2C_VOL_MONITOR_ADDR 0x63
296 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
297 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
298 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
299 #define I2C_SVDD_MONITOR_ADDR 0x4F
301 /* The lowest and highest voltage allowed for LS1088AQDS */
302 #define VDD_MV_MIN 819
303 #define VDD_MV_MAX 1212
305 #define PWM_CHANNEL0 0x0
311 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
314 #define CONFIG_SYS_I2C_EEPROM_NXID
315 #define CONFIG_SYS_EEPROM_BUS_NUM 0
317 #ifdef CONFIG_FSL_DSPI
318 #if !defined(CONFIG_TFABOOT) && \
319 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
323 #ifdef CONFIG_SPL_BUILD
324 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
326 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
329 #define CONFIG_FSL_MEMAC
332 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
333 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
336 "kernelheader_addr_r=0x80200000\0" \
337 "fdtheader_addr_r=0x80100000\0" \
338 "kernel_addr_r=0x81000000\0" \
339 "fdt_addr_r=0x90000000\0" \
340 "load_addr=0xa0000000\0"
342 /* Initial environment variables */
343 #ifdef CONFIG_NXP_ESBC
344 #undef CONFIG_EXTRA_ENV_SETTINGS
345 #define CONFIG_EXTRA_ENV_SETTINGS \
347 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
348 "loadaddr=0x90100000\0" \
349 "kernel_addr=0x100000\0" \
350 "ramdisk_addr=0x800000\0" \
351 "ramdisk_size=0x2000000\0" \
352 "fdt_high=0xa0000000\0" \
353 "initrd_high=0xffffffffffffffff\0" \
354 "kernel_start=0x1000000\0" \
355 "kernel_load=0xa0000000\0" \
356 "kernel_size=0x2800000\0" \
357 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
358 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
359 "sf read 0xa0e00000 0xe00000 0x100000;" \
360 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
361 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
362 "mcmemsize=0x70000000 \0"
363 #else /* if !(CONFIG_NXP_ESBC) */
364 #ifdef CONFIG_TFABOOT
365 #define QSPI_MC_INIT_CMD \
366 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
367 "sf read 0x80e00000 0xE00000 0x100000;" \
368 "fsl_mc start mc 0x80a00000 0x80e00000\0"
369 #define SD_MC_INIT_CMD \
370 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
371 "mmc read 0x80e00000 0x7000 0x800;" \
372 "fsl_mc start mc 0x80a00000 0x80e00000\0"
373 #define IFC_MC_INIT_CMD \
374 "fsl_mc start mc 0x580A00000 0x580E00000\0"
376 #undef CONFIG_EXTRA_ENV_SETTINGS
377 #define CONFIG_EXTRA_ENV_SETTINGS \
379 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
380 "loadaddr=0x90100000\0" \
381 "kernel_addr=0x100000\0" \
382 "kernel_addr_sd=0x800\0" \
383 "ramdisk_addr=0x800000\0" \
384 "ramdisk_size=0x2000000\0" \
385 "fdt_high=0xa0000000\0" \
386 "initrd_high=0xffffffffffffffff\0" \
387 "kernel_start=0x1000000\0" \
388 "kernel_start_sd=0x8000\0" \
389 "kernel_load=0xa0000000\0" \
390 "kernel_size=0x2800000\0" \
391 "kernel_size_sd=0x14000\0" \
392 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
393 "sf read 0x80e00000 0xE00000 0x100000;" \
394 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
395 "mcmemsize=0x70000000 \0" \
396 "BOARD=ls1088aqds\0" \
397 "scriptaddr=0x80000000\0" \
398 "scripthdraddr=0x80080000\0" \
400 "boot_scripts=ls1088aqds_boot.scr\0" \
401 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
402 "scan_dev_for_boot_part=" \
403 "part list ${devtype} ${devnum} devplist; " \
404 "env exists devplist || setenv devplist 1; " \
405 "for distro_bootpart in ${devplist}; do " \
406 "if fstype ${devtype} " \
407 "${devnum}:${distro_bootpart} " \
408 "bootfstype; then " \
409 "run scan_dev_for_boot; " \
413 "load ${devtype} ${devnum}:${distro_bootpart} " \
414 "${scriptaddr} ${prefix}${script}; " \
415 "env exists secureboot && load ${devtype} " \
416 "${devnum}:${distro_bootpart} " \
417 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
418 "env exists secureboot " \
419 "&& esbc_validate ${scripthdraddr};" \
420 "source ${scriptaddr}\0" \
421 "qspi_bootcmd=echo Trying load from qspi..; " \
423 "sf read 0x80001000 0xd00000 0x100000; " \
424 "fsl_mc lazyapply dpl 0x80001000 && " \
425 "sf read $kernel_load $kernel_start " \
426 "$kernel_size && bootm $kernel_load#$BOARD\0" \
427 "sd_bootcmd=echo Trying load from sd card..; " \
428 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
429 "fsl_mc lazyapply dpl 0x80001000 && " \
430 "mmc read $kernel_load $kernel_start_sd " \
431 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
432 "nor_bootcmd=echo Trying load from nor..; " \
433 "fsl_mc lazyapply dpl 0x580d00000 && " \
434 "cp.b $kernel_start $kernel_load " \
435 "$kernel_size && bootm $kernel_load#$BOARD\0"
437 #if defined(CONFIG_QSPI_BOOT)
438 #undef CONFIG_EXTRA_ENV_SETTINGS
439 #define CONFIG_EXTRA_ENV_SETTINGS \
441 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
442 "loadaddr=0x90100000\0" \
443 "kernel_addr=0x100000\0" \
444 "ramdisk_addr=0x800000\0" \
445 "ramdisk_size=0x2000000\0" \
446 "fdt_high=0xa0000000\0" \
447 "initrd_high=0xffffffffffffffff\0" \
448 "kernel_start=0x1000000\0" \
449 "kernel_load=0xa0000000\0" \
450 "kernel_size=0x2800000\0" \
451 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
452 "sf read 0x80e00000 0xE00000 0x100000;" \
453 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
454 "mcmemsize=0x70000000 \0"
455 #elif defined(CONFIG_SD_BOOT)
456 #undef CONFIG_EXTRA_ENV_SETTINGS
457 #define CONFIG_EXTRA_ENV_SETTINGS \
459 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
460 "loadaddr=0x90100000\0" \
461 "kernel_addr=0x800\0" \
462 "ramdisk_addr=0x800000\0" \
463 "ramdisk_size=0x2000000\0" \
464 "fdt_high=0xa0000000\0" \
465 "initrd_high=0xffffffffffffffff\0" \
466 "kernel_start=0x8000\0" \
467 "kernel_load=0xa0000000\0" \
468 "kernel_size=0x14000\0" \
469 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
470 "mmc read 0x80e00000 0x7000 0x800;" \
471 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
472 "mcmemsize=0x70000000 \0"
474 #undef CONFIG_EXTRA_ENV_SETTINGS
475 #define CONFIG_EXTRA_ENV_SETTINGS \
477 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
478 "loadaddr=0x90100000\0" \
479 "kernel_addr=0x100000\0" \
480 "ramdisk_addr=0x800000\0" \
481 "ramdisk_size=0x2000000\0" \
482 "fdt_high=0xa0000000\0" \
483 "initrd_high=0xffffffffffffffff\0" \
484 "kernel_start=0x1000000\0" \
485 "kernel_load=0xa0000000\0" \
486 "kernel_size=0x2800000\0" \
487 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
488 "mcmemsize=0x70000000 \0"
490 #endif /* CONFIG_TFABOOT */
491 #endif /* CONFIG_NXP_ESBC */
493 #ifdef CONFIG_TFABOOT
494 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
495 "env exists secureboot && esbc_halt;;"
496 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
497 "env exists secureboot && esbc_halt;;"
498 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
499 "env exists secureboot && esbc_halt;;"
502 #ifdef CONFIG_FSL_MC_ENET
503 #define CONFIG_FSL_MEMAC
504 #define RGMII_PHY1_ADDR 0x1
505 #define RGMII_PHY2_ADDR 0x2
506 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
507 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
508 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
509 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
511 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
512 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
513 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
514 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
515 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
516 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
517 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
518 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
519 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
520 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
521 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
522 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
523 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
524 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
525 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
526 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
528 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
532 #define BOOT_TARGET_DEVICES(func) \
535 func(SCSI, scsi, 0) \
537 #include <config_distro_bootcmd.h>
539 #include <asm/fsl_secure_boot.h>
541 #endif /* __LS1088A_QDS_H */